root / target-arm / helper.c @ 1de7afc9
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#include "cpu.h" |
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#include "exec/gdbstub.h" |
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#include "helper.h" |
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#include "qemu/host-utils.h" |
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#include "sysemu.h" |
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#include "qemu/bitops.h" |
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|
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#ifndef CONFIG_USER_ONLY
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static inline int get_phys_addr(CPUARMState *env, uint32_t address, |
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int access_type, int is_user, |
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hwaddr *phys_ptr, int *prot,
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target_ulong *page_size); |
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#endif
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|
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static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
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{ |
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int nregs;
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|
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/* VFP data registers are always little-endian. */
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nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
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if (reg < nregs) {
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stfq_le_p(buf, env->vfp.regs[reg]); |
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return 8; |
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} |
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if (arm_feature(env, ARM_FEATURE_NEON)) {
|
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/* Aliases for Q regs. */
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nregs += 16;
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if (reg < nregs) {
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stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); |
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stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); |
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return 16; |
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} |
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} |
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switch (reg - nregs) {
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case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; |
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case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; |
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case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; |
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} |
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return 0; |
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} |
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|
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static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
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{ |
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int nregs;
|
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|
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nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
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if (reg < nregs) {
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env->vfp.regs[reg] = ldfq_le_p(buf); |
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return 8; |
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} |
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if (arm_feature(env, ARM_FEATURE_NEON)) {
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nregs += 16;
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if (reg < nregs) {
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env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); |
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env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); |
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return 16; |
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} |
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} |
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switch (reg - nregs) {
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case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; |
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case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; |
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case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
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} |
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return 0; |
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} |
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|
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static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
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{ |
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env->cp15.c3 = value; |
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tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ |
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return 0; |
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} |
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|
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static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
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{ |
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if (env->cp15.c13_fcse != value) {
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/* Unlike real hardware the qemu TLB uses virtual addresses,
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* not modified virtual addresses, so this causes a TLB flush.
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*/
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tlb_flush(env, 1);
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env->cp15.c13_fcse = value; |
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} |
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return 0; |
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} |
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static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
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/* For VMSA (when not using the LPAE long descriptor page table
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* format) this register includes the ASID, so do a TLB flush.
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* For PMSA it is purely a process ID and no action is needed.
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*/
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tlb_flush(env, 1);
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} |
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env->cp15.c13_context = value; |
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return 0; |
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} |
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|
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static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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/* Invalidate all (TLBIALL) */
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tlb_flush(env, 1);
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return 0; |
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} |
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|
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static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
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tlb_flush_page(env, value & TARGET_PAGE_MASK); |
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return 0; |
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} |
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|
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static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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/* Invalidate by ASID (TLBIASID) */
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tlb_flush(env, value == 0);
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return 0; |
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} |
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|
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static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
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tlb_flush_page(env, value & TARGET_PAGE_MASK); |
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return 0; |
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} |
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|
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static const ARMCPRegInfo cp_reginfo[] = { |
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/* DBGDIDR: just RAZ. In particular this means the "debug architecture
|
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* version" bits will read as a reserved value, which should cause
|
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* Linux to not try to use the debug hardware.
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*/
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{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, |
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.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* MMU Domain access control / MPU write buffer control */
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{ .name = "DACR", .cp = 15, |
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.crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), |
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.resetvalue = 0, .writefn = dacr_write },
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{ .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, |
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), |
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.resetvalue = 0, .writefn = fcse_write },
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{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1, |
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), |
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.resetvalue = 0, .writefn = contextidr_write },
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/* ??? This covers not just the impdef TLB lockdown registers but also
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* some v7VMSA registers relating to TEX remap, so it is overly broad.
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*/
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{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY, |
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.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
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/* MMU TLB control. Note that the wildcarding means we cover not just
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* the unified TLB ops but also the dside/iside/inner-shareable variants.
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*/
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{ .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, |
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.opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
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{ .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
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.opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
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{ .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
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.opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
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{ .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
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.opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
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/* Cache maintenance ops; some of this space may be overridden later. */
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{ .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
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.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
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.type = ARM_CP_NOP | ARM_CP_OVERRIDE }, |
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REGINFO_SENTINEL |
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}; |
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|
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static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
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/* Not all pre-v6 cores implemented this WFI, so this is slightly
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* over-broad.
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*/
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{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, |
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.access = PL1_W, .type = ARM_CP_WFI }, |
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REGINFO_SENTINEL |
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}; |
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|
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static const ARMCPRegInfo not_v7_cp_reginfo[] = { |
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/* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
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* is UNPREDICTABLE; we choose to NOP as most implementations do).
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*/
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{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, |
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.access = PL1_W, .type = ARM_CP_WFI }, |
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/* L1 cache lockdown. Not architectural in v6 and earlier but in practice
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* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
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* OMAPCP will override this space.
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*/
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{ .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, |
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), |
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.resetvalue = 0 },
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{ .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, |
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), |
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.resetvalue = 0 },
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/* v6 doesn't have the cache ID registers but Linux reads them anyway */
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{ .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, |
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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REGINFO_SENTINEL |
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}; |
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|
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static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
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{ |
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if (env->cp15.c1_coproc != value) {
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env->cp15.c1_coproc = value; |
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/* ??? Is this safe when called from within a TB? */
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tb_flush(env); |
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} |
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return 0; |
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} |
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|
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static const ARMCPRegInfo v6_cp_reginfo[] = { |
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/* prefetch by MVA in v6, NOP in v7 */
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{ .name = "MVA_prefetch",
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.cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, |
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.access = PL1_W, .type = ARM_CP_NOP }, |
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{ .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
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.access = PL0_W, .type = ARM_CP_NOP }, |
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{ .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
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.access = PL0_W, .type = ARM_CP_NOP }, |
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{ .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
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.access = PL0_W, .type = ARM_CP_NOP }, |
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{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), |
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.resetvalue = 0, },
|
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/* Watchpoint Fault Address Register : should actually only be present
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* for 1136, 1176, 11MPCore.
|
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*/
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{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, |
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
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{ .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, |
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), |
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.resetvalue = 0, .writefn = cpacr_write },
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REGINFO_SENTINEL |
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}; |
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|
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static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t *value) |
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{ |
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/* Generic performance monitor register read function for where
|
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* user access may be allowed by PMUSERENR.
|
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*/
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
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return EXCP_UDEF;
|
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} |
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*value = CPREG_FIELD32(env, ri); |
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return 0; |
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} |
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|
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static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
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return EXCP_UDEF;
|
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} |
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/* only the DP, X, D and E bits are writable */
|
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env->cp15.c9_pmcr &= ~0x39;
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env->cp15.c9_pmcr |= (value & 0x39);
|
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return 0; |
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} |
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|
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static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
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return EXCP_UDEF;
|
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} |
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value &= (1 << 31); |
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env->cp15.c9_pmcnten |= value; |
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return 0; |
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} |
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|
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static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
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return EXCP_UDEF;
|
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} |
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value &= (1 << 31); |
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env->cp15.c9_pmcnten &= ~value; |
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return 0; |
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} |
284 |
|
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static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
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{ |
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
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return EXCP_UDEF;
|
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} |
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env->cp15.c9_pmovsr &= ~value; |
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return 0; |
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} |
294 |
|
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static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
297 |
{ |
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { |
299 |
return EXCP_UDEF;
|
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} |
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env->cp15.c9_pmxevtyper = value & 0xff;
|
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return 0; |
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} |
304 |
|
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static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
307 |
{ |
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env->cp15.c9_pmuserenr = value & 1;
|
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return 0; |
310 |
} |
311 |
|
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static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
314 |
{ |
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/* We have no event counters so only the C bit can be changed */
|
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value &= (1 << 31); |
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env->cp15.c9_pminten |= value; |
318 |
return 0; |
319 |
} |
320 |
|
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static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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uint64_t value) |
323 |
{ |
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value &= (1 << 31); |
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env->cp15.c9_pminten &= ~value; |
326 |
return 0; |
327 |
} |
328 |
|
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static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
330 |
uint64_t *value) |
331 |
{ |
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ARMCPU *cpu = arm_env_get_cpu(env); |
333 |
*value = cpu->ccsidr[env->cp15.c0_cssel]; |
334 |
return 0; |
335 |
} |
336 |
|
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static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
338 |
uint64_t value) |
339 |
{ |
340 |
env->cp15.c0_cssel = value & 0xf;
|
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return 0; |
342 |
} |
343 |
|
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static const ARMCPRegInfo v7_cp_reginfo[] = { |
345 |
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
|
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* debug components
|
347 |
*/
|
348 |
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, |
349 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
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{ .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
351 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
352 |
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
|
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{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, |
354 |
.access = PL1_W, .type = ARM_CP_NOP }, |
355 |
/* Performance monitors are implementation defined in v7,
|
356 |
* but with an ARM recommended set of registers, which we
|
357 |
* follow (although we don't actually implement any counters)
|
358 |
*
|
359 |
* Performance registers fall into three categories:
|
360 |
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
|
361 |
* (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
|
362 |
* (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
|
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* For the cases controlled by PMUSERENR we must set .access to PL0_RW
|
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* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
|
365 |
*/
|
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{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, |
367 |
.access = PL0_RW, .resetvalue = 0,
|
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
369 |
.readfn = pmreg_read, .writefn = pmcntenset_write }, |
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{ .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
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.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
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.readfn = pmreg_read, .writefn = pmcntenclr_write }, |
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{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
374 |
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
375 |
.readfn = pmreg_read, .writefn = pmovsr_write }, |
376 |
/* Unimplemented so WI. Strictly speaking write accesses in PL0 should
|
377 |
* respect PMUSERENR.
|
378 |
*/
|
379 |
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
380 |
.access = PL0_W, .type = ARM_CP_NOP }, |
381 |
/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
|
382 |
* We choose to RAZ/WI. XXX should respect PMUSERENR.
|
383 |
*/
|
384 |
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
385 |
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
386 |
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
|
387 |
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
389 |
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
390 |
.access = PL0_RW, |
391 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), |
392 |
.readfn = pmreg_read, .writefn = pmxevtyper_write }, |
393 |
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
|
394 |
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
395 |
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
396 |
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
397 |
.access = PL0_R | PL1_RW, |
398 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
399 |
.resetvalue = 0,
|
400 |
.writefn = pmuserenr_write }, |
401 |
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
402 |
.access = PL1_RW, |
403 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
404 |
.resetvalue = 0,
|
405 |
.writefn = pmintenset_write }, |
406 |
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
407 |
.access = PL1_RW, |
408 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
409 |
.resetvalue = 0,
|
410 |
.writefn = pmintenclr_write }, |
411 |
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, |
412 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), |
413 |
.resetvalue = 0, },
|
414 |
{ .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, |
415 |
.access = PL1_R, .readfn = ccsidr_read }, |
416 |
{ .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, |
417 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), |
418 |
.writefn = csselr_write, .resetvalue = 0 },
|
419 |
/* Auxiliary ID register: this actually has an IMPDEF value but for now
|
420 |
* just RAZ for all cores:
|
421 |
*/
|
422 |
{ .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7, |
423 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
424 |
REGINFO_SENTINEL |
425 |
}; |
426 |
|
427 |
static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
428 |
{ |
429 |
value &= 1;
|
430 |
env->teecr = value; |
431 |
return 0; |
432 |
} |
433 |
|
434 |
static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
435 |
uint64_t *value) |
436 |
{ |
437 |
/* This is a helper function because the user access rights
|
438 |
* depend on the value of the TEECR.
|
439 |
*/
|
440 |
if (arm_current_pl(env) == 0 && (env->teecr & 1)) { |
441 |
return EXCP_UDEF;
|
442 |
} |
443 |
*value = env->teehbr; |
444 |
return 0; |
445 |
} |
446 |
|
447 |
static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
448 |
uint64_t value) |
449 |
{ |
450 |
if (arm_current_pl(env) == 0 && (env->teecr & 1)) { |
451 |
return EXCP_UDEF;
|
452 |
} |
453 |
env->teehbr = value; |
454 |
return 0; |
455 |
} |
456 |
|
457 |
static const ARMCPRegInfo t2ee_cp_reginfo[] = { |
458 |
{ .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, |
459 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), |
460 |
.resetvalue = 0,
|
461 |
.writefn = teecr_write }, |
462 |
{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, |
463 |
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), |
464 |
.resetvalue = 0,
|
465 |
.readfn = teehbr_read, .writefn = teehbr_write }, |
466 |
REGINFO_SENTINEL |
467 |
}; |
468 |
|
469 |
static const ARMCPRegInfo v6k_cp_reginfo[] = { |
470 |
{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
471 |
.access = PL0_RW, |
472 |
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls1), |
473 |
.resetvalue = 0 },
|
474 |
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
475 |
.access = PL0_R|PL1_W, |
476 |
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls2), |
477 |
.resetvalue = 0 },
|
478 |
{ .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4, |
479 |
.access = PL1_RW, |
480 |
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls3), |
481 |
.resetvalue = 0 },
|
482 |
REGINFO_SENTINEL |
483 |
}; |
484 |
|
485 |
static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
486 |
/* Dummy implementation: RAZ/WI the whole crn=14 space */
|
487 |
{ .name = "GENERIC_TIMER", .cp = 15, .crn = 14, |
488 |
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, |
489 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
490 |
REGINFO_SENTINEL |
491 |
}; |
492 |
|
493 |
static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
494 |
{ |
495 |
if (arm_feature(env, ARM_FEATURE_LPAE)) {
|
496 |
env->cp15.c7_par = value; |
497 |
} else if (arm_feature(env, ARM_FEATURE_V7)) { |
498 |
env->cp15.c7_par = value & 0xfffff6ff;
|
499 |
} else {
|
500 |
env->cp15.c7_par = value & 0xfffff1ff;
|
501 |
} |
502 |
return 0; |
503 |
} |
504 |
|
505 |
#ifndef CONFIG_USER_ONLY
|
506 |
/* get_phys_addr() isn't present for user-mode-only targets */
|
507 |
|
508 |
/* Return true if extended addresses are enabled, ie this is an
|
509 |
* LPAE implementation and we are using the long-descriptor translation
|
510 |
* table format because the TTBCR EAE bit is set.
|
511 |
*/
|
512 |
static inline bool extended_addresses_enabled(CPUARMState *env) |
513 |
{ |
514 |
return arm_feature(env, ARM_FEATURE_LPAE)
|
515 |
&& (env->cp15.c2_control & (1 << 31)); |
516 |
} |
517 |
|
518 |
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
519 |
{ |
520 |
hwaddr phys_addr; |
521 |
target_ulong page_size; |
522 |
int prot;
|
523 |
int ret, is_user = ri->opc2 & 2; |
524 |
int access_type = ri->opc2 & 1; |
525 |
|
526 |
if (ri->opc2 & 4) { |
527 |
/* Other states are only available with TrustZone */
|
528 |
return EXCP_UDEF;
|
529 |
} |
530 |
ret = get_phys_addr(env, value, access_type, is_user, |
531 |
&phys_addr, &prot, &page_size); |
532 |
if (extended_addresses_enabled(env)) {
|
533 |
/* ret is a DFSR/IFSR value for the long descriptor
|
534 |
* translation table format, but with WnR always clear.
|
535 |
* Convert it to a 64-bit PAR.
|
536 |
*/
|
537 |
uint64_t par64 = (1 << 11); /* LPAE bit always set */ |
538 |
if (ret == 0) { |
539 |
par64 |= phys_addr & ~0xfffULL;
|
540 |
/* We don't set the ATTR or SH fields in the PAR. */
|
541 |
} else {
|
542 |
par64 |= 1; /* F */ |
543 |
par64 |= (ret & 0x3f) << 1; /* FS */ |
544 |
/* Note that S2WLK and FSTAGE are always zero, because we don't
|
545 |
* implement virtualization and therefore there can't be a stage 2
|
546 |
* fault.
|
547 |
*/
|
548 |
} |
549 |
env->cp15.c7_par = par64; |
550 |
env->cp15.c7_par_hi = par64 >> 32;
|
551 |
} else {
|
552 |
/* ret is a DFSR/IFSR value for the short descriptor
|
553 |
* translation table format (with WnR always clear).
|
554 |
* Convert it to a 32-bit PAR.
|
555 |
*/
|
556 |
if (ret == 0) { |
557 |
/* We do not set any attribute bits in the PAR */
|
558 |
if (page_size == (1 << 24) |
559 |
&& arm_feature(env, ARM_FEATURE_V7)) { |
560 |
env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1; |
561 |
} else {
|
562 |
env->cp15.c7_par = phys_addr & 0xfffff000;
|
563 |
} |
564 |
} else {
|
565 |
env->cp15.c7_par = ((ret & (10 << 1)) >> 5) | |
566 |
((ret & (12 << 1)) >> 6) | |
567 |
((ret & 0xf) << 1) | 1; |
568 |
} |
569 |
env->cp15.c7_par_hi = 0;
|
570 |
} |
571 |
return 0; |
572 |
} |
573 |
#endif
|
574 |
|
575 |
static const ARMCPRegInfo vapa_cp_reginfo[] = { |
576 |
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, |
577 |
.access = PL1_RW, .resetvalue = 0,
|
578 |
.fieldoffset = offsetof(CPUARMState, cp15.c7_par), |
579 |
.writefn = par_write }, |
580 |
#ifndef CONFIG_USER_ONLY
|
581 |
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
582 |
.access = PL1_W, .writefn = ats_write }, |
583 |
#endif
|
584 |
REGINFO_SENTINEL |
585 |
}; |
586 |
|
587 |
/* Return basic MPU access permission bits. */
|
588 |
static uint32_t simple_mpu_ap_bits(uint32_t val)
|
589 |
{ |
590 |
uint32_t ret; |
591 |
uint32_t mask; |
592 |
int i;
|
593 |
ret = 0;
|
594 |
mask = 3;
|
595 |
for (i = 0; i < 16; i += 2) { |
596 |
ret |= (val >> i) & mask; |
597 |
mask <<= 2;
|
598 |
} |
599 |
return ret;
|
600 |
} |
601 |
|
602 |
/* Pad basic MPU access permission bits to extended format. */
|
603 |
static uint32_t extended_mpu_ap_bits(uint32_t val)
|
604 |
{ |
605 |
uint32_t ret; |
606 |
uint32_t mask; |
607 |
int i;
|
608 |
ret = 0;
|
609 |
mask = 3;
|
610 |
for (i = 0; i < 16; i += 2) { |
611 |
ret |= (val & mask) << i; |
612 |
mask <<= 2;
|
613 |
} |
614 |
return ret;
|
615 |
} |
616 |
|
617 |
static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
618 |
uint64_t value) |
619 |
{ |
620 |
env->cp15.c5_data = extended_mpu_ap_bits(value); |
621 |
return 0; |
622 |
} |
623 |
|
624 |
static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri, |
625 |
uint64_t *value) |
626 |
{ |
627 |
*value = simple_mpu_ap_bits(env->cp15.c5_data); |
628 |
return 0; |
629 |
} |
630 |
|
631 |
static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
632 |
uint64_t value) |
633 |
{ |
634 |
env->cp15.c5_insn = extended_mpu_ap_bits(value); |
635 |
return 0; |
636 |
} |
637 |
|
638 |
static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri, |
639 |
uint64_t *value) |
640 |
{ |
641 |
*value = simple_mpu_ap_bits(env->cp15.c5_insn); |
642 |
return 0; |
643 |
} |
644 |
|
645 |
static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri, |
646 |
uint64_t *value) |
647 |
{ |
648 |
if (ri->crm >= 8) { |
649 |
return EXCP_UDEF;
|
650 |
} |
651 |
*value = env->cp15.c6_region[ri->crm]; |
652 |
return 0; |
653 |
} |
654 |
|
655 |
static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri, |
656 |
uint64_t value) |
657 |
{ |
658 |
if (ri->crm >= 8) { |
659 |
return EXCP_UDEF;
|
660 |
} |
661 |
env->cp15.c6_region[ri->crm] = value; |
662 |
return 0; |
663 |
} |
664 |
|
665 |
static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
666 |
{ .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
667 |
.access = PL1_RW, |
668 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
|
669 |
.readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
670 |
{ .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
671 |
.access = PL1_RW, |
672 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
|
673 |
.readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
674 |
{ .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, |
675 |
.access = PL1_RW, |
676 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
|
677 |
{ .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
678 |
.access = PL1_RW, |
679 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
|
680 |
{ .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
681 |
.access = PL1_RW, |
682 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
|
683 |
{ .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, |
684 |
.access = PL1_RW, |
685 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
|
686 |
/* Protection region base and size registers */
|
687 |
{ .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0, |
688 |
.opc2 = CP_ANY, .access = PL1_RW, |
689 |
.readfn = arm946_prbs_read, .writefn = arm946_prbs_write, }, |
690 |
REGINFO_SENTINEL |
691 |
}; |
692 |
|
693 |
static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
694 |
uint64_t value) |
695 |
{ |
696 |
if (arm_feature(env, ARM_FEATURE_LPAE)) {
|
697 |
value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); |
698 |
/* With LPAE the TTBCR could result in a change of ASID
|
699 |
* via the TTBCR.A1 bit, so do a TLB flush.
|
700 |
*/
|
701 |
tlb_flush(env, 1);
|
702 |
} else {
|
703 |
value &= 7;
|
704 |
} |
705 |
/* Note that we always calculate c2_mask and c2_base_mask, but
|
706 |
* they are only used for short-descriptor tables (ie if EAE is 0);
|
707 |
* for long-descriptor tables the TTBCR fields are used differently
|
708 |
* and the c2_mask and c2_base_mask values are meaningless.
|
709 |
*/
|
710 |
env->cp15.c2_control = value; |
711 |
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
|
712 |
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
|
713 |
return 0; |
714 |
} |
715 |
|
716 |
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
717 |
{ |
718 |
env->cp15.c2_base_mask = 0xffffc000u;
|
719 |
env->cp15.c2_control = 0;
|
720 |
env->cp15.c2_mask = 0;
|
721 |
} |
722 |
|
723 |
static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
724 |
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
725 |
.access = PL1_RW, |
726 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
|
727 |
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
728 |
.access = PL1_RW, |
729 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
|
730 |
{ .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
731 |
.access = PL1_RW, |
732 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
|
733 |
{ .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, |
734 |
.access = PL1_RW, |
735 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
|
736 |
{ .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
737 |
.access = PL1_RW, .writefn = vmsa_ttbcr_write, |
738 |
.resetfn = vmsa_ttbcr_reset, |
739 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, |
740 |
{ .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, |
741 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data), |
742 |
.resetvalue = 0, },
|
743 |
REGINFO_SENTINEL |
744 |
}; |
745 |
|
746 |
static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
747 |
uint64_t value) |
748 |
{ |
749 |
env->cp15.c15_ticonfig = value & 0xe7;
|
750 |
/* The OS_TYPE bit in this register changes the reported CPUID! */
|
751 |
env->cp15.c0_cpuid = (value & (1 << 5)) ? |
752 |
ARM_CPUID_TI915T : ARM_CPUID_TI925T; |
753 |
return 0; |
754 |
} |
755 |
|
756 |
static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
757 |
uint64_t value) |
758 |
{ |
759 |
env->cp15.c15_threadid = value & 0xffff;
|
760 |
return 0; |
761 |
} |
762 |
|
763 |
static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
764 |
uint64_t value) |
765 |
{ |
766 |
/* Wait-for-interrupt (deprecated) */
|
767 |
cpu_interrupt(env, CPU_INTERRUPT_HALT); |
768 |
return 0; |
769 |
} |
770 |
|
771 |
static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
772 |
uint64_t value) |
773 |
{ |
774 |
/* On OMAP there are registers indicating the max/min index of dcache lines
|
775 |
* containing a dirty line; cache flush operations have to reset these.
|
776 |
*/
|
777 |
env->cp15.c15_i_max = 0x000;
|
778 |
env->cp15.c15_i_min = 0xff0;
|
779 |
return 0; |
780 |
} |
781 |
|
782 |
static const ARMCPRegInfo omap_cp_reginfo[] = { |
783 |
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, |
784 |
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, |
785 |
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
|
786 |
{ .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
787 |
.access = PL1_RW, .type = ARM_CP_NOP }, |
788 |
{ .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, |
789 |
.access = PL1_RW, |
790 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
|
791 |
.writefn = omap_ticonfig_write }, |
792 |
{ .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, |
793 |
.access = PL1_RW, |
794 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
|
795 |
{ .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, |
796 |
.access = PL1_RW, .resetvalue = 0xff0,
|
797 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, |
798 |
{ .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, |
799 |
.access = PL1_RW, |
800 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
|
801 |
.writefn = omap_threadid_write }, |
802 |
{ .name = "TI925T_STATUS", .cp = 15, .crn = 15, |
803 |
.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, |
804 |
.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
805 |
/* TODO: Peripheral port remap register:
|
806 |
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
|
807 |
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
|
808 |
* when MMU is off.
|
809 |
*/
|
810 |
{ .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
811 |
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
|
812 |
.writefn = omap_cachemaint_write }, |
813 |
{ .name = "C9", .cp = 15, .crn = 9, |
814 |
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, |
815 |
.type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
|
816 |
REGINFO_SENTINEL |
817 |
}; |
818 |
|
819 |
static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
820 |
uint64_t value) |
821 |
{ |
822 |
value &= 0x3fff;
|
823 |
if (env->cp15.c15_cpar != value) {
|
824 |
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
|
825 |
tb_flush(env); |
826 |
env->cp15.c15_cpar = value; |
827 |
} |
828 |
return 0; |
829 |
} |
830 |
|
831 |
static const ARMCPRegInfo xscale_cp_reginfo[] = { |
832 |
{ .name = "XSCALE_CPAR",
|
833 |
.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, |
834 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
|
835 |
.writefn = xscale_cpar_write, }, |
836 |
{ .name = "XSCALE_AUXCR",
|
837 |
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, |
838 |
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), |
839 |
.resetvalue = 0, },
|
840 |
REGINFO_SENTINEL |
841 |
}; |
842 |
|
843 |
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { |
844 |
/* RAZ/WI the whole crn=15 space, when we don't have a more specific
|
845 |
* implementation of this implementation-defined space.
|
846 |
* Ideally this should eventually disappear in favour of actually
|
847 |
* implementing the correct behaviour for all cores.
|
848 |
*/
|
849 |
{ .name = "C15_IMPDEF", .cp = 15, .crn = 15, |
850 |
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, |
851 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
852 |
REGINFO_SENTINEL |
853 |
}; |
854 |
|
855 |
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
856 |
/* Cache status: RAZ because we have no cache so it's always clean */
|
857 |
{ .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, |
858 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
859 |
REGINFO_SENTINEL |
860 |
}; |
861 |
|
862 |
static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { |
863 |
/* We never have a a block transfer operation in progress */
|
864 |
{ .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, |
865 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
866 |
/* The cache ops themselves: these all NOP for QEMU */
|
867 |
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, |
868 |
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
869 |
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, |
870 |
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
871 |
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, |
872 |
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
873 |
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, |
874 |
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
875 |
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, |
876 |
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
877 |
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, |
878 |
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, |
879 |
REGINFO_SENTINEL |
880 |
}; |
881 |
|
882 |
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { |
883 |
/* The cache test-and-clean instructions always return (1 << 30)
|
884 |
* to indicate that there are no dirty cache lines.
|
885 |
*/
|
886 |
{ .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, |
887 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) }, |
888 |
{ .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
889 |
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) }, |
890 |
REGINFO_SENTINEL |
891 |
}; |
892 |
|
893 |
static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
894 |
/* Ignore ReadBuffer accesses */
|
895 |
{ .name = "C9_READBUFFER", .cp = 15, .crn = 9, |
896 |
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, |
897 |
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
898 |
.resetvalue = 0 },
|
899 |
REGINFO_SENTINEL |
900 |
}; |
901 |
|
902 |
static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
903 |
uint64_t *value) |
904 |
{ |
905 |
uint32_t mpidr = env->cpu_index; |
906 |
/* We don't support setting cluster ID ([8..11])
|
907 |
* so these bits always RAZ.
|
908 |
*/
|
909 |
if (arm_feature(env, ARM_FEATURE_V7MP)) {
|
910 |
mpidr |= (1 << 31); |
911 |
/* Cores which are uniprocessor (non-coherent)
|
912 |
* but still implement the MP extensions set
|
913 |
* bit 30. (For instance, A9UP.) However we do
|
914 |
* not currently model any of those cores.
|
915 |
*/
|
916 |
} |
917 |
*value = mpidr; |
918 |
return 0; |
919 |
} |
920 |
|
921 |
static const ARMCPRegInfo mpidr_cp_reginfo[] = { |
922 |
{ .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, |
923 |
.access = PL1_R, .readfn = mpidr_read }, |
924 |
REGINFO_SENTINEL |
925 |
}; |
926 |
|
927 |
static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) |
928 |
{ |
929 |
*value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
|
930 |
return 0; |
931 |
} |
932 |
|
933 |
static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
934 |
{ |
935 |
env->cp15.c7_par_hi = value >> 32;
|
936 |
env->cp15.c7_par = value; |
937 |
return 0; |
938 |
} |
939 |
|
940 |
static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
941 |
{ |
942 |
env->cp15.c7_par_hi = 0;
|
943 |
env->cp15.c7_par = 0;
|
944 |
} |
945 |
|
946 |
static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri, |
947 |
uint64_t *value) |
948 |
{ |
949 |
*value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
|
950 |
return 0; |
951 |
} |
952 |
|
953 |
static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri, |
954 |
uint64_t value) |
955 |
{ |
956 |
env->cp15.c2_base0_hi = value >> 32;
|
957 |
env->cp15.c2_base0 = value; |
958 |
/* Writes to the 64 bit format TTBRs may change the ASID */
|
959 |
tlb_flush(env, 1);
|
960 |
return 0; |
961 |
} |
962 |
|
963 |
static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
964 |
{ |
965 |
env->cp15.c2_base0_hi = 0;
|
966 |
env->cp15.c2_base0 = 0;
|
967 |
} |
968 |
|
969 |
static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri, |
970 |
uint64_t *value) |
971 |
{ |
972 |
*value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
|
973 |
return 0; |
974 |
} |
975 |
|
976 |
static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri, |
977 |
uint64_t value) |
978 |
{ |
979 |
env->cp15.c2_base1_hi = value >> 32;
|
980 |
env->cp15.c2_base1 = value; |
981 |
return 0; |
982 |
} |
983 |
|
984 |
static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
985 |
{ |
986 |
env->cp15.c2_base1_hi = 0;
|
987 |
env->cp15.c2_base1 = 0;
|
988 |
} |
989 |
|
990 |
static const ARMCPRegInfo lpae_cp_reginfo[] = { |
991 |
/* NOP AMAIR0/1: the override is because these clash with the rather
|
992 |
* broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
|
993 |
*/
|
994 |
{ .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, |
995 |
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
996 |
.resetvalue = 0 },
|
997 |
{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
998 |
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, |
999 |
.resetvalue = 0 },
|
1000 |
/* 64 bit access versions of the (dummy) debug registers */
|
1001 |
{ .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, |
1002 |
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
|
1003 |
{ .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, |
1004 |
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
|
1005 |
{ .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
1006 |
.access = PL1_RW, .type = ARM_CP_64BIT, |
1007 |
.readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset }, |
1008 |
{ .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
1009 |
.access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read, |
1010 |
.writefn = ttbr064_write, .resetfn = ttbr064_reset }, |
1011 |
{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
1012 |
.access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read, |
1013 |
.writefn = ttbr164_write, .resetfn = ttbr164_reset }, |
1014 |
REGINFO_SENTINEL |
1015 |
}; |
1016 |
|
1017 |
static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1018 |
{ |
1019 |
env->cp15.c1_sys = value; |
1020 |
/* ??? Lots of these bits are not implemented. */
|
1021 |
/* This may enable/disable the MMU, so do a TLB flush. */
|
1022 |
tlb_flush(env, 1);
|
1023 |
return 0; |
1024 |
} |
1025 |
|
1026 |
void register_cp_regs_for_features(ARMCPU *cpu)
|
1027 |
{ |
1028 |
/* Register all the coprocessor registers based on feature bits */
|
1029 |
CPUARMState *env = &cpu->env; |
1030 |
if (arm_feature(env, ARM_FEATURE_M)) {
|
1031 |
/* M profile has no coprocessor registers */
|
1032 |
return;
|
1033 |
} |
1034 |
|
1035 |
define_arm_cp_regs(cpu, cp_reginfo); |
1036 |
if (arm_feature(env, ARM_FEATURE_V6)) {
|
1037 |
/* The ID registers all have impdef reset values */
|
1038 |
ARMCPRegInfo v6_idregs[] = { |
1039 |
{ .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1, |
1040 |
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, |
1041 |
.resetvalue = cpu->id_pfr0 }, |
1042 |
{ .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1, |
1043 |
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, |
1044 |
.resetvalue = cpu->id_pfr1 }, |
1045 |
{ .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1, |
1046 |
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, |
1047 |
.resetvalue = cpu->id_dfr0 }, |
1048 |
{ .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1, |
1049 |
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, |
1050 |
.resetvalue = cpu->id_afr0 }, |
1051 |
{ .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1, |
1052 |
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, |
1053 |
.resetvalue = cpu->id_mmfr0 }, |
1054 |
{ .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1, |
1055 |
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, |
1056 |
.resetvalue = cpu->id_mmfr1 }, |
1057 |
{ .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1, |
1058 |
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, |
1059 |
.resetvalue = cpu->id_mmfr2 }, |
1060 |
{ .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1, |
1061 |
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, |
1062 |
.resetvalue = cpu->id_mmfr3 }, |
1063 |
{ .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2, |
1064 |
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, |
1065 |
.resetvalue = cpu->id_isar0 }, |
1066 |
{ .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2, |
1067 |
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, |
1068 |
.resetvalue = cpu->id_isar1 }, |
1069 |
{ .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2, |
1070 |
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, |
1071 |
.resetvalue = cpu->id_isar2 }, |
1072 |
{ .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2, |
1073 |
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, |
1074 |
.resetvalue = cpu->id_isar3 }, |
1075 |
{ .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2, |
1076 |
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, |
1077 |
.resetvalue = cpu->id_isar4 }, |
1078 |
{ .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2, |
1079 |
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, |
1080 |
.resetvalue = cpu->id_isar5 }, |
1081 |
/* 6..7 are as yet unallocated and must RAZ */
|
1082 |
{ .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2, |
1083 |
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, |
1084 |
.resetvalue = 0 },
|
1085 |
{ .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2, |
1086 |
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, |
1087 |
.resetvalue = 0 },
|
1088 |
REGINFO_SENTINEL |
1089 |
}; |
1090 |
define_arm_cp_regs(cpu, v6_idregs); |
1091 |
define_arm_cp_regs(cpu, v6_cp_reginfo); |
1092 |
} else {
|
1093 |
define_arm_cp_regs(cpu, not_v6_cp_reginfo); |
1094 |
} |
1095 |
if (arm_feature(env, ARM_FEATURE_V6K)) {
|
1096 |
define_arm_cp_regs(cpu, v6k_cp_reginfo); |
1097 |
} |
1098 |
if (arm_feature(env, ARM_FEATURE_V7)) {
|
1099 |
/* v7 performance monitor control register: same implementor
|
1100 |
* field as main ID register, and we implement no event counters.
|
1101 |
*/
|
1102 |
ARMCPRegInfo pmcr = { |
1103 |
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, |
1104 |
.access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
|
1105 |
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), |
1106 |
.readfn = pmreg_read, .writefn = pmcr_write |
1107 |
}; |
1108 |
ARMCPRegInfo clidr = { |
1109 |
.name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, |
1110 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
1111 |
}; |
1112 |
define_one_arm_cp_reg(cpu, &pmcr); |
1113 |
define_one_arm_cp_reg(cpu, &clidr); |
1114 |
define_arm_cp_regs(cpu, v7_cp_reginfo); |
1115 |
} else {
|
1116 |
define_arm_cp_regs(cpu, not_v7_cp_reginfo); |
1117 |
} |
1118 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1119 |
/* These are the MPU registers prior to PMSAv6. Any new
|
1120 |
* PMSA core later than the ARM946 will require that we
|
1121 |
* implement the PMSAv6 or PMSAv7 registers, which are
|
1122 |
* completely different.
|
1123 |
*/
|
1124 |
assert(!arm_feature(env, ARM_FEATURE_V6)); |
1125 |
define_arm_cp_regs(cpu, pmsav5_cp_reginfo); |
1126 |
} else {
|
1127 |
define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
1128 |
} |
1129 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
1130 |
define_arm_cp_regs(cpu, t2ee_cp_reginfo); |
1131 |
} |
1132 |
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
|
1133 |
define_arm_cp_regs(cpu, generic_timer_cp_reginfo); |
1134 |
} |
1135 |
if (arm_feature(env, ARM_FEATURE_VAPA)) {
|
1136 |
define_arm_cp_regs(cpu, vapa_cp_reginfo); |
1137 |
} |
1138 |
if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
|
1139 |
define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); |
1140 |
} |
1141 |
if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
|
1142 |
define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); |
1143 |
} |
1144 |
if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
|
1145 |
define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); |
1146 |
} |
1147 |
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
1148 |
define_arm_cp_regs(cpu, omap_cp_reginfo); |
1149 |
} |
1150 |
if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
|
1151 |
define_arm_cp_regs(cpu, strongarm_cp_reginfo); |
1152 |
} |
1153 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1154 |
define_arm_cp_regs(cpu, xscale_cp_reginfo); |
1155 |
} |
1156 |
if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
|
1157 |
define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); |
1158 |
} |
1159 |
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
|
1160 |
define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
1161 |
} |
1162 |
if (arm_feature(env, ARM_FEATURE_LPAE)) {
|
1163 |
define_arm_cp_regs(cpu, lpae_cp_reginfo); |
1164 |
} |
1165 |
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
|
1166 |
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
|
1167 |
* be read-only (ie write causes UNDEF exception).
|
1168 |
*/
|
1169 |
{ |
1170 |
ARMCPRegInfo id_cp_reginfo[] = { |
1171 |
/* Note that the MIDR isn't a simple constant register because
|
1172 |
* of the TI925 behaviour where writes to another register can
|
1173 |
* cause the MIDR value to change.
|
1174 |
*/
|
1175 |
{ .name = "MIDR",
|
1176 |
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, |
1177 |
.access = PL1_R, .resetvalue = cpu->midr, |
1178 |
.writefn = arm_cp_write_ignore, |
1179 |
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) }, |
1180 |
{ .name = "CTR",
|
1181 |
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, |
1182 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, |
1183 |
{ .name = "TCMTR",
|
1184 |
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, |
1185 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
1186 |
{ .name = "TLBTR",
|
1187 |
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, |
1188 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
1189 |
/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
|
1190 |
{ .name = "DUMMY",
|
1191 |
.cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, |
1192 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
1193 |
{ .name = "DUMMY",
|
1194 |
.cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, |
1195 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
1196 |
{ .name = "DUMMY",
|
1197 |
.cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, |
1198 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
1199 |
{ .name = "DUMMY",
|
1200 |
.cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, |
1201 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
1202 |
{ .name = "DUMMY",
|
1203 |
.cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, |
1204 |
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
|
1205 |
REGINFO_SENTINEL |
1206 |
}; |
1207 |
ARMCPRegInfo crn0_wi_reginfo = { |
1208 |
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, |
1209 |
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, |
1210 |
.type = ARM_CP_NOP | ARM_CP_OVERRIDE |
1211 |
}; |
1212 |
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
|
1213 |
arm_feature(env, ARM_FEATURE_STRONGARM)) { |
1214 |
ARMCPRegInfo *r; |
1215 |
/* Register the blanket "writes ignored" value first to cover the
|
1216 |
* whole space. Then define the specific ID registers, but update
|
1217 |
* their access field to allow write access, so that they ignore
|
1218 |
* writes rather than causing them to UNDEF.
|
1219 |
*/
|
1220 |
define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); |
1221 |
for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
|
1222 |
r->access = PL1_RW; |
1223 |
define_one_arm_cp_reg(cpu, r); |
1224 |
} |
1225 |
} else {
|
1226 |
/* Just register the standard ID registers (read-only, meaning
|
1227 |
* that writes will UNDEF).
|
1228 |
*/
|
1229 |
define_arm_cp_regs(cpu, id_cp_reginfo); |
1230 |
} |
1231 |
} |
1232 |
|
1233 |
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
|
1234 |
ARMCPRegInfo auxcr = { |
1235 |
.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, |
1236 |
.access = PL1_RW, .type = ARM_CP_CONST, |
1237 |
.resetvalue = cpu->reset_auxcr |
1238 |
}; |
1239 |
define_one_arm_cp_reg(cpu, &auxcr); |
1240 |
} |
1241 |
|
1242 |
/* Generic registers whose values depend on the implementation */
|
1243 |
{ |
1244 |
ARMCPRegInfo sctlr = { |
1245 |
.name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, |
1246 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), |
1247 |
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr |
1248 |
}; |
1249 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1250 |
/* Normally we would always end the TB on an SCTLR write, but Linux
|
1251 |
* arch/arm/mach-pxa/sleep.S expects two instructions following
|
1252 |
* an MMU enable to execute from cache. Imitate this behaviour.
|
1253 |
*/
|
1254 |
sctlr.type |= ARM_CP_SUPPRESS_TB_END; |
1255 |
} |
1256 |
define_one_arm_cp_reg(cpu, &sctlr); |
1257 |
} |
1258 |
} |
1259 |
|
1260 |
ARMCPU *cpu_arm_init(const char *cpu_model) |
1261 |
{ |
1262 |
ARMCPU *cpu; |
1263 |
CPUARMState *env; |
1264 |
static int inited = 0; |
1265 |
|
1266 |
if (!object_class_by_name(cpu_model)) {
|
1267 |
return NULL; |
1268 |
} |
1269 |
cpu = ARM_CPU(object_new(cpu_model)); |
1270 |
env = &cpu->env; |
1271 |
env->cpu_model_str = cpu_model; |
1272 |
arm_cpu_realize(cpu); |
1273 |
|
1274 |
if (tcg_enabled() && !inited) {
|
1275 |
inited = 1;
|
1276 |
arm_translate_init(); |
1277 |
} |
1278 |
|
1279 |
cpu_reset(CPU(cpu)); |
1280 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
1281 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
1282 |
51, "arm-neon.xml", 0); |
1283 |
} else if (arm_feature(env, ARM_FEATURE_VFP3)) { |
1284 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
1285 |
35, "arm-vfp3.xml", 0); |
1286 |
} else if (arm_feature(env, ARM_FEATURE_VFP)) { |
1287 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
1288 |
19, "arm-vfp.xml", 0); |
1289 |
} |
1290 |
qemu_init_vcpu(env); |
1291 |
return cpu;
|
1292 |
} |
1293 |
|
1294 |
typedef struct ARMCPUListState { |
1295 |
fprintf_function cpu_fprintf; |
1296 |
FILE *file; |
1297 |
} ARMCPUListState; |
1298 |
|
1299 |
/* Sort alphabetically by type name, except for "any". */
|
1300 |
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
|
1301 |
{ |
1302 |
ObjectClass *class_a = (ObjectClass *)a; |
1303 |
ObjectClass *class_b = (ObjectClass *)b; |
1304 |
const char *name_a, *name_b; |
1305 |
|
1306 |
name_a = object_class_get_name(class_a); |
1307 |
name_b = object_class_get_name(class_b); |
1308 |
if (strcmp(name_a, "any") == 0) { |
1309 |
return 1; |
1310 |
} else if (strcmp(name_b, "any") == 0) { |
1311 |
return -1; |
1312 |
} else {
|
1313 |
return strcmp(name_a, name_b);
|
1314 |
} |
1315 |
} |
1316 |
|
1317 |
static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
1318 |
{ |
1319 |
ObjectClass *oc = data; |
1320 |
ARMCPUListState *s = user_data; |
1321 |
|
1322 |
(*s->cpu_fprintf)(s->file, " %s\n",
|
1323 |
object_class_get_name(oc)); |
1324 |
} |
1325 |
|
1326 |
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
1327 |
{ |
1328 |
ARMCPUListState s = { |
1329 |
.file = f, |
1330 |
.cpu_fprintf = cpu_fprintf, |
1331 |
}; |
1332 |
GSList *list; |
1333 |
|
1334 |
list = object_class_get_list(TYPE_ARM_CPU, false);
|
1335 |
list = g_slist_sort(list, arm_cpu_list_compare); |
1336 |
(*cpu_fprintf)(f, "Available CPUs:\n");
|
1337 |
g_slist_foreach(list, arm_cpu_list_entry, &s); |
1338 |
g_slist_free(list); |
1339 |
} |
1340 |
|
1341 |
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
|
1342 |
const ARMCPRegInfo *r, void *opaque) |
1343 |
{ |
1344 |
/* Define implementations of coprocessor registers.
|
1345 |
* We store these in a hashtable because typically
|
1346 |
* there are less than 150 registers in a space which
|
1347 |
* is 16*16*16*8*8 = 262144 in size.
|
1348 |
* Wildcarding is supported for the crm, opc1 and opc2 fields.
|
1349 |
* If a register is defined twice then the second definition is
|
1350 |
* used, so this can be used to define some generic registers and
|
1351 |
* then override them with implementation specific variations.
|
1352 |
* At least one of the original and the second definition should
|
1353 |
* include ARM_CP_OVERRIDE in its type bits -- this is just a guard
|
1354 |
* against accidental use.
|
1355 |
*/
|
1356 |
int crm, opc1, opc2;
|
1357 |
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
1358 |
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; |
1359 |
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; |
1360 |
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; |
1361 |
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; |
1362 |
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; |
1363 |
/* 64 bit registers have only CRm and Opc1 fields */
|
1364 |
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); |
1365 |
/* Check that the register definition has enough info to handle
|
1366 |
* reads and writes if they are permitted.
|
1367 |
*/
|
1368 |
if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
|
1369 |
if (r->access & PL3_R) {
|
1370 |
assert(r->fieldoffset || r->readfn); |
1371 |
} |
1372 |
if (r->access & PL3_W) {
|
1373 |
assert(r->fieldoffset || r->writefn); |
1374 |
} |
1375 |
} |
1376 |
/* Bad type field probably means missing sentinel at end of reg list */
|
1377 |
assert(cptype_valid(r->type)); |
1378 |
for (crm = crmmin; crm <= crmmax; crm++) {
|
1379 |
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
|
1380 |
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
|
1381 |
uint32_t *key = g_new(uint32_t, 1);
|
1382 |
ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
|
1383 |
int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; |
1384 |
*key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2); |
1385 |
r2->opaque = opaque; |
1386 |
/* Make sure reginfo passed to helpers for wildcarded regs
|
1387 |
* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
|
1388 |
*/
|
1389 |
r2->crm = crm; |
1390 |
r2->opc1 = opc1; |
1391 |
r2->opc2 = opc2; |
1392 |
/* Overriding of an existing definition must be explicitly
|
1393 |
* requested.
|
1394 |
*/
|
1395 |
if (!(r->type & ARM_CP_OVERRIDE)) {
|
1396 |
ARMCPRegInfo *oldreg; |
1397 |
oldreg = g_hash_table_lookup(cpu->cp_regs, key); |
1398 |
if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
|
1399 |
fprintf(stderr, "Register redefined: cp=%d %d bit "
|
1400 |
"crn=%d crm=%d opc1=%d opc2=%d, "
|
1401 |
"was %s, now %s\n", r2->cp, 32 + 32 * is64, |
1402 |
r2->crn, r2->crm, r2->opc1, r2->opc2, |
1403 |
oldreg->name, r2->name); |
1404 |
assert(0);
|
1405 |
} |
1406 |
} |
1407 |
g_hash_table_insert(cpu->cp_regs, key, r2); |
1408 |
} |
1409 |
} |
1410 |
} |
1411 |
} |
1412 |
|
1413 |
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
|
1414 |
const ARMCPRegInfo *regs, void *opaque) |
1415 |
{ |
1416 |
/* Define a whole list of registers */
|
1417 |
const ARMCPRegInfo *r;
|
1418 |
for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
|
1419 |
define_one_arm_cp_reg_with_opaque(cpu, r, opaque); |
1420 |
} |
1421 |
} |
1422 |
|
1423 |
const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
|
1424 |
{ |
1425 |
return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
|
1426 |
} |
1427 |
|
1428 |
int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
1429 |
uint64_t value) |
1430 |
{ |
1431 |
/* Helper coprocessor write function for write-ignore registers */
|
1432 |
return 0; |
1433 |
} |
1434 |
|
1435 |
int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) |
1436 |
{ |
1437 |
/* Helper coprocessor write function for read-as-zero registers */
|
1438 |
*value = 0;
|
1439 |
return 0; |
1440 |
} |
1441 |
|
1442 |
static int bad_mode_switch(CPUARMState *env, int mode) |
1443 |
{ |
1444 |
/* Return true if it is not valid for us to switch to
|
1445 |
* this CPU mode (ie all the UNPREDICTABLE cases in
|
1446 |
* the ARM ARM CPSRWriteByInstr pseudocode).
|
1447 |
*/
|
1448 |
switch (mode) {
|
1449 |
case ARM_CPU_MODE_USR:
|
1450 |
case ARM_CPU_MODE_SYS:
|
1451 |
case ARM_CPU_MODE_SVC:
|
1452 |
case ARM_CPU_MODE_ABT:
|
1453 |
case ARM_CPU_MODE_UND:
|
1454 |
case ARM_CPU_MODE_IRQ:
|
1455 |
case ARM_CPU_MODE_FIQ:
|
1456 |
return 0; |
1457 |
default:
|
1458 |
return 1; |
1459 |
} |
1460 |
} |
1461 |
|
1462 |
uint32_t cpsr_read(CPUARMState *env) |
1463 |
{ |
1464 |
int ZF;
|
1465 |
ZF = (env->ZF == 0);
|
1466 |
return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | |
1467 |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
1468 |
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25) |
1469 |
| ((env->condexec_bits & 0xfc) << 8) |
1470 |
| (env->GE << 16);
|
1471 |
} |
1472 |
|
1473 |
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
|
1474 |
{ |
1475 |
if (mask & CPSR_NZCV) {
|
1476 |
env->ZF = (~val) & CPSR_Z; |
1477 |
env->NF = val; |
1478 |
env->CF = (val >> 29) & 1; |
1479 |
env->VF = (val << 3) & 0x80000000; |
1480 |
} |
1481 |
if (mask & CPSR_Q)
|
1482 |
env->QF = ((val & CPSR_Q) != 0);
|
1483 |
if (mask & CPSR_T)
|
1484 |
env->thumb = ((val & CPSR_T) != 0);
|
1485 |
if (mask & CPSR_IT_0_1) {
|
1486 |
env->condexec_bits &= ~3;
|
1487 |
env->condexec_bits |= (val >> 25) & 3; |
1488 |
} |
1489 |
if (mask & CPSR_IT_2_7) {
|
1490 |
env->condexec_bits &= 3;
|
1491 |
env->condexec_bits |= (val >> 8) & 0xfc; |
1492 |
} |
1493 |
if (mask & CPSR_GE) {
|
1494 |
env->GE = (val >> 16) & 0xf; |
1495 |
} |
1496 |
|
1497 |
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
|
1498 |
if (bad_mode_switch(env, val & CPSR_M)) {
|
1499 |
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
|
1500 |
* We choose to ignore the attempt and leave the CPSR M field
|
1501 |
* untouched.
|
1502 |
*/
|
1503 |
mask &= ~CPSR_M; |
1504 |
} else {
|
1505 |
switch_mode(env, val & CPSR_M); |
1506 |
} |
1507 |
} |
1508 |
mask &= ~CACHED_CPSR_BITS; |
1509 |
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
1510 |
} |
1511 |
|
1512 |
/* Sign/zero extend */
|
1513 |
uint32_t HELPER(sxtb16)(uint32_t x) |
1514 |
{ |
1515 |
uint32_t res; |
1516 |
res = (uint16_t)(int8_t)x; |
1517 |
res |= (uint32_t)(int8_t)(x >> 16) << 16; |
1518 |
return res;
|
1519 |
} |
1520 |
|
1521 |
uint32_t HELPER(uxtb16)(uint32_t x) |
1522 |
{ |
1523 |
uint32_t res; |
1524 |
res = (uint16_t)(uint8_t)x; |
1525 |
res |= (uint32_t)(uint8_t)(x >> 16) << 16; |
1526 |
return res;
|
1527 |
} |
1528 |
|
1529 |
uint32_t HELPER(clz)(uint32_t x) |
1530 |
{ |
1531 |
return clz32(x);
|
1532 |
} |
1533 |
|
1534 |
int32_t HELPER(sdiv)(int32_t num, int32_t den) |
1535 |
{ |
1536 |
if (den == 0) |
1537 |
return 0; |
1538 |
if (num == INT_MIN && den == -1) |
1539 |
return INT_MIN;
|
1540 |
return num / den;
|
1541 |
} |
1542 |
|
1543 |
uint32_t HELPER(udiv)(uint32_t num, uint32_t den) |
1544 |
{ |
1545 |
if (den == 0) |
1546 |
return 0; |
1547 |
return num / den;
|
1548 |
} |
1549 |
|
1550 |
uint32_t HELPER(rbit)(uint32_t x) |
1551 |
{ |
1552 |
x = ((x & 0xff000000) >> 24) |
1553 |
| ((x & 0x00ff0000) >> 8) |
1554 |
| ((x & 0x0000ff00) << 8) |
1555 |
| ((x & 0x000000ff) << 24); |
1556 |
x = ((x & 0xf0f0f0f0) >> 4) |
1557 |
| ((x & 0x0f0f0f0f) << 4); |
1558 |
x = ((x & 0x88888888) >> 3) |
1559 |
| ((x & 0x44444444) >> 1) |
1560 |
| ((x & 0x22222222) << 1) |
1561 |
| ((x & 0x11111111) << 3); |
1562 |
return x;
|
1563 |
} |
1564 |
|
1565 |
#if defined(CONFIG_USER_ONLY)
|
1566 |
|
1567 |
void do_interrupt (CPUARMState *env)
|
1568 |
{ |
1569 |
env->exception_index = -1;
|
1570 |
} |
1571 |
|
1572 |
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
1573 |
int mmu_idx)
|
1574 |
{ |
1575 |
if (rw == 2) { |
1576 |
env->exception_index = EXCP_PREFETCH_ABORT; |
1577 |
env->cp15.c6_insn = address; |
1578 |
} else {
|
1579 |
env->exception_index = EXCP_DATA_ABORT; |
1580 |
env->cp15.c6_data = address; |
1581 |
} |
1582 |
return 1; |
1583 |
} |
1584 |
|
1585 |
/* These should probably raise undefined insn exceptions. */
|
1586 |
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
|
1587 |
{ |
1588 |
cpu_abort(env, "v7m_mrs %d\n", reg);
|
1589 |
} |
1590 |
|
1591 |
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
1592 |
{ |
1593 |
cpu_abort(env, "v7m_mrs %d\n", reg);
|
1594 |
return 0; |
1595 |
} |
1596 |
|
1597 |
void switch_mode(CPUARMState *env, int mode) |
1598 |
{ |
1599 |
if (mode != ARM_CPU_MODE_USR)
|
1600 |
cpu_abort(env, "Tried to switch out of user mode\n");
|
1601 |
} |
1602 |
|
1603 |
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
|
1604 |
{ |
1605 |
cpu_abort(env, "banked r13 write\n");
|
1606 |
} |
1607 |
|
1608 |
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
1609 |
{ |
1610 |
cpu_abort(env, "banked r13 read\n");
|
1611 |
return 0; |
1612 |
} |
1613 |
|
1614 |
#else
|
1615 |
|
1616 |
/* Map CPU modes onto saved register banks. */
|
1617 |
static inline int bank_number(CPUARMState *env, int mode) |
1618 |
{ |
1619 |
switch (mode) {
|
1620 |
case ARM_CPU_MODE_USR:
|
1621 |
case ARM_CPU_MODE_SYS:
|
1622 |
return 0; |
1623 |
case ARM_CPU_MODE_SVC:
|
1624 |
return 1; |
1625 |
case ARM_CPU_MODE_ABT:
|
1626 |
return 2; |
1627 |
case ARM_CPU_MODE_UND:
|
1628 |
return 3; |
1629 |
case ARM_CPU_MODE_IRQ:
|
1630 |
return 4; |
1631 |
case ARM_CPU_MODE_FIQ:
|
1632 |
return 5; |
1633 |
} |
1634 |
cpu_abort(env, "Bad mode %x\n", mode);
|
1635 |
return -1; |
1636 |
} |
1637 |
|
1638 |
void switch_mode(CPUARMState *env, int mode) |
1639 |
{ |
1640 |
int old_mode;
|
1641 |
int i;
|
1642 |
|
1643 |
old_mode = env->uncached_cpsr & CPSR_M; |
1644 |
if (mode == old_mode)
|
1645 |
return;
|
1646 |
|
1647 |
if (old_mode == ARM_CPU_MODE_FIQ) {
|
1648 |
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
1649 |
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
1650 |
} else if (mode == ARM_CPU_MODE_FIQ) { |
1651 |
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
1652 |
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
1653 |
} |
1654 |
|
1655 |
i = bank_number(env, old_mode); |
1656 |
env->banked_r13[i] = env->regs[13];
|
1657 |
env->banked_r14[i] = env->regs[14];
|
1658 |
env->banked_spsr[i] = env->spsr; |
1659 |
|
1660 |
i = bank_number(env, mode); |
1661 |
env->regs[13] = env->banked_r13[i];
|
1662 |
env->regs[14] = env->banked_r14[i];
|
1663 |
env->spsr = env->banked_spsr[i]; |
1664 |
} |
1665 |
|
1666 |
static void v7m_push(CPUARMState *env, uint32_t val) |
1667 |
{ |
1668 |
env->regs[13] -= 4; |
1669 |
stl_phys(env->regs[13], val);
|
1670 |
} |
1671 |
|
1672 |
static uint32_t v7m_pop(CPUARMState *env)
|
1673 |
{ |
1674 |
uint32_t val; |
1675 |
val = ldl_phys(env->regs[13]);
|
1676 |
env->regs[13] += 4; |
1677 |
return val;
|
1678 |
} |
1679 |
|
1680 |
/* Switch to V7M main or process stack pointer. */
|
1681 |
static void switch_v7m_sp(CPUARMState *env, int process) |
1682 |
{ |
1683 |
uint32_t tmp; |
1684 |
if (env->v7m.current_sp != process) {
|
1685 |
tmp = env->v7m.other_sp; |
1686 |
env->v7m.other_sp = env->regs[13];
|
1687 |
env->regs[13] = tmp;
|
1688 |
env->v7m.current_sp = process; |
1689 |
} |
1690 |
} |
1691 |
|
1692 |
static void do_v7m_exception_exit(CPUARMState *env) |
1693 |
{ |
1694 |
uint32_t type; |
1695 |
uint32_t xpsr; |
1696 |
|
1697 |
type = env->regs[15];
|
1698 |
if (env->v7m.exception != 0) |
1699 |
armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
1700 |
|
1701 |
/* Switch to the target stack. */
|
1702 |
switch_v7m_sp(env, (type & 4) != 0); |
1703 |
/* Pop registers. */
|
1704 |
env->regs[0] = v7m_pop(env);
|
1705 |
env->regs[1] = v7m_pop(env);
|
1706 |
env->regs[2] = v7m_pop(env);
|
1707 |
env->regs[3] = v7m_pop(env);
|
1708 |
env->regs[12] = v7m_pop(env);
|
1709 |
env->regs[14] = v7m_pop(env);
|
1710 |
env->regs[15] = v7m_pop(env);
|
1711 |
xpsr = v7m_pop(env); |
1712 |
xpsr_write(env, xpsr, 0xfffffdff);
|
1713 |
/* Undo stack alignment. */
|
1714 |
if (xpsr & 0x200) |
1715 |
env->regs[13] |= 4; |
1716 |
/* ??? The exception return type specifies Thread/Handler mode. However
|
1717 |
this is also implied by the xPSR value. Not sure what to do
|
1718 |
if there is a mismatch. */
|
1719 |
/* ??? Likewise for mismatches between the CONTROL register and the stack
|
1720 |
pointer. */
|
1721 |
} |
1722 |
|
1723 |
static void do_interrupt_v7m(CPUARMState *env) |
1724 |
{ |
1725 |
uint32_t xpsr = xpsr_read(env); |
1726 |
uint32_t lr; |
1727 |
uint32_t addr; |
1728 |
|
1729 |
lr = 0xfffffff1;
|
1730 |
if (env->v7m.current_sp)
|
1731 |
lr |= 4;
|
1732 |
if (env->v7m.exception == 0) |
1733 |
lr |= 8;
|
1734 |
|
1735 |
/* For exceptions we just mark as pending on the NVIC, and let that
|
1736 |
handle it. */
|
1737 |
/* TODO: Need to escalate if the current priority is higher than the
|
1738 |
one we're raising. */
|
1739 |
switch (env->exception_index) {
|
1740 |
case EXCP_UDEF:
|
1741 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
1742 |
return;
|
1743 |
case EXCP_SWI:
|
1744 |
env->regs[15] += 2; |
1745 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
1746 |
return;
|
1747 |
case EXCP_PREFETCH_ABORT:
|
1748 |
case EXCP_DATA_ABORT:
|
1749 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
1750 |
return;
|
1751 |
case EXCP_BKPT:
|
1752 |
if (semihosting_enabled) {
|
1753 |
int nr;
|
1754 |
nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
1755 |
if (nr == 0xab) { |
1756 |
env->regs[15] += 2; |
1757 |
env->regs[0] = do_arm_semihosting(env);
|
1758 |
return;
|
1759 |
} |
1760 |
} |
1761 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
1762 |
return;
|
1763 |
case EXCP_IRQ:
|
1764 |
env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
1765 |
break;
|
1766 |
case EXCP_EXCEPTION_EXIT:
|
1767 |
do_v7m_exception_exit(env); |
1768 |
return;
|
1769 |
default:
|
1770 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
1771 |
return; /* Never happens. Keep compiler happy. */ |
1772 |
} |
1773 |
|
1774 |
/* Align stack pointer. */
|
1775 |
/* ??? Should only do this if Configuration Control Register
|
1776 |
STACKALIGN bit is set. */
|
1777 |
if (env->regs[13] & 4) { |
1778 |
env->regs[13] -= 4; |
1779 |
xpsr |= 0x200;
|
1780 |
} |
1781 |
/* Switch to the handler mode. */
|
1782 |
v7m_push(env, xpsr); |
1783 |
v7m_push(env, env->regs[15]);
|
1784 |
v7m_push(env, env->regs[14]);
|
1785 |
v7m_push(env, env->regs[12]);
|
1786 |
v7m_push(env, env->regs[3]);
|
1787 |
v7m_push(env, env->regs[2]);
|
1788 |
v7m_push(env, env->regs[1]);
|
1789 |
v7m_push(env, env->regs[0]);
|
1790 |
switch_v7m_sp(env, 0);
|
1791 |
/* Clear IT bits */
|
1792 |
env->condexec_bits = 0;
|
1793 |
env->regs[14] = lr;
|
1794 |
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
|
1795 |
env->regs[15] = addr & 0xfffffffe; |
1796 |
env->thumb = addr & 1;
|
1797 |
} |
1798 |
|
1799 |
/* Handle a CPU exception. */
|
1800 |
void do_interrupt(CPUARMState *env)
|
1801 |
{ |
1802 |
uint32_t addr; |
1803 |
uint32_t mask; |
1804 |
int new_mode;
|
1805 |
uint32_t offset; |
1806 |
|
1807 |
if (IS_M(env)) {
|
1808 |
do_interrupt_v7m(env); |
1809 |
return;
|
1810 |
} |
1811 |
/* TODO: Vectored interrupt controller. */
|
1812 |
switch (env->exception_index) {
|
1813 |
case EXCP_UDEF:
|
1814 |
new_mode = ARM_CPU_MODE_UND; |
1815 |
addr = 0x04;
|
1816 |
mask = CPSR_I; |
1817 |
if (env->thumb)
|
1818 |
offset = 2;
|
1819 |
else
|
1820 |
offset = 4;
|
1821 |
break;
|
1822 |
case EXCP_SWI:
|
1823 |
if (semihosting_enabled) {
|
1824 |
/* Check for semihosting interrupt. */
|
1825 |
if (env->thumb) {
|
1826 |
mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code) |
1827 |
& 0xff;
|
1828 |
} else {
|
1829 |
mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code) |
1830 |
& 0xffffff;
|
1831 |
} |
1832 |
/* Only intercept calls from privileged modes, to provide some
|
1833 |
semblance of security. */
|
1834 |
if (((mask == 0x123456 && !env->thumb) |
1835 |
|| (mask == 0xab && env->thumb))
|
1836 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
1837 |
env->regs[0] = do_arm_semihosting(env);
|
1838 |
return;
|
1839 |
} |
1840 |
} |
1841 |
new_mode = ARM_CPU_MODE_SVC; |
1842 |
addr = 0x08;
|
1843 |
mask = CPSR_I; |
1844 |
/* The PC already points to the next instruction. */
|
1845 |
offset = 0;
|
1846 |
break;
|
1847 |
case EXCP_BKPT:
|
1848 |
/* See if this is a semihosting syscall. */
|
1849 |
if (env->thumb && semihosting_enabled) {
|
1850 |
mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; |
1851 |
if (mask == 0xab |
1852 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
1853 |
env->regs[15] += 2; |
1854 |
env->regs[0] = do_arm_semihosting(env);
|
1855 |
return;
|
1856 |
} |
1857 |
} |
1858 |
env->cp15.c5_insn = 2;
|
1859 |
/* Fall through to prefetch abort. */
|
1860 |
case EXCP_PREFETCH_ABORT:
|
1861 |
new_mode = ARM_CPU_MODE_ABT; |
1862 |
addr = 0x0c;
|
1863 |
mask = CPSR_A | CPSR_I; |
1864 |
offset = 4;
|
1865 |
break;
|
1866 |
case EXCP_DATA_ABORT:
|
1867 |
new_mode = ARM_CPU_MODE_ABT; |
1868 |
addr = 0x10;
|
1869 |
mask = CPSR_A | CPSR_I; |
1870 |
offset = 8;
|
1871 |
break;
|
1872 |
case EXCP_IRQ:
|
1873 |
new_mode = ARM_CPU_MODE_IRQ; |
1874 |
addr = 0x18;
|
1875 |
/* Disable IRQ and imprecise data aborts. */
|
1876 |
mask = CPSR_A | CPSR_I; |
1877 |
offset = 4;
|
1878 |
break;
|
1879 |
case EXCP_FIQ:
|
1880 |
new_mode = ARM_CPU_MODE_FIQ; |
1881 |
addr = 0x1c;
|
1882 |
/* Disable FIQ, IRQ and imprecise data aborts. */
|
1883 |
mask = CPSR_A | CPSR_I | CPSR_F; |
1884 |
offset = 4;
|
1885 |
break;
|
1886 |
default:
|
1887 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
1888 |
return; /* Never happens. Keep compiler happy. */ |
1889 |
} |
1890 |
/* High vectors. */
|
1891 |
if (env->cp15.c1_sys & (1 << 13)) { |
1892 |
addr += 0xffff0000;
|
1893 |
} |
1894 |
switch_mode (env, new_mode); |
1895 |
env->spsr = cpsr_read(env); |
1896 |
/* Clear IT bits. */
|
1897 |
env->condexec_bits = 0;
|
1898 |
/* Switch to the new mode, and to the correct instruction set. */
|
1899 |
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
1900 |
env->uncached_cpsr |= mask; |
1901 |
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
|
1902 |
* and we should just guard the thumb mode on V4 */
|
1903 |
if (arm_feature(env, ARM_FEATURE_V4T)) {
|
1904 |
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0; |
1905 |
} |
1906 |
env->regs[14] = env->regs[15] + offset; |
1907 |
env->regs[15] = addr;
|
1908 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1909 |
} |
1910 |
|
1911 |
/* Check section/page access permissions.
|
1912 |
Returns the page protection flags, or zero if the access is not
|
1913 |
permitted. */
|
1914 |
static inline int check_ap(CPUARMState *env, int ap, int domain_prot, |
1915 |
int access_type, int is_user) |
1916 |
{ |
1917 |
int prot_ro;
|
1918 |
|
1919 |
if (domain_prot == 3) { |
1920 |
return PAGE_READ | PAGE_WRITE;
|
1921 |
} |
1922 |
|
1923 |
if (access_type == 1) |
1924 |
prot_ro = 0;
|
1925 |
else
|
1926 |
prot_ro = PAGE_READ; |
1927 |
|
1928 |
switch (ap) {
|
1929 |
case 0: |
1930 |
if (access_type == 1) |
1931 |
return 0; |
1932 |
switch ((env->cp15.c1_sys >> 8) & 3) { |
1933 |
case 1: |
1934 |
return is_user ? 0 : PAGE_READ; |
1935 |
case 2: |
1936 |
return PAGE_READ;
|
1937 |
default:
|
1938 |
return 0; |
1939 |
} |
1940 |
case 1: |
1941 |
return is_user ? 0 : PAGE_READ | PAGE_WRITE; |
1942 |
case 2: |
1943 |
if (is_user)
|
1944 |
return prot_ro;
|
1945 |
else
|
1946 |
return PAGE_READ | PAGE_WRITE;
|
1947 |
case 3: |
1948 |
return PAGE_READ | PAGE_WRITE;
|
1949 |
case 4: /* Reserved. */ |
1950 |
return 0; |
1951 |
case 5: |
1952 |
return is_user ? 0 : prot_ro; |
1953 |
case 6: |
1954 |
return prot_ro;
|
1955 |
case 7: |
1956 |
if (!arm_feature (env, ARM_FEATURE_V6K))
|
1957 |
return 0; |
1958 |
return prot_ro;
|
1959 |
default:
|
1960 |
abort(); |
1961 |
} |
1962 |
} |
1963 |
|
1964 |
static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
|
1965 |
{ |
1966 |
uint32_t table; |
1967 |
|
1968 |
if (address & env->cp15.c2_mask)
|
1969 |
table = env->cp15.c2_base1 & 0xffffc000;
|
1970 |
else
|
1971 |
table = env->cp15.c2_base0 & env->cp15.c2_base_mask; |
1972 |
|
1973 |
table |= (address >> 18) & 0x3ffc; |
1974 |
return table;
|
1975 |
} |
1976 |
|
1977 |
static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, |
1978 |
int is_user, hwaddr *phys_ptr,
|
1979 |
int *prot, target_ulong *page_size)
|
1980 |
{ |
1981 |
int code;
|
1982 |
uint32_t table; |
1983 |
uint32_t desc; |
1984 |
int type;
|
1985 |
int ap;
|
1986 |
int domain;
|
1987 |
int domain_prot;
|
1988 |
hwaddr phys_addr; |
1989 |
|
1990 |
/* Pagetable walk. */
|
1991 |
/* Lookup l1 descriptor. */
|
1992 |
table = get_level1_table_address(env, address); |
1993 |
desc = ldl_phys(table); |
1994 |
type = (desc & 3);
|
1995 |
domain = (desc >> 5) & 0x0f; |
1996 |
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
1997 |
if (type == 0) { |
1998 |
/* Section translation fault. */
|
1999 |
code = 5;
|
2000 |
goto do_fault;
|
2001 |
} |
2002 |
if (domain_prot == 0 || domain_prot == 2) { |
2003 |
if (type == 2) |
2004 |
code = 9; /* Section domain fault. */ |
2005 |
else
|
2006 |
code = 11; /* Page domain fault. */ |
2007 |
goto do_fault;
|
2008 |
} |
2009 |
if (type == 2) { |
2010 |
/* 1Mb section. */
|
2011 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
2012 |
ap = (desc >> 10) & 3; |
2013 |
code = 13;
|
2014 |
*page_size = 1024 * 1024; |
2015 |
} else {
|
2016 |
/* Lookup l2 entry. */
|
2017 |
if (type == 1) { |
2018 |
/* Coarse pagetable. */
|
2019 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
2020 |
} else {
|
2021 |
/* Fine pagetable. */
|
2022 |
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); |
2023 |
} |
2024 |
desc = ldl_phys(table); |
2025 |
switch (desc & 3) { |
2026 |
case 0: /* Page translation fault. */ |
2027 |
code = 7;
|
2028 |
goto do_fault;
|
2029 |
case 1: /* 64k page. */ |
2030 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
2031 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
2032 |
*page_size = 0x10000;
|
2033 |
break;
|
2034 |
case 2: /* 4k page. */ |
2035 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
2036 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
2037 |
*page_size = 0x1000;
|
2038 |
break;
|
2039 |
case 3: /* 1k page. */ |
2040 |
if (type == 1) { |
2041 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
2042 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
2043 |
} else {
|
2044 |
/* Page translation fault. */
|
2045 |
code = 7;
|
2046 |
goto do_fault;
|
2047 |
} |
2048 |
} else {
|
2049 |
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); |
2050 |
} |
2051 |
ap = (desc >> 4) & 3; |
2052 |
*page_size = 0x400;
|
2053 |
break;
|
2054 |
default:
|
2055 |
/* Never happens, but compiler isn't smart enough to tell. */
|
2056 |
abort(); |
2057 |
} |
2058 |
code = 15;
|
2059 |
} |
2060 |
*prot = check_ap(env, ap, domain_prot, access_type, is_user); |
2061 |
if (!*prot) {
|
2062 |
/* Access permission fault. */
|
2063 |
goto do_fault;
|
2064 |
} |
2065 |
*prot |= PAGE_EXEC; |
2066 |
*phys_ptr = phys_addr; |
2067 |
return 0; |
2068 |
do_fault:
|
2069 |
return code | (domain << 4); |
2070 |
} |
2071 |
|
2072 |
static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, |
2073 |
int is_user, hwaddr *phys_ptr,
|
2074 |
int *prot, target_ulong *page_size)
|
2075 |
{ |
2076 |
int code;
|
2077 |
uint32_t table; |
2078 |
uint32_t desc; |
2079 |
uint32_t xn; |
2080 |
uint32_t pxn = 0;
|
2081 |
int type;
|
2082 |
int ap;
|
2083 |
int domain = 0; |
2084 |
int domain_prot;
|
2085 |
hwaddr phys_addr; |
2086 |
|
2087 |
/* Pagetable walk. */
|
2088 |
/* Lookup l1 descriptor. */
|
2089 |
table = get_level1_table_address(env, address); |
2090 |
desc = ldl_phys(table); |
2091 |
type = (desc & 3);
|
2092 |
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
2093 |
/* Section translation fault, or attempt to use the encoding
|
2094 |
* which is Reserved on implementations without PXN.
|
2095 |
*/
|
2096 |
code = 5;
|
2097 |
goto do_fault;
|
2098 |
} |
2099 |
if ((type == 1) || !(desc & (1 << 18))) { |
2100 |
/* Page or Section. */
|
2101 |
domain = (desc >> 5) & 0x0f; |
2102 |
} |
2103 |
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
2104 |
if (domain_prot == 0 || domain_prot == 2) { |
2105 |
if (type != 1) { |
2106 |
code = 9; /* Section domain fault. */ |
2107 |
} else {
|
2108 |
code = 11; /* Page domain fault. */ |
2109 |
} |
2110 |
goto do_fault;
|
2111 |
} |
2112 |
if (type != 1) { |
2113 |
if (desc & (1 << 18)) { |
2114 |
/* Supersection. */
|
2115 |
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); |
2116 |
*page_size = 0x1000000;
|
2117 |
} else {
|
2118 |
/* Section. */
|
2119 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
2120 |
*page_size = 0x100000;
|
2121 |
} |
2122 |
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
2123 |
xn = desc & (1 << 4); |
2124 |
pxn = desc & 1;
|
2125 |
code = 13;
|
2126 |
} else {
|
2127 |
if (arm_feature(env, ARM_FEATURE_PXN)) {
|
2128 |
pxn = (desc >> 2) & 1; |
2129 |
} |
2130 |
/* Lookup l2 entry. */
|
2131 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
2132 |
desc = ldl_phys(table); |
2133 |
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
2134 |
switch (desc & 3) { |
2135 |
case 0: /* Page translation fault. */ |
2136 |
code = 7;
|
2137 |
goto do_fault;
|
2138 |
case 1: /* 64k page. */ |
2139 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
2140 |
xn = desc & (1 << 15); |
2141 |
*page_size = 0x10000;
|
2142 |
break;
|
2143 |
case 2: case 3: /* 4k page. */ |
2144 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
2145 |
xn = desc & 1;
|
2146 |
*page_size = 0x1000;
|
2147 |
break;
|
2148 |
default:
|
2149 |
/* Never happens, but compiler isn't smart enough to tell. */
|
2150 |
abort(); |
2151 |
} |
2152 |
code = 15;
|
2153 |
} |
2154 |
if (domain_prot == 3) { |
2155 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
2156 |
} else {
|
2157 |
if (pxn && !is_user) {
|
2158 |
xn = 1;
|
2159 |
} |
2160 |
if (xn && access_type == 2) |
2161 |
goto do_fault;
|
2162 |
|
2163 |
/* The simplified model uses AP[0] as an access control bit. */
|
2164 |
if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) { |
2165 |
/* Access flag fault. */
|
2166 |
code = (code == 15) ? 6 : 3; |
2167 |
goto do_fault;
|
2168 |
} |
2169 |
*prot = check_ap(env, ap, domain_prot, access_type, is_user); |
2170 |
if (!*prot) {
|
2171 |
/* Access permission fault. */
|
2172 |
goto do_fault;
|
2173 |
} |
2174 |
if (!xn) {
|
2175 |
*prot |= PAGE_EXEC; |
2176 |
} |
2177 |
} |
2178 |
*phys_ptr = phys_addr; |
2179 |
return 0; |
2180 |
do_fault:
|
2181 |
return code | (domain << 4); |
2182 |
} |
2183 |
|
2184 |
/* Fault type for long-descriptor MMU fault reporting; this corresponds
|
2185 |
* to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
|
2186 |
*/
|
2187 |
typedef enum { |
2188 |
translation_fault = 1,
|
2189 |
access_fault = 2,
|
2190 |
permission_fault = 3,
|
2191 |
} MMUFaultType; |
2192 |
|
2193 |
static int get_phys_addr_lpae(CPUARMState *env, uint32_t address, |
2194 |
int access_type, int is_user, |
2195 |
hwaddr *phys_ptr, int *prot,
|
2196 |
target_ulong *page_size_ptr) |
2197 |
{ |
2198 |
/* Read an LPAE long-descriptor translation table. */
|
2199 |
MMUFaultType fault_type = translation_fault; |
2200 |
uint32_t level = 1;
|
2201 |
uint32_t epd; |
2202 |
uint32_t tsz; |
2203 |
uint64_t ttbr; |
2204 |
int ttbr_select;
|
2205 |
int n;
|
2206 |
hwaddr descaddr; |
2207 |
uint32_t tableattrs; |
2208 |
target_ulong page_size; |
2209 |
uint32_t attrs; |
2210 |
|
2211 |
/* Determine whether this address is in the region controlled by
|
2212 |
* TTBR0 or TTBR1 (or if it is in neither region and should fault).
|
2213 |
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
|
2214 |
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
|
2215 |
*/
|
2216 |
uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3); |
2217 |
uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3); |
2218 |
if (t0sz && !extract32(address, 32 - t0sz, t0sz)) { |
2219 |
/* there is a ttbr0 region and we are in it (high bits all zero) */
|
2220 |
ttbr_select = 0;
|
2221 |
} else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) { |
2222 |
/* there is a ttbr1 region and we are in it (high bits all one) */
|
2223 |
ttbr_select = 1;
|
2224 |
} else if (!t0sz) { |
2225 |
/* ttbr0 region is "everything not in the ttbr1 region" */
|
2226 |
ttbr_select = 0;
|
2227 |
} else if (!t1sz) { |
2228 |
/* ttbr1 region is "everything not in the ttbr0 region" */
|
2229 |
ttbr_select = 1;
|
2230 |
} else {
|
2231 |
/* in the gap between the two regions, this is a Translation fault */
|
2232 |
fault_type = translation_fault; |
2233 |
goto do_fault;
|
2234 |
} |
2235 |
|
2236 |
/* Note that QEMU ignores shareability and cacheability attributes,
|
2237 |
* so we don't need to do anything with the SH, ORGN, IRGN fields
|
2238 |
* in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
|
2239 |
* ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
|
2240 |
* implement any ASID-like capability so we can ignore it (instead
|
2241 |
* we will always flush the TLB any time the ASID is changed).
|
2242 |
*/
|
2243 |
if (ttbr_select == 0) { |
2244 |
ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
|
2245 |
epd = extract32(env->cp15.c2_control, 7, 1); |
2246 |
tsz = t0sz; |
2247 |
} else {
|
2248 |
ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
|
2249 |
epd = extract32(env->cp15.c2_control, 23, 1); |
2250 |
tsz = t1sz; |
2251 |
} |
2252 |
|
2253 |
if (epd) {
|
2254 |
/* Translation table walk disabled => Translation fault on TLB miss */
|
2255 |
goto do_fault;
|
2256 |
} |
2257 |
|
2258 |
/* If the region is small enough we will skip straight to a 2nd level
|
2259 |
* lookup. This affects the number of bits of the address used in
|
2260 |
* combination with the TTBR to find the first descriptor. ('n' here
|
2261 |
* matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
|
2262 |
* from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
|
2263 |
*/
|
2264 |
if (tsz > 1) { |
2265 |
level = 2;
|
2266 |
n = 14 - tsz;
|
2267 |
} else {
|
2268 |
n = 5 - tsz;
|
2269 |
} |
2270 |
|
2271 |
/* Clear the vaddr bits which aren't part of the within-region address,
|
2272 |
* so that we don't have to special case things when calculating the
|
2273 |
* first descriptor address.
|
2274 |
*/
|
2275 |
address &= (0xffffffffU >> tsz);
|
2276 |
|
2277 |
/* Now we can extract the actual base address from the TTBR */
|
2278 |
descaddr = extract64(ttbr, 0, 40); |
2279 |
descaddr &= ~((1ULL << n) - 1); |
2280 |
|
2281 |
tableattrs = 0;
|
2282 |
for (;;) {
|
2283 |
uint64_t descriptor; |
2284 |
|
2285 |
descaddr |= ((address >> (9 * (4 - level))) & 0xff8); |
2286 |
descriptor = ldq_phys(descaddr); |
2287 |
if (!(descriptor & 1) || |
2288 |
(!(descriptor & 2) && (level == 3))) { |
2289 |
/* Invalid, or the Reserved level 3 encoding */
|
2290 |
goto do_fault;
|
2291 |
} |
2292 |
descaddr = descriptor & 0xfffffff000ULL;
|
2293 |
|
2294 |
if ((descriptor & 2) && (level < 3)) { |
2295 |
/* Table entry. The top five bits are attributes which may
|
2296 |
* propagate down through lower levels of the table (and
|
2297 |
* which are all arranged so that 0 means "no effect", so
|
2298 |
* we can gather them up by ORing in the bits at each level).
|
2299 |
*/
|
2300 |
tableattrs |= extract64(descriptor, 59, 5); |
2301 |
level++; |
2302 |
continue;
|
2303 |
} |
2304 |
/* Block entry at level 1 or 2, or page entry at level 3.
|
2305 |
* These are basically the same thing, although the number
|
2306 |
* of bits we pull in from the vaddr varies.
|
2307 |
*/
|
2308 |
page_size = (1 << (39 - (9 * level))); |
2309 |
descaddr |= (address & (page_size - 1));
|
2310 |
/* Extract attributes from the descriptor and merge with table attrs */
|
2311 |
attrs = extract64(descriptor, 2, 10) |
2312 |
| (extract64(descriptor, 52, 12) << 10); |
2313 |
attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ |
2314 |
attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ |
2315 |
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
|
2316 |
* means "force PL1 access only", which means forcing AP[1] to 0.
|
2317 |
*/
|
2318 |
if (extract32(tableattrs, 2, 1)) { |
2319 |
attrs &= ~(1 << 4); |
2320 |
} |
2321 |
/* Since we're always in the Non-secure state, NSTable is ignored. */
|
2322 |
break;
|
2323 |
} |
2324 |
/* Here descaddr is the final physical address, and attributes
|
2325 |
* are all in attrs.
|
2326 |
*/
|
2327 |
fault_type = access_fault; |
2328 |
if ((attrs & (1 << 8)) == 0) { |
2329 |
/* Access flag */
|
2330 |
goto do_fault;
|
2331 |
} |
2332 |
fault_type = permission_fault; |
2333 |
if (is_user && !(attrs & (1 << 4))) { |
2334 |
/* Unprivileged access not enabled */
|
2335 |
goto do_fault;
|
2336 |
} |
2337 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
2338 |
if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) { |
2339 |
/* XN or PXN */
|
2340 |
if (access_type == 2) { |
2341 |
goto do_fault;
|
2342 |
} |
2343 |
*prot &= ~PAGE_EXEC; |
2344 |
} |
2345 |
if (attrs & (1 << 5)) { |
2346 |
/* Write access forbidden */
|
2347 |
if (access_type == 1) { |
2348 |
goto do_fault;
|
2349 |
} |
2350 |
*prot &= ~PAGE_WRITE; |
2351 |
} |
2352 |
|
2353 |
*phys_ptr = descaddr; |
2354 |
*page_size_ptr = page_size; |
2355 |
return 0; |
2356 |
|
2357 |
do_fault:
|
2358 |
/* Long-descriptor format IFSR/DFSR value */
|
2359 |
return (1 << 9) | (fault_type << 2) | level; |
2360 |
} |
2361 |
|
2362 |
static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, |
2363 |
int access_type, int is_user, |
2364 |
hwaddr *phys_ptr, int *prot)
|
2365 |
{ |
2366 |
int n;
|
2367 |
uint32_t mask; |
2368 |
uint32_t base; |
2369 |
|
2370 |
*phys_ptr = address; |
2371 |
for (n = 7; n >= 0; n--) { |
2372 |
base = env->cp15.c6_region[n]; |
2373 |
if ((base & 1) == 0) |
2374 |
continue;
|
2375 |
mask = 1 << ((base >> 1) & 0x1f); |
2376 |
/* Keep this shift separate from the above to avoid an
|
2377 |
(undefined) << 32. */
|
2378 |
mask = (mask << 1) - 1; |
2379 |
if (((base ^ address) & ~mask) == 0) |
2380 |
break;
|
2381 |
} |
2382 |
if (n < 0) |
2383 |
return 2; |
2384 |
|
2385 |
if (access_type == 2) { |
2386 |
mask = env->cp15.c5_insn; |
2387 |
} else {
|
2388 |
mask = env->cp15.c5_data; |
2389 |
} |
2390 |
mask = (mask >> (n * 4)) & 0xf; |
2391 |
switch (mask) {
|
2392 |
case 0: |
2393 |
return 1; |
2394 |
case 1: |
2395 |
if (is_user)
|
2396 |
return 1; |
2397 |
*prot = PAGE_READ | PAGE_WRITE; |
2398 |
break;
|
2399 |
case 2: |
2400 |
*prot = PAGE_READ; |
2401 |
if (!is_user)
|
2402 |
*prot |= PAGE_WRITE; |
2403 |
break;
|
2404 |
case 3: |
2405 |
*prot = PAGE_READ | PAGE_WRITE; |
2406 |
break;
|
2407 |
case 5: |
2408 |
if (is_user)
|
2409 |
return 1; |
2410 |
*prot = PAGE_READ; |
2411 |
break;
|
2412 |
case 6: |
2413 |
*prot = PAGE_READ; |
2414 |
break;
|
2415 |
default:
|
2416 |
/* Bad permission. */
|
2417 |
return 1; |
2418 |
} |
2419 |
*prot |= PAGE_EXEC; |
2420 |
return 0; |
2421 |
} |
2422 |
|
2423 |
/* get_phys_addr - get the physical address for this virtual address
|
2424 |
*
|
2425 |
* Find the physical address corresponding to the given virtual address,
|
2426 |
* by doing a translation table walk on MMU based systems or using the
|
2427 |
* MPU state on MPU based systems.
|
2428 |
*
|
2429 |
* Returns 0 if the translation was successful. Otherwise, phys_ptr,
|
2430 |
* prot and page_size are not filled in, and the return value provides
|
2431 |
* information on why the translation aborted, in the format of a
|
2432 |
* DFSR/IFSR fault register, with the following caveats:
|
2433 |
* * we honour the short vs long DFSR format differences.
|
2434 |
* * the WnR bit is never set (the caller must do this).
|
2435 |
* * for MPU based systems we don't bother to return a full FSR format
|
2436 |
* value.
|
2437 |
*
|
2438 |
* @env: CPUARMState
|
2439 |
* @address: virtual address to get physical address for
|
2440 |
* @access_type: 0 for read, 1 for write, 2 for execute
|
2441 |
* @is_user: 0 for privileged access, 1 for user
|
2442 |
* @phys_ptr: set to the physical address corresponding to the virtual address
|
2443 |
* @prot: set to the permissions for the page containing phys_ptr
|
2444 |
* @page_size: set to the size of the page containing phys_ptr
|
2445 |
*/
|
2446 |
static inline int get_phys_addr(CPUARMState *env, uint32_t address, |
2447 |
int access_type, int is_user, |
2448 |
hwaddr *phys_ptr, int *prot,
|
2449 |
target_ulong *page_size) |
2450 |
{ |
2451 |
/* Fast Context Switch Extension. */
|
2452 |
if (address < 0x02000000) |
2453 |
address += env->cp15.c13_fcse; |
2454 |
|
2455 |
if ((env->cp15.c1_sys & 1) == 0) { |
2456 |
/* MMU/MPU disabled. */
|
2457 |
*phys_ptr = address; |
2458 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
2459 |
*page_size = TARGET_PAGE_SIZE; |
2460 |
return 0; |
2461 |
} else if (arm_feature(env, ARM_FEATURE_MPU)) { |
2462 |
*page_size = TARGET_PAGE_SIZE; |
2463 |
return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
|
2464 |
prot); |
2465 |
} else if (extended_addresses_enabled(env)) { |
2466 |
return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
|
2467 |
prot, page_size); |
2468 |
} else if (env->cp15.c1_sys & (1 << 23)) { |
2469 |
return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
|
2470 |
prot, page_size); |
2471 |
} else {
|
2472 |
return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
|
2473 |
prot, page_size); |
2474 |
} |
2475 |
} |
2476 |
|
2477 |
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
|
2478 |
int access_type, int mmu_idx) |
2479 |
{ |
2480 |
hwaddr phys_addr; |
2481 |
target_ulong page_size; |
2482 |
int prot;
|
2483 |
int ret, is_user;
|
2484 |
|
2485 |
is_user = mmu_idx == MMU_USER_IDX; |
2486 |
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
2487 |
&page_size); |
2488 |
if (ret == 0) { |
2489 |
/* Map a single [sub]page. */
|
2490 |
phys_addr &= ~(hwaddr)0x3ff;
|
2491 |
address &= ~(uint32_t)0x3ff;
|
2492 |
tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); |
2493 |
return 0; |
2494 |
} |
2495 |
|
2496 |
if (access_type == 2) { |
2497 |
env->cp15.c5_insn = ret; |
2498 |
env->cp15.c6_insn = address; |
2499 |
env->exception_index = EXCP_PREFETCH_ABORT; |
2500 |
} else {
|
2501 |
env->cp15.c5_data = ret; |
2502 |
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
2503 |
env->cp15.c5_data |= (1 << 11); |
2504 |
env->cp15.c6_data = address; |
2505 |
env->exception_index = EXCP_DATA_ABORT; |
2506 |
} |
2507 |
return 1; |
2508 |
} |
2509 |
|
2510 |
hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr) |
2511 |
{ |
2512 |
hwaddr phys_addr; |
2513 |
target_ulong page_size; |
2514 |
int prot;
|
2515 |
int ret;
|
2516 |
|
2517 |
ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size); |
2518 |
|
2519 |
if (ret != 0) |
2520 |
return -1; |
2521 |
|
2522 |
return phys_addr;
|
2523 |
} |
2524 |
|
2525 |
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
|
2526 |
{ |
2527 |
if ((env->uncached_cpsr & CPSR_M) == mode) {
|
2528 |
env->regs[13] = val;
|
2529 |
} else {
|
2530 |
env->banked_r13[bank_number(env, mode)] = val; |
2531 |
} |
2532 |
} |
2533 |
|
2534 |
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) |
2535 |
{ |
2536 |
if ((env->uncached_cpsr & CPSR_M) == mode) {
|
2537 |
return env->regs[13]; |
2538 |
} else {
|
2539 |
return env->banked_r13[bank_number(env, mode)];
|
2540 |
} |
2541 |
} |
2542 |
|
2543 |
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
2544 |
{ |
2545 |
switch (reg) {
|
2546 |
case 0: /* APSR */ |
2547 |
return xpsr_read(env) & 0xf8000000; |
2548 |
case 1: /* IAPSR */ |
2549 |
return xpsr_read(env) & 0xf80001ff; |
2550 |
case 2: /* EAPSR */ |
2551 |
return xpsr_read(env) & 0xff00fc00; |
2552 |
case 3: /* xPSR */ |
2553 |
return xpsr_read(env) & 0xff00fdff; |
2554 |
case 5: /* IPSR */ |
2555 |
return xpsr_read(env) & 0x000001ff; |
2556 |
case 6: /* EPSR */ |
2557 |
return xpsr_read(env) & 0x0700fc00; |
2558 |
case 7: /* IEPSR */ |
2559 |
return xpsr_read(env) & 0x0700edff; |
2560 |
case 8: /* MSP */ |
2561 |
return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; |
2562 |
case 9: /* PSP */ |
2563 |
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; |
2564 |
case 16: /* PRIMASK */ |
2565 |
return (env->uncached_cpsr & CPSR_I) != 0; |
2566 |
case 17: /* BASEPRI */ |
2567 |
case 18: /* BASEPRI_MAX */ |
2568 |
return env->v7m.basepri;
|
2569 |
case 19: /* FAULTMASK */ |
2570 |
return (env->uncached_cpsr & CPSR_F) != 0; |
2571 |
case 20: /* CONTROL */ |
2572 |
return env->v7m.control;
|
2573 |
default:
|
2574 |
/* ??? For debugging only. */
|
2575 |
cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
|
2576 |
return 0; |
2577 |
} |
2578 |
} |
2579 |
|
2580 |
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
|
2581 |
{ |
2582 |
switch (reg) {
|
2583 |
case 0: /* APSR */ |
2584 |
xpsr_write(env, val, 0xf8000000);
|
2585 |
break;
|
2586 |
case 1: /* IAPSR */ |
2587 |
xpsr_write(env, val, 0xf8000000);
|
2588 |
break;
|
2589 |
case 2: /* EAPSR */ |
2590 |
xpsr_write(env, val, 0xfe00fc00);
|
2591 |
break;
|
2592 |
case 3: /* xPSR */ |
2593 |
xpsr_write(env, val, 0xfe00fc00);
|
2594 |
break;
|
2595 |
case 5: /* IPSR */ |
2596 |
/* IPSR bits are readonly. */
|
2597 |
break;
|
2598 |
case 6: /* EPSR */ |
2599 |
xpsr_write(env, val, 0x0600fc00);
|
2600 |
break;
|
2601 |
case 7: /* IEPSR */ |
2602 |
xpsr_write(env, val, 0x0600fc00);
|
2603 |
break;
|
2604 |
case 8: /* MSP */ |
2605 |
if (env->v7m.current_sp)
|
2606 |
env->v7m.other_sp = val; |
2607 |
else
|
2608 |
env->regs[13] = val;
|
2609 |
break;
|
2610 |
case 9: /* PSP */ |
2611 |
if (env->v7m.current_sp)
|
2612 |
env->regs[13] = val;
|
2613 |
else
|
2614 |
env->v7m.other_sp = val; |
2615 |
break;
|
2616 |
case 16: /* PRIMASK */ |
2617 |
if (val & 1) |
2618 |
env->uncached_cpsr |= CPSR_I; |
2619 |
else
|
2620 |
env->uncached_cpsr &= ~CPSR_I; |
2621 |
break;
|
2622 |
case 17: /* BASEPRI */ |
2623 |
env->v7m.basepri = val & 0xff;
|
2624 |
break;
|
2625 |
case 18: /* BASEPRI_MAX */ |
2626 |
val &= 0xff;
|
2627 |
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) |
2628 |
env->v7m.basepri = val; |
2629 |
break;
|
2630 |
case 19: /* FAULTMASK */ |
2631 |
if (val & 1) |
2632 |
env->uncached_cpsr |= CPSR_F; |
2633 |
else
|
2634 |
env->uncached_cpsr &= ~CPSR_F; |
2635 |
break;
|
2636 |
case 20: /* CONTROL */ |
2637 |
env->v7m.control = val & 3;
|
2638 |
switch_v7m_sp(env, (val & 2) != 0); |
2639 |
break;
|
2640 |
default:
|
2641 |
/* ??? For debugging only. */
|
2642 |
cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
|
2643 |
return;
|
2644 |
} |
2645 |
} |
2646 |
|
2647 |
#endif
|
2648 |
|
2649 |
/* Note that signed overflow is undefined in C. The following routines are
|
2650 |
careful to use unsigned types where modulo arithmetic is required.
|
2651 |
Failure to do so _will_ break on newer gcc. */
|
2652 |
|
2653 |
/* Signed saturating arithmetic. */
|
2654 |
|
2655 |
/* Perform 16-bit signed saturating addition. */
|
2656 |
static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
2657 |
{ |
2658 |
uint16_t res; |
2659 |
|
2660 |
res = a + b; |
2661 |
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { |
2662 |
if (a & 0x8000) |
2663 |
res = 0x8000;
|
2664 |
else
|
2665 |
res = 0x7fff;
|
2666 |
} |
2667 |
return res;
|
2668 |
} |
2669 |
|
2670 |
/* Perform 8-bit signed saturating addition. */
|
2671 |
static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
2672 |
{ |
2673 |
uint8_t res; |
2674 |
|
2675 |
res = a + b; |
2676 |
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { |
2677 |
if (a & 0x80) |
2678 |
res = 0x80;
|
2679 |
else
|
2680 |
res = 0x7f;
|
2681 |
} |
2682 |
return res;
|
2683 |
} |
2684 |
|
2685 |
/* Perform 16-bit signed saturating subtraction. */
|
2686 |
static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
2687 |
{ |
2688 |
uint16_t res; |
2689 |
|
2690 |
res = a - b; |
2691 |
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { |
2692 |
if (a & 0x8000) |
2693 |
res = 0x8000;
|
2694 |
else
|
2695 |
res = 0x7fff;
|
2696 |
} |
2697 |
return res;
|
2698 |
} |
2699 |
|
2700 |
/* Perform 8-bit signed saturating subtraction. */
|
2701 |
static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
2702 |
{ |
2703 |
uint8_t res; |
2704 |
|
2705 |
res = a - b; |
2706 |
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { |
2707 |
if (a & 0x80) |
2708 |
res = 0x80;
|
2709 |
else
|
2710 |
res = 0x7f;
|
2711 |
} |
2712 |
return res;
|
2713 |
} |
2714 |
|
2715 |
#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); |
2716 |
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); |
2717 |
#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); |
2718 |
#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); |
2719 |
#define PFX q
|
2720 |
|
2721 |
#include "op_addsub.h" |
2722 |
|
2723 |
/* Unsigned saturating arithmetic. */
|
2724 |
static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
2725 |
{ |
2726 |
uint16_t res; |
2727 |
res = a + b; |
2728 |
if (res < a)
|
2729 |
res = 0xffff;
|
2730 |
return res;
|
2731 |
} |
2732 |
|
2733 |
static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
2734 |
{ |
2735 |
if (a > b)
|
2736 |
return a - b;
|
2737 |
else
|
2738 |
return 0; |
2739 |
} |
2740 |
|
2741 |
static inline uint8_t add8_usat(uint8_t a, uint8_t b) |
2742 |
{ |
2743 |
uint8_t res; |
2744 |
res = a + b; |
2745 |
if (res < a)
|
2746 |
res = 0xff;
|
2747 |
return res;
|
2748 |
} |
2749 |
|
2750 |
static inline uint8_t sub8_usat(uint8_t a, uint8_t b) |
2751 |
{ |
2752 |
if (a > b)
|
2753 |
return a - b;
|
2754 |
else
|
2755 |
return 0; |
2756 |
} |
2757 |
|
2758 |
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); |
2759 |
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); |
2760 |
#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); |
2761 |
#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); |
2762 |
#define PFX uq
|
2763 |
|
2764 |
#include "op_addsub.h" |
2765 |
|
2766 |
/* Signed modulo arithmetic. */
|
2767 |
#define SARITH16(a, b, n, op) do { \ |
2768 |
int32_t sum; \ |
2769 |
sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
2770 |
RESULT(sum, n, 16); \
|
2771 |
if (sum >= 0) \ |
2772 |
ge |= 3 << (n * 2); \ |
2773 |
} while(0) |
2774 |
|
2775 |
#define SARITH8(a, b, n, op) do { \ |
2776 |
int32_t sum; \ |
2777 |
sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
2778 |
RESULT(sum, n, 8); \
|
2779 |
if (sum >= 0) \ |
2780 |
ge |= 1 << n; \
|
2781 |
} while(0) |
2782 |
|
2783 |
|
2784 |
#define ADD16(a, b, n) SARITH16(a, b, n, +)
|
2785 |
#define SUB16(a, b, n) SARITH16(a, b, n, -)
|
2786 |
#define ADD8(a, b, n) SARITH8(a, b, n, +)
|
2787 |
#define SUB8(a, b, n) SARITH8(a, b, n, -)
|
2788 |
#define PFX s
|
2789 |
#define ARITH_GE
|
2790 |
|
2791 |
#include "op_addsub.h" |
2792 |
|
2793 |
/* Unsigned modulo arithmetic. */
|
2794 |
#define ADD16(a, b, n) do { \ |
2795 |
uint32_t sum; \ |
2796 |
sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ |
2797 |
RESULT(sum, n, 16); \
|
2798 |
if ((sum >> 16) == 1) \ |
2799 |
ge |= 3 << (n * 2); \ |
2800 |
} while(0) |
2801 |
|
2802 |
#define ADD8(a, b, n) do { \ |
2803 |
uint32_t sum; \ |
2804 |
sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ |
2805 |
RESULT(sum, n, 8); \
|
2806 |
if ((sum >> 8) == 1) \ |
2807 |
ge |= 1 << n; \
|
2808 |
} while(0) |
2809 |
|
2810 |
#define SUB16(a, b, n) do { \ |
2811 |
uint32_t sum; \ |
2812 |
sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ |
2813 |
RESULT(sum, n, 16); \
|
2814 |
if ((sum >> 16) == 0) \ |
2815 |
ge |= 3 << (n * 2); \ |
2816 |
} while(0) |
2817 |
|
2818 |
#define SUB8(a, b, n) do { \ |
2819 |
uint32_t sum; \ |
2820 |
sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ |
2821 |
RESULT(sum, n, 8); \
|
2822 |
if ((sum >> 8) == 0) \ |
2823 |
ge |= 1 << n; \
|
2824 |
} while(0) |
2825 |
|
2826 |
#define PFX u
|
2827 |
#define ARITH_GE
|
2828 |
|
2829 |
#include "op_addsub.h" |
2830 |
|
2831 |
/* Halved signed arithmetic. */
|
2832 |
#define ADD16(a, b, n) \
|
2833 |
RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) |
2834 |
#define SUB16(a, b, n) \
|
2835 |
RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) |
2836 |
#define ADD8(a, b, n) \
|
2837 |
RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) |
2838 |
#define SUB8(a, b, n) \
|
2839 |
RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) |
2840 |
#define PFX sh
|
2841 |
|
2842 |
#include "op_addsub.h" |
2843 |
|
2844 |
/* Halved unsigned arithmetic. */
|
2845 |
#define ADD16(a, b, n) \
|
2846 |
RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
2847 |
#define SUB16(a, b, n) \
|
2848 |
RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
2849 |
#define ADD8(a, b, n) \
|
2850 |
RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
2851 |
#define SUB8(a, b, n) \
|
2852 |
RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
2853 |
#define PFX uh
|
2854 |
|
2855 |
#include "op_addsub.h" |
2856 |
|
2857 |
static inline uint8_t do_usad(uint8_t a, uint8_t b) |
2858 |
{ |
2859 |
if (a > b)
|
2860 |
return a - b;
|
2861 |
else
|
2862 |
return b - a;
|
2863 |
} |
2864 |
|
2865 |
/* Unsigned sum of absolute byte differences. */
|
2866 |
uint32_t HELPER(usad8)(uint32_t a, uint32_t b) |
2867 |
{ |
2868 |
uint32_t sum; |
2869 |
sum = do_usad(a, b); |
2870 |
sum += do_usad(a >> 8, b >> 8); |
2871 |
sum += do_usad(a >> 16, b >>16); |
2872 |
sum += do_usad(a >> 24, b >> 24); |
2873 |
return sum;
|
2874 |
} |
2875 |
|
2876 |
/* For ARMv6 SEL instruction. */
|
2877 |
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) |
2878 |
{ |
2879 |
uint32_t mask; |
2880 |
|
2881 |
mask = 0;
|
2882 |
if (flags & 1) |
2883 |
mask |= 0xff;
|
2884 |
if (flags & 2) |
2885 |
mask |= 0xff00;
|
2886 |
if (flags & 4) |
2887 |
mask |= 0xff0000;
|
2888 |
if (flags & 8) |
2889 |
mask |= 0xff000000;
|
2890 |
return (a & mask) | (b & ~mask);
|
2891 |
} |
2892 |
|
2893 |
uint32_t HELPER(logicq_cc)(uint64_t val) |
2894 |
{ |
2895 |
return (val >> 32) | (val != 0); |
2896 |
} |
2897 |
|
2898 |
/* VFP support. We follow the convention used for VFP instructions:
|
2899 |
Single precision routines have a "s" suffix, double precision a
|
2900 |
"d" suffix. */
|
2901 |
|
2902 |
/* Convert host exception flags to vfp form. */
|
2903 |
static inline int vfp_exceptbits_from_host(int host_bits) |
2904 |
{ |
2905 |
int target_bits = 0; |
2906 |
|
2907 |
if (host_bits & float_flag_invalid)
|
2908 |
target_bits |= 1;
|
2909 |
if (host_bits & float_flag_divbyzero)
|
2910 |
target_bits |= 2;
|
2911 |
if (host_bits & float_flag_overflow)
|
2912 |
target_bits |= 4;
|
2913 |
if (host_bits & (float_flag_underflow | float_flag_output_denormal))
|
2914 |
target_bits |= 8;
|
2915 |
if (host_bits & float_flag_inexact)
|
2916 |
target_bits |= 0x10;
|
2917 |
if (host_bits & float_flag_input_denormal)
|
2918 |
target_bits |= 0x80;
|
2919 |
return target_bits;
|
2920 |
} |
2921 |
|
2922 |
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
2923 |
{ |
2924 |
int i;
|
2925 |
uint32_t fpscr; |
2926 |
|
2927 |
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
|
2928 |
| (env->vfp.vec_len << 16)
|
2929 |
| (env->vfp.vec_stride << 20);
|
2930 |
i = get_float_exception_flags(&env->vfp.fp_status); |
2931 |
i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
2932 |
fpscr |= vfp_exceptbits_from_host(i); |
2933 |
return fpscr;
|
2934 |
} |
2935 |
|
2936 |
uint32_t vfp_get_fpscr(CPUARMState *env) |
2937 |
{ |
2938 |
return HELPER(vfp_get_fpscr)(env);
|
2939 |
} |
2940 |
|
2941 |
/* Convert vfp exception flags to target form. */
|
2942 |
static inline int vfp_exceptbits_to_host(int target_bits) |
2943 |
{ |
2944 |
int host_bits = 0; |
2945 |
|
2946 |
if (target_bits & 1) |
2947 |
host_bits |= float_flag_invalid; |
2948 |
if (target_bits & 2) |
2949 |
host_bits |= float_flag_divbyzero; |
2950 |
if (target_bits & 4) |
2951 |
host_bits |= float_flag_overflow; |
2952 |
if (target_bits & 8) |
2953 |
host_bits |= float_flag_underflow; |
2954 |
if (target_bits & 0x10) |
2955 |
host_bits |= float_flag_inexact; |
2956 |
if (target_bits & 0x80) |
2957 |
host_bits |= float_flag_input_denormal; |
2958 |
return host_bits;
|
2959 |
} |
2960 |
|
2961 |
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
|
2962 |
{ |
2963 |
int i;
|
2964 |
uint32_t changed; |
2965 |
|
2966 |
changed = env->vfp.xregs[ARM_VFP_FPSCR]; |
2967 |
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
|
2968 |
env->vfp.vec_len = (val >> 16) & 7; |
2969 |
env->vfp.vec_stride = (val >> 20) & 3; |
2970 |
|
2971 |
changed ^= val; |
2972 |
if (changed & (3 << 22)) { |
2973 |
i = (val >> 22) & 3; |
2974 |
switch (i) {
|
2975 |
case 0: |
2976 |
i = float_round_nearest_even; |
2977 |
break;
|
2978 |
case 1: |
2979 |
i = float_round_up; |
2980 |
break;
|
2981 |
case 2: |
2982 |
i = float_round_down; |
2983 |
break;
|
2984 |
case 3: |
2985 |
i = float_round_to_zero; |
2986 |
break;
|
2987 |
} |
2988 |
set_float_rounding_mode(i, &env->vfp.fp_status); |
2989 |
} |
2990 |
if (changed & (1 << 24)) { |
2991 |
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
2992 |
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
2993 |
} |
2994 |
if (changed & (1 << 25)) |
2995 |
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); |
2996 |
|
2997 |
i = vfp_exceptbits_to_host(val); |
2998 |
set_float_exception_flags(i, &env->vfp.fp_status); |
2999 |
set_float_exception_flags(0, &env->vfp.standard_fp_status);
|
3000 |
} |
3001 |
|
3002 |
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
|
3003 |
{ |
3004 |
HELPER(vfp_set_fpscr)(env, val); |
3005 |
} |
3006 |
|
3007 |
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
|
3008 |
|
3009 |
#define VFP_BINOP(name) \
|
3010 |
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
|
3011 |
{ \ |
3012 |
float_status *fpst = fpstp; \ |
3013 |
return float32_ ## name(a, b, fpst); \ |
3014 |
} \ |
3015 |
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
|
3016 |
{ \ |
3017 |
float_status *fpst = fpstp; \ |
3018 |
return float64_ ## name(a, b, fpst); \ |
3019 |
} |
3020 |
VFP_BINOP(add) |
3021 |
VFP_BINOP(sub) |
3022 |
VFP_BINOP(mul) |
3023 |
VFP_BINOP(div) |
3024 |
#undef VFP_BINOP
|
3025 |
|
3026 |
float32 VFP_HELPER(neg, s)(float32 a) |
3027 |
{ |
3028 |
return float32_chs(a);
|
3029 |
} |
3030 |
|
3031 |
float64 VFP_HELPER(neg, d)(float64 a) |
3032 |
{ |
3033 |
return float64_chs(a);
|
3034 |
} |
3035 |
|
3036 |
float32 VFP_HELPER(abs, s)(float32 a) |
3037 |
{ |
3038 |
return float32_abs(a);
|
3039 |
} |
3040 |
|
3041 |
float64 VFP_HELPER(abs, d)(float64 a) |
3042 |
{ |
3043 |
return float64_abs(a);
|
3044 |
} |
3045 |
|
3046 |
float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
3047 |
{ |
3048 |
return float32_sqrt(a, &env->vfp.fp_status);
|
3049 |
} |
3050 |
|
3051 |
float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
3052 |
{ |
3053 |
return float64_sqrt(a, &env->vfp.fp_status);
|
3054 |
} |
3055 |
|
3056 |
/* XXX: check quiet/signaling case */
|
3057 |
#define DO_VFP_cmp(p, type) \
|
3058 |
void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
|
3059 |
{ \ |
3060 |
uint32_t flags; \ |
3061 |
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ |
3062 |
case 0: flags = 0x6; break; \ |
3063 |
case -1: flags = 0x8; break; \ |
3064 |
case 1: flags = 0x2; break; \ |
3065 |
default: case 2: flags = 0x3; break; \ |
3066 |
} \ |
3067 |
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
3068 |
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
3069 |
} \ |
3070 |
void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
|
3071 |
{ \ |
3072 |
uint32_t flags; \ |
3073 |
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ |
3074 |
case 0: flags = 0x6; break; \ |
3075 |
case -1: flags = 0x8; break; \ |
3076 |
case 1: flags = 0x2; break; \ |
3077 |
default: case 2: flags = 0x3; break; \ |
3078 |
} \ |
3079 |
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
3080 |
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
3081 |
} |
3082 |
DO_VFP_cmp(s, float32) |
3083 |
DO_VFP_cmp(d, float64) |
3084 |
#undef DO_VFP_cmp
|
3085 |
|
3086 |
/* Integer to float and float to integer conversions */
|
3087 |
|
3088 |
#define CONV_ITOF(name, fsz, sign) \
|
3089 |
float##fsz HELPER(name)(uint32_t x, void *fpstp) \ |
3090 |
{ \ |
3091 |
float_status *fpst = fpstp; \ |
3092 |
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
3093 |
} |
3094 |
|
3095 |
#define CONV_FTOI(name, fsz, sign, round) \
|
3096 |
uint32_t HELPER(name)(float##fsz x, void *fpstp) \ |
3097 |
{ \ |
3098 |
float_status *fpst = fpstp; \ |
3099 |
if (float##fsz##_is_any_nan(x)) { \ |
3100 |
float_raise(float_flag_invalid, fpst); \ |
3101 |
return 0; \ |
3102 |
} \ |
3103 |
return float##fsz##_to_##sign##int32##round(x, fpst); \ |
3104 |
} |
3105 |
|
3106 |
#define FLOAT_CONVS(name, p, fsz, sign) \
|
3107 |
CONV_ITOF(vfp_##name##to##p, fsz, sign) \ |
3108 |
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ |
3109 |
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) |
3110 |
|
3111 |
FLOAT_CONVS(si, s, 32, )
|
3112 |
FLOAT_CONVS(si, d, 64, )
|
3113 |
FLOAT_CONVS(ui, s, 32, u)
|
3114 |
FLOAT_CONVS(ui, d, 64, u)
|
3115 |
|
3116 |
#undef CONV_ITOF
|
3117 |
#undef CONV_FTOI
|
3118 |
#undef FLOAT_CONVS
|
3119 |
|
3120 |
/* floating point conversion */
|
3121 |
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
3122 |
{ |
3123 |
float64 r = float32_to_float64(x, &env->vfp.fp_status); |
3124 |
/* ARM requires that S<->D conversion of any kind of NaN generates
|
3125 |
* a quiet NaN by forcing the most significant frac bit to 1.
|
3126 |
*/
|
3127 |
return float64_maybe_silence_nan(r);
|
3128 |
} |
3129 |
|
3130 |
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
3131 |
{ |
3132 |
float32 r = float64_to_float32(x, &env->vfp.fp_status); |
3133 |
/* ARM requires that S<->D conversion of any kind of NaN generates
|
3134 |
* a quiet NaN by forcing the most significant frac bit to 1.
|
3135 |
*/
|
3136 |
return float32_maybe_silence_nan(r);
|
3137 |
} |
3138 |
|
3139 |
/* VFP3 fixed point conversion. */
|
3140 |
#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
|
3141 |
float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \ |
3142 |
void *fpstp) \
|
3143 |
{ \ |
3144 |
float_status *fpst = fpstp; \ |
3145 |
float##fsz tmp; \ |
3146 |
tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \ |
3147 |
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
3148 |
} \ |
3149 |
uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \ |
3150 |
void *fpstp) \
|
3151 |
{ \ |
3152 |
float_status *fpst = fpstp; \ |
3153 |
float##fsz tmp; \ |
3154 |
if (float##fsz##_is_any_nan(x)) { \ |
3155 |
float_raise(float_flag_invalid, fpst); \ |
3156 |
return 0; \ |
3157 |
} \ |
3158 |
tmp = float##fsz##_scalbn(x, shift, fpst); \ |
3159 |
return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \ |
3160 |
} |
3161 |
|
3162 |
VFP_CONV_FIX(sh, d, 64, int16, )
|
3163 |
VFP_CONV_FIX(sl, d, 64, int32, )
|
3164 |
VFP_CONV_FIX(uh, d, 64, uint16, u)
|
3165 |
VFP_CONV_FIX(ul, d, 64, uint32, u)
|
3166 |
VFP_CONV_FIX(sh, s, 32, int16, )
|
3167 |
VFP_CONV_FIX(sl, s, 32, int32, )
|
3168 |
VFP_CONV_FIX(uh, s, 32, uint16, u)
|
3169 |
VFP_CONV_FIX(ul, s, 32, uint32, u)
|
3170 |
#undef VFP_CONV_FIX
|
3171 |
|
3172 |
/* Half precision conversions. */
|
3173 |
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
|
3174 |
{ |
3175 |
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
3176 |
float32 r = float16_to_float32(make_float16(a), ieee, s); |
3177 |
if (ieee) {
|
3178 |
return float32_maybe_silence_nan(r);
|
3179 |
} |
3180 |
return r;
|
3181 |
} |
3182 |
|
3183 |
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
|
3184 |
{ |
3185 |
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
3186 |
float16 r = float32_to_float16(a, ieee, s); |
3187 |
if (ieee) {
|
3188 |
r = float16_maybe_silence_nan(r); |
3189 |
} |
3190 |
return float16_val(r);
|
3191 |
} |
3192 |
|
3193 |
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
3194 |
{ |
3195 |
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
|
3196 |
} |
3197 |
|
3198 |
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
3199 |
{ |
3200 |
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
|
3201 |
} |
3202 |
|
3203 |
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
3204 |
{ |
3205 |
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
|
3206 |
} |
3207 |
|
3208 |
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
3209 |
{ |
3210 |
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
|
3211 |
} |
3212 |
|
3213 |
#define float32_two make_float32(0x40000000) |
3214 |
#define float32_three make_float32(0x40400000) |
3215 |
#define float32_one_point_five make_float32(0x3fc00000) |
3216 |
|
3217 |
float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
3218 |
{ |
3219 |
float_status *s = &env->vfp.standard_fp_status; |
3220 |
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
|
3221 |
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { |
3222 |
if (!(float32_is_zero(a) || float32_is_zero(b))) {
|
3223 |
float_raise(float_flag_input_denormal, s); |
3224 |
} |
3225 |
return float32_two;
|
3226 |
} |
3227 |
return float32_sub(float32_two, float32_mul(a, b, s), s);
|
3228 |
} |
3229 |
|
3230 |
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
3231 |
{ |
3232 |
float_status *s = &env->vfp.standard_fp_status; |
3233 |
float32 product; |
3234 |
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
|
3235 |
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { |
3236 |
if (!(float32_is_zero(a) || float32_is_zero(b))) {
|
3237 |
float_raise(float_flag_input_denormal, s); |
3238 |
} |
3239 |
return float32_one_point_five;
|
3240 |
} |
3241 |
product = float32_mul(a, b, s); |
3242 |
return float32_div(float32_sub(float32_three, product, s), float32_two, s);
|
3243 |
} |
3244 |
|
3245 |
/* NEON helpers. */
|
3246 |
|
3247 |
/* Constants 256 and 512 are used in some helpers; we avoid relying on
|
3248 |
* int->float conversions at run-time. */
|
3249 |
#define float64_256 make_float64(0x4070000000000000LL) |
3250 |
#define float64_512 make_float64(0x4080000000000000LL) |
3251 |
|
3252 |
/* The algorithm that must be used to calculate the estimate
|
3253 |
* is specified by the ARM ARM.
|
3254 |
*/
|
3255 |
static float64 recip_estimate(float64 a, CPUARMState *env)
|
3256 |
{ |
3257 |
/* These calculations mustn't set any fp exception flags,
|
3258 |
* so we use a local copy of the fp_status.
|
3259 |
*/
|
3260 |
float_status dummy_status = env->vfp.standard_fp_status; |
3261 |
float_status *s = &dummy_status; |
3262 |
/* q = (int)(a * 512.0) */
|
3263 |
float64 q = float64_mul(float64_512, a, s); |
3264 |
int64_t q_int = float64_to_int64_round_to_zero(q, s); |
3265 |
|
3266 |
/* r = 1.0 / (((double)q + 0.5) / 512.0) */
|
3267 |
q = int64_to_float64(q_int, s); |
3268 |
q = float64_add(q, float64_half, s); |
3269 |
q = float64_div(q, float64_512, s); |
3270 |
q = float64_div(float64_one, q, s); |
3271 |
|
3272 |
/* s = (int)(256.0 * r + 0.5) */
|
3273 |
q = float64_mul(q, float64_256, s); |
3274 |
q = float64_add(q, float64_half, s); |
3275 |
q_int = float64_to_int64_round_to_zero(q, s); |
3276 |
|
3277 |
/* return (double)s / 256.0 */
|
3278 |
return float64_div(int64_to_float64(q_int, s), float64_256, s);
|
3279 |
} |
3280 |
|
3281 |
float32 HELPER(recpe_f32)(float32 a, CPUARMState *env) |
3282 |
{ |
3283 |
float_status *s = &env->vfp.standard_fp_status; |
3284 |
float64 f64; |
3285 |
uint32_t val32 = float32_val(a); |
3286 |
|
3287 |
int result_exp;
|
3288 |
int a_exp = (val32 & 0x7f800000) >> 23; |
3289 |
int sign = val32 & 0x80000000; |
3290 |
|
3291 |
if (float32_is_any_nan(a)) {
|
3292 |
if (float32_is_signaling_nan(a)) {
|
3293 |
float_raise(float_flag_invalid, s); |
3294 |
} |
3295 |
return float32_default_nan;
|
3296 |
} else if (float32_is_infinity(a)) { |
3297 |
return float32_set_sign(float32_zero, float32_is_neg(a));
|
3298 |
} else if (float32_is_zero_or_denormal(a)) { |
3299 |
if (!float32_is_zero(a)) {
|
3300 |
float_raise(float_flag_input_denormal, s); |
3301 |
} |
3302 |
float_raise(float_flag_divbyzero, s); |
3303 |
return float32_set_sign(float32_infinity, float32_is_neg(a));
|
3304 |
} else if (a_exp >= 253) { |
3305 |
float_raise(float_flag_underflow, s); |
3306 |
return float32_set_sign(float32_zero, float32_is_neg(a));
|
3307 |
} |
3308 |
|
3309 |
f64 = make_float64((0x3feULL << 52) |
3310 |
| ((int64_t)(val32 & 0x7fffff) << 29)); |
3311 |
|
3312 |
result_exp = 253 - a_exp;
|
3313 |
|
3314 |
f64 = recip_estimate(f64, env); |
3315 |
|
3316 |
val32 = sign |
3317 |
| ((result_exp & 0xff) << 23) |
3318 |
| ((float64_val(f64) >> 29) & 0x7fffff); |
3319 |
return make_float32(val32);
|
3320 |
} |
3321 |
|
3322 |
/* The algorithm that must be used to calculate the estimate
|
3323 |
* is specified by the ARM ARM.
|
3324 |
*/
|
3325 |
static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
|
3326 |
{ |
3327 |
/* These calculations mustn't set any fp exception flags,
|
3328 |
* so we use a local copy of the fp_status.
|
3329 |
*/
|
3330 |
float_status dummy_status = env->vfp.standard_fp_status; |
3331 |
float_status *s = &dummy_status; |
3332 |
float64 q; |
3333 |
int64_t q_int; |
3334 |
|
3335 |
if (float64_lt(a, float64_half, s)) {
|
3336 |
/* range 0.25 <= a < 0.5 */
|
3337 |
|
3338 |
/* a in units of 1/512 rounded down */
|
3339 |
/* q0 = (int)(a * 512.0); */
|
3340 |
q = float64_mul(float64_512, a, s); |
3341 |
q_int = float64_to_int64_round_to_zero(q, s); |
3342 |
|
3343 |
/* reciprocal root r */
|
3344 |
/* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
|
3345 |
q = int64_to_float64(q_int, s); |
3346 |
q = float64_add(q, float64_half, s); |
3347 |
q = float64_div(q, float64_512, s); |
3348 |
q = float64_sqrt(q, s); |
3349 |
q = float64_div(float64_one, q, s); |
3350 |
} else {
|
3351 |
/* range 0.5 <= a < 1.0 */
|
3352 |
|
3353 |
/* a in units of 1/256 rounded down */
|
3354 |
/* q1 = (int)(a * 256.0); */
|
3355 |
q = float64_mul(float64_256, a, s); |
3356 |
int64_t q_int = float64_to_int64_round_to_zero(q, s); |
3357 |
|
3358 |
/* reciprocal root r */
|
3359 |
/* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
|
3360 |
q = int64_to_float64(q_int, s); |
3361 |
q = float64_add(q, float64_half, s); |
3362 |
q = float64_div(q, float64_256, s); |
3363 |
q = float64_sqrt(q, s); |
3364 |
q = float64_div(float64_one, q, s); |
3365 |
} |
3366 |
/* r in units of 1/256 rounded to nearest */
|
3367 |
/* s = (int)(256.0 * r + 0.5); */
|
3368 |
|
3369 |
q = float64_mul(q, float64_256,s ); |
3370 |
q = float64_add(q, float64_half, s); |
3371 |
q_int = float64_to_int64_round_to_zero(q, s); |
3372 |
|
3373 |
/* return (double)s / 256.0;*/
|
3374 |
return float64_div(int64_to_float64(q_int, s), float64_256, s);
|
3375 |
} |
3376 |
|
3377 |
float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env) |
3378 |
{ |
3379 |
float_status *s = &env->vfp.standard_fp_status; |
3380 |
int result_exp;
|
3381 |
float64 f64; |
3382 |
uint32_t val; |
3383 |
uint64_t val64; |
3384 |
|
3385 |
val = float32_val(a); |
3386 |
|
3387 |
if (float32_is_any_nan(a)) {
|
3388 |
if (float32_is_signaling_nan(a)) {
|
3389 |
float_raise(float_flag_invalid, s); |
3390 |
} |
3391 |
return float32_default_nan;
|
3392 |
} else if (float32_is_zero_or_denormal(a)) { |
3393 |
if (!float32_is_zero(a)) {
|
3394 |
float_raise(float_flag_input_denormal, s); |
3395 |
} |
3396 |
float_raise(float_flag_divbyzero, s); |
3397 |
return float32_set_sign(float32_infinity, float32_is_neg(a));
|
3398 |
} else if (float32_is_neg(a)) { |
3399 |
float_raise(float_flag_invalid, s); |
3400 |
return float32_default_nan;
|
3401 |
} else if (float32_is_infinity(a)) { |
3402 |
return float32_zero;
|
3403 |
} |
3404 |
|
3405 |
/* Normalize to a double-precision value between 0.25 and 1.0,
|
3406 |
* preserving the parity of the exponent. */
|
3407 |
if ((val & 0x800000) == 0) { |
3408 |
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) |
3409 |
| (0x3feULL << 52) |
3410 |
| ((uint64_t)(val & 0x7fffff) << 29)); |
3411 |
} else {
|
3412 |
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) |
3413 |
| (0x3fdULL << 52) |
3414 |
| ((uint64_t)(val & 0x7fffff) << 29)); |
3415 |
} |
3416 |
|
3417 |
result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2; |
3418 |
|
3419 |
f64 = recip_sqrt_estimate(f64, env); |
3420 |
|
3421 |
val64 = float64_val(f64); |
3422 |
|
3423 |
val = ((result_exp & 0xff) << 23) |
3424 |
| ((val64 >> 29) & 0x7fffff); |
3425 |
return make_float32(val);
|
3426 |
} |
3427 |
|
3428 |
uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env) |
3429 |
{ |
3430 |
float64 f64; |
3431 |
|
3432 |
if ((a & 0x80000000) == 0) { |
3433 |
return 0xffffffff; |
3434 |
} |
3435 |
|
3436 |
f64 = make_float64((0x3feULL << 52) |
3437 |
| ((int64_t)(a & 0x7fffffff) << 21)); |
3438 |
|
3439 |
f64 = recip_estimate (f64, env); |
3440 |
|
3441 |
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); |
3442 |
} |
3443 |
|
3444 |
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env) |
3445 |
{ |
3446 |
float64 f64; |
3447 |
|
3448 |
if ((a & 0xc0000000) == 0) { |
3449 |
return 0xffffffff; |
3450 |
} |
3451 |
|
3452 |
if (a & 0x80000000) { |
3453 |
f64 = make_float64((0x3feULL << 52) |
3454 |
| ((uint64_t)(a & 0x7fffffff) << 21)); |
3455 |
} else { /* bits 31-30 == '01' */ |
3456 |
f64 = make_float64((0x3fdULL << 52) |
3457 |
| ((uint64_t)(a & 0x3fffffff) << 22)); |
3458 |
} |
3459 |
|
3460 |
f64 = recip_sqrt_estimate(f64, env); |
3461 |
|
3462 |
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); |
3463 |
} |
3464 |
|
3465 |
/* VFPv4 fused multiply-accumulate */
|
3466 |
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
|
3467 |
{ |
3468 |
float_status *fpst = fpstp; |
3469 |
return float32_muladd(a, b, c, 0, fpst); |
3470 |
} |
3471 |
|
3472 |
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
|
3473 |
{ |
3474 |
float_status *fpst = fpstp; |
3475 |
return float64_muladd(a, b, c, 0, fpst); |
3476 |
} |