root / target-openrisc / interrupt.c @ 1de7afc9
History | View | Annotate | Download (2.4 kB)
| 1 |
/*
|
|---|---|
| 2 |
* OpenRISC interrupt.
|
| 3 |
*
|
| 4 |
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
|
| 5 |
*
|
| 6 |
* This library is free software; you can redistribute it and/or
|
| 7 |
* modify it under the terms of the GNU Lesser General Public
|
| 8 |
* License as published by the Free Software Foundation; either
|
| 9 |
* version 2 of the License, or (at your option) any later version.
|
| 10 |
*
|
| 11 |
* This library is distributed in the hope that it will be useful,
|
| 12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
| 14 |
* Lesser General Public License for more details.
|
| 15 |
*
|
| 16 |
* You should have received a copy of the GNU Lesser General Public
|
| 17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
| 18 |
*/
|
| 19 |
|
| 20 |
#include "cpu.h" |
| 21 |
#include "qemu-common.h" |
| 22 |
#include "exec/gdbstub.h" |
| 23 |
#include "qemu/host-utils.h" |
| 24 |
#ifndef CONFIG_USER_ONLY
|
| 25 |
#include "hw/loader.h" |
| 26 |
#endif
|
| 27 |
|
| 28 |
void do_interrupt(CPUOpenRISCState *env)
|
| 29 |
{
|
| 30 |
#ifndef CONFIG_USER_ONLY
|
| 31 |
if (env->flags & D_FLAG) { /* Delay Slot insn */ |
| 32 |
env->flags &= ~D_FLAG; |
| 33 |
env->sr |= SR_DSX; |
| 34 |
if (env->exception_index == EXCP_TICK ||
|
| 35 |
env->exception_index == EXCP_INT || |
| 36 |
env->exception_index == EXCP_SYSCALL || |
| 37 |
env->exception_index == EXCP_FPE) {
|
| 38 |
env->epcr = env->jmp_pc; |
| 39 |
} else {
|
| 40 |
env->epcr = env->pc - 4;
|
| 41 |
} |
| 42 |
} else {
|
| 43 |
if (env->exception_index == EXCP_TICK ||
|
| 44 |
env->exception_index == EXCP_INT || |
| 45 |
env->exception_index == EXCP_SYSCALL || |
| 46 |
env->exception_index == EXCP_FPE) {
|
| 47 |
env->epcr = env->npc; |
| 48 |
} else {
|
| 49 |
env->epcr = env->pc; |
| 50 |
} |
| 51 |
} |
| 52 |
|
| 53 |
/* For machine-state changed between user-mode and supervisor mode,
|
| 54 |
we need flush TLB when we enter&exit EXCP. */
|
| 55 |
tlb_flush(env, 1);
|
| 56 |
|
| 57 |
env->esr = env->sr; |
| 58 |
env->sr &= ~SR_DME; |
| 59 |
env->sr &= ~SR_IME; |
| 60 |
env->sr |= SR_SM; |
| 61 |
env->sr &= ~SR_IEE; |
| 62 |
env->sr &= ~SR_TEE; |
| 63 |
env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; |
| 64 |
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; |
| 65 |
|
| 66 |
if (env->exception_index > 0 && env->exception_index < EXCP_NR) { |
| 67 |
env->pc = (env->exception_index << 8);
|
| 68 |
} else {
|
| 69 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
| 70 |
} |
| 71 |
#endif
|
| 72 |
|
| 73 |
env->exception_index = -1;
|
| 74 |
} |