Revision 1e4840bf target-i386/cpu.h
| b/target-i386/cpu.h | ||
|---|---|---|
| 472 | 472 |
#define NB_MMU_MODES 2 |
| 473 | 473 |
|
| 474 | 474 |
typedef struct CPUX86State {
|
| 475 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
|
| 476 |
/* temporaries if we cannot store them in host registers */ |
|
| 477 |
target_ulong t0, t1, t2; |
|
| 478 |
#endif |
|
| 479 |
target_ulong t3; |
|
| 480 |
|
|
| 481 | 475 |
/* standard registers */ |
| 482 | 476 |
target_ulong regs[CPU_NB_REGS]; |
| 483 | 477 |
target_ulong eip; |
| ... | ... | |
| 526 | 520 |
XMMReg xmm_regs[CPU_NB_REGS]; |
| 527 | 521 |
XMMReg xmm_t0; |
| 528 | 522 |
MMXReg mmx_t0; |
| 523 |
target_ulong cc_tmp; /* temporary for rcr/rcl */ |
|
| 529 | 524 |
|
| 530 | 525 |
/* sysenter registers */ |
| 531 | 526 |
uint32_t sysenter_cs; |
Also available in: Unified diff