root / target-i386 / ops_sse.h @ 1e6eec8b
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1 | 664e0f19 | bellard | /*
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2 | 222a3336 | balrog | * MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support
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3 | 5fafdf24 | ths | *
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4 | 664e0f19 | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 222a3336 | balrog | * Copyright (c) 2008 Intel Corporation <andrew.zaborowski@intel.com>
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6 | 664e0f19 | bellard | *
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7 | 664e0f19 | bellard | * This library is free software; you can redistribute it and/or
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8 | 664e0f19 | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 664e0f19 | bellard | * License as published by the Free Software Foundation; either
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10 | 664e0f19 | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 664e0f19 | bellard | *
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12 | 664e0f19 | bellard | * This library is distributed in the hope that it will be useful,
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13 | 664e0f19 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 664e0f19 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 664e0f19 | bellard | * Lesser General Public License for more details.
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16 | 664e0f19 | bellard | *
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17 | 664e0f19 | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 664e0f19 | bellard | */
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20 | 664e0f19 | bellard | #if SHIFT == 0 |
21 | 664e0f19 | bellard | #define Reg MMXReg
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22 | 001faf32 | Blue Swirl | #define XMM_ONLY(...)
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23 | 664e0f19 | bellard | #define B(n) MMX_B(n)
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24 | 664e0f19 | bellard | #define W(n) MMX_W(n)
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25 | 664e0f19 | bellard | #define L(n) MMX_L(n)
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26 | 664e0f19 | bellard | #define Q(n) q
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27 | 664e0f19 | bellard | #define SUFFIX _mmx
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28 | 664e0f19 | bellard | #else
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29 | 664e0f19 | bellard | #define Reg XMMReg
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30 | 001faf32 | Blue Swirl | #define XMM_ONLY(...) __VA_ARGS__
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31 | 664e0f19 | bellard | #define B(n) XMM_B(n)
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32 | 664e0f19 | bellard | #define W(n) XMM_W(n)
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33 | 664e0f19 | bellard | #define L(n) XMM_L(n)
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34 | 664e0f19 | bellard | #define Q(n) XMM_Q(n)
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35 | 664e0f19 | bellard | #define SUFFIX _xmm
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36 | 664e0f19 | bellard | #endif
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37 | 664e0f19 | bellard | |
38 | 5af45186 | bellard | void glue(helper_psrlw, SUFFIX)(Reg *d, Reg *s)
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39 | 664e0f19 | bellard | { |
40 | 664e0f19 | bellard | int shift;
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41 | 664e0f19 | bellard | |
42 | 664e0f19 | bellard | if (s->Q(0) > 15) { |
43 | 664e0f19 | bellard | d->Q(0) = 0; |
44 | 664e0f19 | bellard | #if SHIFT == 1 |
45 | 664e0f19 | bellard | d->Q(1) = 0; |
46 | 664e0f19 | bellard | #endif
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47 | 664e0f19 | bellard | } else {
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48 | 664e0f19 | bellard | shift = s->B(0);
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49 | 664e0f19 | bellard | d->W(0) >>= shift;
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50 | 664e0f19 | bellard | d->W(1) >>= shift;
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51 | 664e0f19 | bellard | d->W(2) >>= shift;
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52 | 664e0f19 | bellard | d->W(3) >>= shift;
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53 | 664e0f19 | bellard | #if SHIFT == 1 |
54 | 664e0f19 | bellard | d->W(4) >>= shift;
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55 | 664e0f19 | bellard | d->W(5) >>= shift;
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56 | 664e0f19 | bellard | d->W(6) >>= shift;
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57 | 664e0f19 | bellard | d->W(7) >>= shift;
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58 | 664e0f19 | bellard | #endif
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59 | 664e0f19 | bellard | } |
60 | 664e0f19 | bellard | } |
61 | 664e0f19 | bellard | |
62 | 5af45186 | bellard | void glue(helper_psraw, SUFFIX)(Reg *d, Reg *s)
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63 | 664e0f19 | bellard | { |
64 | 664e0f19 | bellard | int shift;
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65 | 664e0f19 | bellard | |
66 | 664e0f19 | bellard | if (s->Q(0) > 15) { |
67 | 664e0f19 | bellard | shift = 15;
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68 | 664e0f19 | bellard | } else {
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69 | 664e0f19 | bellard | shift = s->B(0);
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70 | 664e0f19 | bellard | } |
71 | 664e0f19 | bellard | d->W(0) = (int16_t)d->W(0) >> shift; |
72 | 664e0f19 | bellard | d->W(1) = (int16_t)d->W(1) >> shift; |
73 | 664e0f19 | bellard | d->W(2) = (int16_t)d->W(2) >> shift; |
74 | 664e0f19 | bellard | d->W(3) = (int16_t)d->W(3) >> shift; |
75 | 664e0f19 | bellard | #if SHIFT == 1 |
76 | 664e0f19 | bellard | d->W(4) = (int16_t)d->W(4) >> shift; |
77 | 664e0f19 | bellard | d->W(5) = (int16_t)d->W(5) >> shift; |
78 | 664e0f19 | bellard | d->W(6) = (int16_t)d->W(6) >> shift; |
79 | 664e0f19 | bellard | d->W(7) = (int16_t)d->W(7) >> shift; |
80 | 664e0f19 | bellard | #endif
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81 | 664e0f19 | bellard | } |
82 | 664e0f19 | bellard | |
83 | 5af45186 | bellard | void glue(helper_psllw, SUFFIX)(Reg *d, Reg *s)
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84 | 664e0f19 | bellard | { |
85 | 664e0f19 | bellard | int shift;
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86 | 664e0f19 | bellard | |
87 | 664e0f19 | bellard | if (s->Q(0) > 15) { |
88 | 664e0f19 | bellard | d->Q(0) = 0; |
89 | 664e0f19 | bellard | #if SHIFT == 1 |
90 | 664e0f19 | bellard | d->Q(1) = 0; |
91 | 664e0f19 | bellard | #endif
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92 | 664e0f19 | bellard | } else {
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93 | 664e0f19 | bellard | shift = s->B(0);
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94 | 664e0f19 | bellard | d->W(0) <<= shift;
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95 | 664e0f19 | bellard | d->W(1) <<= shift;
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96 | 664e0f19 | bellard | d->W(2) <<= shift;
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97 | 664e0f19 | bellard | d->W(3) <<= shift;
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98 | 664e0f19 | bellard | #if SHIFT == 1 |
99 | 664e0f19 | bellard | d->W(4) <<= shift;
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100 | 664e0f19 | bellard | d->W(5) <<= shift;
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101 | 664e0f19 | bellard | d->W(6) <<= shift;
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102 | 664e0f19 | bellard | d->W(7) <<= shift;
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103 | 664e0f19 | bellard | #endif
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104 | 664e0f19 | bellard | } |
105 | 664e0f19 | bellard | } |
106 | 664e0f19 | bellard | |
107 | 5af45186 | bellard | void glue(helper_psrld, SUFFIX)(Reg *d, Reg *s)
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108 | 664e0f19 | bellard | { |
109 | 664e0f19 | bellard | int shift;
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110 | 664e0f19 | bellard | |
111 | 664e0f19 | bellard | if (s->Q(0) > 31) { |
112 | 664e0f19 | bellard | d->Q(0) = 0; |
113 | 664e0f19 | bellard | #if SHIFT == 1 |
114 | 664e0f19 | bellard | d->Q(1) = 0; |
115 | 664e0f19 | bellard | #endif
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116 | 664e0f19 | bellard | } else {
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117 | 664e0f19 | bellard | shift = s->B(0);
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118 | 664e0f19 | bellard | d->L(0) >>= shift;
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119 | 664e0f19 | bellard | d->L(1) >>= shift;
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120 | 664e0f19 | bellard | #if SHIFT == 1 |
121 | 664e0f19 | bellard | d->L(2) >>= shift;
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122 | 664e0f19 | bellard | d->L(3) >>= shift;
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123 | 664e0f19 | bellard | #endif
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124 | 664e0f19 | bellard | } |
125 | 664e0f19 | bellard | } |
126 | 664e0f19 | bellard | |
127 | 5af45186 | bellard | void glue(helper_psrad, SUFFIX)(Reg *d, Reg *s)
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128 | 664e0f19 | bellard | { |
129 | 664e0f19 | bellard | int shift;
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130 | 664e0f19 | bellard | |
131 | 664e0f19 | bellard | if (s->Q(0) > 31) { |
132 | 664e0f19 | bellard | shift = 31;
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133 | 664e0f19 | bellard | } else {
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134 | 664e0f19 | bellard | shift = s->B(0);
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135 | 664e0f19 | bellard | } |
136 | 664e0f19 | bellard | d->L(0) = (int32_t)d->L(0) >> shift; |
137 | 664e0f19 | bellard | d->L(1) = (int32_t)d->L(1) >> shift; |
138 | 664e0f19 | bellard | #if SHIFT == 1 |
139 | 664e0f19 | bellard | d->L(2) = (int32_t)d->L(2) >> shift; |
140 | 664e0f19 | bellard | d->L(3) = (int32_t)d->L(3) >> shift; |
141 | 664e0f19 | bellard | #endif
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142 | 664e0f19 | bellard | } |
143 | 664e0f19 | bellard | |
144 | 5af45186 | bellard | void glue(helper_pslld, SUFFIX)(Reg *d, Reg *s)
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145 | 664e0f19 | bellard | { |
146 | 664e0f19 | bellard | int shift;
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147 | 664e0f19 | bellard | |
148 | 664e0f19 | bellard | if (s->Q(0) > 31) { |
149 | 664e0f19 | bellard | d->Q(0) = 0; |
150 | 664e0f19 | bellard | #if SHIFT == 1 |
151 | 664e0f19 | bellard | d->Q(1) = 0; |
152 | 664e0f19 | bellard | #endif
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153 | 664e0f19 | bellard | } else {
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154 | 664e0f19 | bellard | shift = s->B(0);
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155 | 664e0f19 | bellard | d->L(0) <<= shift;
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156 | 664e0f19 | bellard | d->L(1) <<= shift;
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157 | 664e0f19 | bellard | #if SHIFT == 1 |
158 | 664e0f19 | bellard | d->L(2) <<= shift;
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159 | 664e0f19 | bellard | d->L(3) <<= shift;
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160 | 664e0f19 | bellard | #endif
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161 | 664e0f19 | bellard | } |
162 | 664e0f19 | bellard | } |
163 | 664e0f19 | bellard | |
164 | 5af45186 | bellard | void glue(helper_psrlq, SUFFIX)(Reg *d, Reg *s)
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165 | 664e0f19 | bellard | { |
166 | 664e0f19 | bellard | int shift;
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167 | 664e0f19 | bellard | |
168 | 664e0f19 | bellard | if (s->Q(0) > 63) { |
169 | 664e0f19 | bellard | d->Q(0) = 0; |
170 | 664e0f19 | bellard | #if SHIFT == 1 |
171 | 664e0f19 | bellard | d->Q(1) = 0; |
172 | 664e0f19 | bellard | #endif
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173 | 664e0f19 | bellard | } else {
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174 | 664e0f19 | bellard | shift = s->B(0);
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175 | 664e0f19 | bellard | d->Q(0) >>= shift;
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176 | 664e0f19 | bellard | #if SHIFT == 1 |
177 | 664e0f19 | bellard | d->Q(1) >>= shift;
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178 | 664e0f19 | bellard | #endif
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179 | 664e0f19 | bellard | } |
180 | 664e0f19 | bellard | } |
181 | 664e0f19 | bellard | |
182 | 5af45186 | bellard | void glue(helper_psllq, SUFFIX)(Reg *d, Reg *s)
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183 | 664e0f19 | bellard | { |
184 | 664e0f19 | bellard | int shift;
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185 | 664e0f19 | bellard | |
186 | 664e0f19 | bellard | if (s->Q(0) > 63) { |
187 | 664e0f19 | bellard | d->Q(0) = 0; |
188 | 664e0f19 | bellard | #if SHIFT == 1 |
189 | 664e0f19 | bellard | d->Q(1) = 0; |
190 | 664e0f19 | bellard | #endif
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191 | 664e0f19 | bellard | } else {
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192 | 664e0f19 | bellard | shift = s->B(0);
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193 | 664e0f19 | bellard | d->Q(0) <<= shift;
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194 | 664e0f19 | bellard | #if SHIFT == 1 |
195 | 664e0f19 | bellard | d->Q(1) <<= shift;
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196 | 664e0f19 | bellard | #endif
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197 | 664e0f19 | bellard | } |
198 | 664e0f19 | bellard | } |
199 | 664e0f19 | bellard | |
200 | 664e0f19 | bellard | #if SHIFT == 1 |
201 | 5af45186 | bellard | void glue(helper_psrldq, SUFFIX)(Reg *d, Reg *s)
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202 | 664e0f19 | bellard | { |
203 | 664e0f19 | bellard | int shift, i;
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204 | 664e0f19 | bellard | |
205 | 664e0f19 | bellard | shift = s->L(0);
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206 | 664e0f19 | bellard | if (shift > 16) |
207 | 664e0f19 | bellard | shift = 16;
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208 | 664e0f19 | bellard | for(i = 0; i < 16 - shift; i++) |
209 | 664e0f19 | bellard | d->B(i) = d->B(i + shift); |
210 | 664e0f19 | bellard | for(i = 16 - shift; i < 16; i++) |
211 | 664e0f19 | bellard | d->B(i) = 0;
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212 | 664e0f19 | bellard | } |
213 | 664e0f19 | bellard | |
214 | 5af45186 | bellard | void glue(helper_pslldq, SUFFIX)(Reg *d, Reg *s)
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215 | 664e0f19 | bellard | { |
216 | 664e0f19 | bellard | int shift, i;
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217 | 664e0f19 | bellard | |
218 | 664e0f19 | bellard | shift = s->L(0);
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219 | 664e0f19 | bellard | if (shift > 16) |
220 | 664e0f19 | bellard | shift = 16;
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221 | 664e0f19 | bellard | for(i = 15; i >= shift; i--) |
222 | 664e0f19 | bellard | d->B(i) = d->B(i - shift); |
223 | 664e0f19 | bellard | for(i = 0; i < shift; i++) |
224 | 664e0f19 | bellard | d->B(i) = 0;
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225 | 664e0f19 | bellard | } |
226 | 664e0f19 | bellard | #endif
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227 | 664e0f19 | bellard | |
228 | 5af45186 | bellard | #define SSE_HELPER_B(name, F)\
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229 | 5af45186 | bellard | void glue(name, SUFFIX) (Reg *d, Reg *s)\
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230 | 664e0f19 | bellard | {\ |
231 | 664e0f19 | bellard | d->B(0) = F(d->B(0), s->B(0));\ |
232 | 664e0f19 | bellard | d->B(1) = F(d->B(1), s->B(1));\ |
233 | 664e0f19 | bellard | d->B(2) = F(d->B(2), s->B(2));\ |
234 | 664e0f19 | bellard | d->B(3) = F(d->B(3), s->B(3));\ |
235 | 664e0f19 | bellard | d->B(4) = F(d->B(4), s->B(4));\ |
236 | 664e0f19 | bellard | d->B(5) = F(d->B(5), s->B(5));\ |
237 | 664e0f19 | bellard | d->B(6) = F(d->B(6), s->B(6));\ |
238 | 664e0f19 | bellard | d->B(7) = F(d->B(7), s->B(7));\ |
239 | 664e0f19 | bellard | XMM_ONLY(\ |
240 | 664e0f19 | bellard | d->B(8) = F(d->B(8), s->B(8));\ |
241 | 664e0f19 | bellard | d->B(9) = F(d->B(9), s->B(9));\ |
242 | 664e0f19 | bellard | d->B(10) = F(d->B(10), s->B(10));\ |
243 | 664e0f19 | bellard | d->B(11) = F(d->B(11), s->B(11));\ |
244 | 664e0f19 | bellard | d->B(12) = F(d->B(12), s->B(12));\ |
245 | 664e0f19 | bellard | d->B(13) = F(d->B(13), s->B(13));\ |
246 | 664e0f19 | bellard | d->B(14) = F(d->B(14), s->B(14));\ |
247 | 664e0f19 | bellard | d->B(15) = F(d->B(15), s->B(15));\ |
248 | 664e0f19 | bellard | )\ |
249 | 664e0f19 | bellard | } |
250 | 664e0f19 | bellard | |
251 | 5af45186 | bellard | #define SSE_HELPER_W(name, F)\
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252 | 5af45186 | bellard | void glue(name, SUFFIX) (Reg *d, Reg *s)\
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253 | 664e0f19 | bellard | {\ |
254 | 664e0f19 | bellard | d->W(0) = F(d->W(0), s->W(0));\ |
255 | 664e0f19 | bellard | d->W(1) = F(d->W(1), s->W(1));\ |
256 | 664e0f19 | bellard | d->W(2) = F(d->W(2), s->W(2));\ |
257 | 664e0f19 | bellard | d->W(3) = F(d->W(3), s->W(3));\ |
258 | 664e0f19 | bellard | XMM_ONLY(\ |
259 | 664e0f19 | bellard | d->W(4) = F(d->W(4), s->W(4));\ |
260 | 664e0f19 | bellard | d->W(5) = F(d->W(5), s->W(5));\ |
261 | 664e0f19 | bellard | d->W(6) = F(d->W(6), s->W(6));\ |
262 | 664e0f19 | bellard | d->W(7) = F(d->W(7), s->W(7));\ |
263 | 664e0f19 | bellard | )\ |
264 | 664e0f19 | bellard | } |
265 | 664e0f19 | bellard | |
266 | 5af45186 | bellard | #define SSE_HELPER_L(name, F)\
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267 | 5af45186 | bellard | void glue(name, SUFFIX) (Reg *d, Reg *s)\
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268 | 664e0f19 | bellard | {\ |
269 | 664e0f19 | bellard | d->L(0) = F(d->L(0), s->L(0));\ |
270 | 664e0f19 | bellard | d->L(1) = F(d->L(1), s->L(1));\ |
271 | 664e0f19 | bellard | XMM_ONLY(\ |
272 | 664e0f19 | bellard | d->L(2) = F(d->L(2), s->L(2));\ |
273 | 664e0f19 | bellard | d->L(3) = F(d->L(3), s->L(3));\ |
274 | 664e0f19 | bellard | )\ |
275 | 664e0f19 | bellard | } |
276 | 664e0f19 | bellard | |
277 | 5af45186 | bellard | #define SSE_HELPER_Q(name, F)\
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278 | 5af45186 | bellard | void glue(name, SUFFIX) (Reg *d, Reg *s)\
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279 | 664e0f19 | bellard | {\ |
280 | 664e0f19 | bellard | d->Q(0) = F(d->Q(0), s->Q(0));\ |
281 | 664e0f19 | bellard | XMM_ONLY(\ |
282 | 664e0f19 | bellard | d->Q(1) = F(d->Q(1), s->Q(1));\ |
283 | 664e0f19 | bellard | )\ |
284 | 664e0f19 | bellard | } |
285 | 664e0f19 | bellard | |
286 | 664e0f19 | bellard | #if SHIFT == 0 |
287 | 664e0f19 | bellard | static inline int satub(int x) |
288 | 664e0f19 | bellard | { |
289 | 664e0f19 | bellard | if (x < 0) |
290 | 664e0f19 | bellard | return 0; |
291 | 664e0f19 | bellard | else if (x > 255) |
292 | 664e0f19 | bellard | return 255; |
293 | 664e0f19 | bellard | else
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294 | 664e0f19 | bellard | return x;
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295 | 664e0f19 | bellard | } |
296 | 664e0f19 | bellard | |
297 | 664e0f19 | bellard | static inline int satuw(int x) |
298 | 664e0f19 | bellard | { |
299 | 664e0f19 | bellard | if (x < 0) |
300 | 664e0f19 | bellard | return 0; |
301 | 664e0f19 | bellard | else if (x > 65535) |
302 | 664e0f19 | bellard | return 65535; |
303 | 664e0f19 | bellard | else
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304 | 664e0f19 | bellard | return x;
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305 | 664e0f19 | bellard | } |
306 | 664e0f19 | bellard | |
307 | 664e0f19 | bellard | static inline int satsb(int x) |
308 | 664e0f19 | bellard | { |
309 | 664e0f19 | bellard | if (x < -128) |
310 | 664e0f19 | bellard | return -128; |
311 | 664e0f19 | bellard | else if (x > 127) |
312 | 664e0f19 | bellard | return 127; |
313 | 664e0f19 | bellard | else
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314 | 664e0f19 | bellard | return x;
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315 | 664e0f19 | bellard | } |
316 | 664e0f19 | bellard | |
317 | 664e0f19 | bellard | static inline int satsw(int x) |
318 | 664e0f19 | bellard | { |
319 | 664e0f19 | bellard | if (x < -32768) |
320 | 664e0f19 | bellard | return -32768; |
321 | 664e0f19 | bellard | else if (x > 32767) |
322 | 664e0f19 | bellard | return 32767; |
323 | 664e0f19 | bellard | else
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324 | 664e0f19 | bellard | return x;
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325 | 664e0f19 | bellard | } |
326 | 664e0f19 | bellard | |
327 | 664e0f19 | bellard | #define FADD(a, b) ((a) + (b))
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328 | 664e0f19 | bellard | #define FADDUB(a, b) satub((a) + (b))
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329 | 664e0f19 | bellard | #define FADDUW(a, b) satuw((a) + (b))
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330 | 664e0f19 | bellard | #define FADDSB(a, b) satsb((int8_t)(a) + (int8_t)(b))
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331 | 664e0f19 | bellard | #define FADDSW(a, b) satsw((int16_t)(a) + (int16_t)(b))
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332 | 664e0f19 | bellard | |
333 | 664e0f19 | bellard | #define FSUB(a, b) ((a) - (b))
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334 | 664e0f19 | bellard | #define FSUBUB(a, b) satub((a) - (b))
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335 | 664e0f19 | bellard | #define FSUBUW(a, b) satuw((a) - (b))
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336 | 664e0f19 | bellard | #define FSUBSB(a, b) satsb((int8_t)(a) - (int8_t)(b))
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337 | 664e0f19 | bellard | #define FSUBSW(a, b) satsw((int16_t)(a) - (int16_t)(b))
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338 | 664e0f19 | bellard | #define FMINUB(a, b) ((a) < (b)) ? (a) : (b)
|
339 | 664e0f19 | bellard | #define FMINSW(a, b) ((int16_t)(a) < (int16_t)(b)) ? (a) : (b)
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340 | 664e0f19 | bellard | #define FMAXUB(a, b) ((a) > (b)) ? (a) : (b)
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341 | 664e0f19 | bellard | #define FMAXSW(a, b) ((int16_t)(a) > (int16_t)(b)) ? (a) : (b)
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342 | 664e0f19 | bellard | |
343 | 664e0f19 | bellard | #define FAND(a, b) (a) & (b)
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344 | 664e0f19 | bellard | #define FANDN(a, b) ((~(a)) & (b))
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345 | 664e0f19 | bellard | #define FOR(a, b) (a) | (b)
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346 | 664e0f19 | bellard | #define FXOR(a, b) (a) ^ (b)
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347 | 664e0f19 | bellard | |
348 | 664e0f19 | bellard | #define FCMPGTB(a, b) (int8_t)(a) > (int8_t)(b) ? -1 : 0 |
349 | 664e0f19 | bellard | #define FCMPGTW(a, b) (int16_t)(a) > (int16_t)(b) ? -1 : 0 |
350 | 664e0f19 | bellard | #define FCMPGTL(a, b) (int32_t)(a) > (int32_t)(b) ? -1 : 0 |
351 | 664e0f19 | bellard | #define FCMPEQ(a, b) (a) == (b) ? -1 : 0 |
352 | 664e0f19 | bellard | |
353 | 664e0f19 | bellard | #define FMULLW(a, b) (a) * (b)
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354 | a35f3ec7 | aurel32 | #define FMULHRW(a, b) ((int16_t)(a) * (int16_t)(b) + 0x8000) >> 16 |
355 | 664e0f19 | bellard | #define FMULHUW(a, b) (a) * (b) >> 16 |
356 | 664e0f19 | bellard | #define FMULHW(a, b) (int16_t)(a) * (int16_t)(b) >> 16 |
357 | 664e0f19 | bellard | |
358 | 664e0f19 | bellard | #define FAVG(a, b) ((a) + (b) + 1) >> 1 |
359 | 664e0f19 | bellard | #endif
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360 | 664e0f19 | bellard | |
361 | 5af45186 | bellard | SSE_HELPER_B(helper_paddb, FADD) |
362 | 5af45186 | bellard | SSE_HELPER_W(helper_paddw, FADD) |
363 | 5af45186 | bellard | SSE_HELPER_L(helper_paddl, FADD) |
364 | 5af45186 | bellard | SSE_HELPER_Q(helper_paddq, FADD) |
365 | 664e0f19 | bellard | |
366 | 5af45186 | bellard | SSE_HELPER_B(helper_psubb, FSUB) |
367 | 5af45186 | bellard | SSE_HELPER_W(helper_psubw, FSUB) |
368 | 5af45186 | bellard | SSE_HELPER_L(helper_psubl, FSUB) |
369 | 5af45186 | bellard | SSE_HELPER_Q(helper_psubq, FSUB) |
370 | 664e0f19 | bellard | |
371 | 5af45186 | bellard | SSE_HELPER_B(helper_paddusb, FADDUB) |
372 | 5af45186 | bellard | SSE_HELPER_B(helper_paddsb, FADDSB) |
373 | 5af45186 | bellard | SSE_HELPER_B(helper_psubusb, FSUBUB) |
374 | 5af45186 | bellard | SSE_HELPER_B(helper_psubsb, FSUBSB) |
375 | 664e0f19 | bellard | |
376 | 5af45186 | bellard | SSE_HELPER_W(helper_paddusw, FADDUW) |
377 | 5af45186 | bellard | SSE_HELPER_W(helper_paddsw, FADDSW) |
378 | 5af45186 | bellard | SSE_HELPER_W(helper_psubusw, FSUBUW) |
379 | 5af45186 | bellard | SSE_HELPER_W(helper_psubsw, FSUBSW) |
380 | 664e0f19 | bellard | |
381 | 5af45186 | bellard | SSE_HELPER_B(helper_pminub, FMINUB) |
382 | 5af45186 | bellard | SSE_HELPER_B(helper_pmaxub, FMAXUB) |
383 | 664e0f19 | bellard | |
384 | 5af45186 | bellard | SSE_HELPER_W(helper_pminsw, FMINSW) |
385 | 5af45186 | bellard | SSE_HELPER_W(helper_pmaxsw, FMAXSW) |
386 | 664e0f19 | bellard | |
387 | 5af45186 | bellard | SSE_HELPER_Q(helper_pand, FAND) |
388 | 5af45186 | bellard | SSE_HELPER_Q(helper_pandn, FANDN) |
389 | 5af45186 | bellard | SSE_HELPER_Q(helper_por, FOR) |
390 | 5af45186 | bellard | SSE_HELPER_Q(helper_pxor, FXOR) |
391 | 664e0f19 | bellard | |
392 | 5af45186 | bellard | SSE_HELPER_B(helper_pcmpgtb, FCMPGTB) |
393 | 5af45186 | bellard | SSE_HELPER_W(helper_pcmpgtw, FCMPGTW) |
394 | 5af45186 | bellard | SSE_HELPER_L(helper_pcmpgtl, FCMPGTL) |
395 | 664e0f19 | bellard | |
396 | 5af45186 | bellard | SSE_HELPER_B(helper_pcmpeqb, FCMPEQ) |
397 | 5af45186 | bellard | SSE_HELPER_W(helper_pcmpeqw, FCMPEQ) |
398 | 5af45186 | bellard | SSE_HELPER_L(helper_pcmpeql, FCMPEQ) |
399 | 664e0f19 | bellard | |
400 | 5af45186 | bellard | SSE_HELPER_W(helper_pmullw, FMULLW) |
401 | a35f3ec7 | aurel32 | #if SHIFT == 0 |
402 | 5af45186 | bellard | SSE_HELPER_W(helper_pmulhrw, FMULHRW) |
403 | a35f3ec7 | aurel32 | #endif
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404 | 5af45186 | bellard | SSE_HELPER_W(helper_pmulhuw, FMULHUW) |
405 | 5af45186 | bellard | SSE_HELPER_W(helper_pmulhw, FMULHW) |
406 | 664e0f19 | bellard | |
407 | 5af45186 | bellard | SSE_HELPER_B(helper_pavgb, FAVG) |
408 | 5af45186 | bellard | SSE_HELPER_W(helper_pavgw, FAVG) |
409 | 664e0f19 | bellard | |
410 | 5af45186 | bellard | void glue(helper_pmuludq, SUFFIX) (Reg *d, Reg *s)
|
411 | 664e0f19 | bellard | { |
412 | 664e0f19 | bellard | d->Q(0) = (uint64_t)s->L(0) * (uint64_t)d->L(0); |
413 | 664e0f19 | bellard | #if SHIFT == 1 |
414 | 664e0f19 | bellard | d->Q(1) = (uint64_t)s->L(2) * (uint64_t)d->L(2); |
415 | 664e0f19 | bellard | #endif
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416 | 664e0f19 | bellard | } |
417 | 664e0f19 | bellard | |
418 | 5af45186 | bellard | void glue(helper_pmaddwd, SUFFIX) (Reg *d, Reg *s)
|
419 | 664e0f19 | bellard | { |
420 | 664e0f19 | bellard | int i;
|
421 | 664e0f19 | bellard | |
422 | 664e0f19 | bellard | for(i = 0; i < (2 << SHIFT); i++) { |
423 | 664e0f19 | bellard | d->L(i) = (int16_t)s->W(2*i) * (int16_t)d->W(2*i) + |
424 | 664e0f19 | bellard | (int16_t)s->W(2*i+1) * (int16_t)d->W(2*i+1); |
425 | 664e0f19 | bellard | } |
426 | 664e0f19 | bellard | } |
427 | 664e0f19 | bellard | |
428 | 664e0f19 | bellard | #if SHIFT == 0 |
429 | 664e0f19 | bellard | static inline int abs1(int a) |
430 | 664e0f19 | bellard | { |
431 | 664e0f19 | bellard | if (a < 0) |
432 | 664e0f19 | bellard | return -a;
|
433 | 664e0f19 | bellard | else
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434 | 664e0f19 | bellard | return a;
|
435 | 664e0f19 | bellard | } |
436 | 664e0f19 | bellard | #endif
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437 | 5af45186 | bellard | void glue(helper_psadbw, SUFFIX) (Reg *d, Reg *s)
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438 | 664e0f19 | bellard | { |
439 | 664e0f19 | bellard | unsigned int val; |
440 | 664e0f19 | bellard | |
441 | 664e0f19 | bellard | val = 0;
|
442 | 664e0f19 | bellard | val += abs1(d->B(0) - s->B(0)); |
443 | 664e0f19 | bellard | val += abs1(d->B(1) - s->B(1)); |
444 | 664e0f19 | bellard | val += abs1(d->B(2) - s->B(2)); |
445 | 664e0f19 | bellard | val += abs1(d->B(3) - s->B(3)); |
446 | 664e0f19 | bellard | val += abs1(d->B(4) - s->B(4)); |
447 | 664e0f19 | bellard | val += abs1(d->B(5) - s->B(5)); |
448 | 664e0f19 | bellard | val += abs1(d->B(6) - s->B(6)); |
449 | 664e0f19 | bellard | val += abs1(d->B(7) - s->B(7)); |
450 | 664e0f19 | bellard | d->Q(0) = val;
|
451 | 664e0f19 | bellard | #if SHIFT == 1 |
452 | 664e0f19 | bellard | val = 0;
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453 | 664e0f19 | bellard | val += abs1(d->B(8) - s->B(8)); |
454 | 664e0f19 | bellard | val += abs1(d->B(9) - s->B(9)); |
455 | 664e0f19 | bellard | val += abs1(d->B(10) - s->B(10)); |
456 | 664e0f19 | bellard | val += abs1(d->B(11) - s->B(11)); |
457 | 664e0f19 | bellard | val += abs1(d->B(12) - s->B(12)); |
458 | 664e0f19 | bellard | val += abs1(d->B(13) - s->B(13)); |
459 | 664e0f19 | bellard | val += abs1(d->B(14) - s->B(14)); |
460 | 664e0f19 | bellard | val += abs1(d->B(15) - s->B(15)); |
461 | 664e0f19 | bellard | d->Q(1) = val;
|
462 | 664e0f19 | bellard | #endif
|
463 | 664e0f19 | bellard | } |
464 | 664e0f19 | bellard | |
465 | b8b6a50b | bellard | void glue(helper_maskmov, SUFFIX) (Reg *d, Reg *s, target_ulong a0)
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466 | 664e0f19 | bellard | { |
467 | 664e0f19 | bellard | int i;
|
468 | 664e0f19 | bellard | for(i = 0; i < (8 << SHIFT); i++) { |
469 | 664e0f19 | bellard | if (s->B(i) & 0x80) |
470 | b8b6a50b | bellard | stb(a0 + i, d->B(i)); |
471 | 664e0f19 | bellard | } |
472 | 664e0f19 | bellard | } |
473 | 664e0f19 | bellard | |
474 | 5af45186 | bellard | void glue(helper_movl_mm_T0, SUFFIX) (Reg *d, uint32_t val)
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475 | 664e0f19 | bellard | { |
476 | 5af45186 | bellard | d->L(0) = val;
|
477 | 664e0f19 | bellard | d->L(1) = 0; |
478 | 664e0f19 | bellard | #if SHIFT == 1 |
479 | 664e0f19 | bellard | d->Q(1) = 0; |
480 | 664e0f19 | bellard | #endif
|
481 | 664e0f19 | bellard | } |
482 | 664e0f19 | bellard | |
483 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
484 | 5af45186 | bellard | void glue(helper_movq_mm_T0, SUFFIX) (Reg *d, uint64_t val)
|
485 | dabd98dd | bellard | { |
486 | 5af45186 | bellard | d->Q(0) = val;
|
487 | dabd98dd | bellard | #if SHIFT == 1 |
488 | dabd98dd | bellard | d->Q(1) = 0; |
489 | dabd98dd | bellard | #endif
|
490 | dabd98dd | bellard | } |
491 | dabd98dd | bellard | #endif
|
492 | dabd98dd | bellard | |
493 | 664e0f19 | bellard | #if SHIFT == 0 |
494 | 5af45186 | bellard | void glue(helper_pshufw, SUFFIX) (Reg *d, Reg *s, int order) |
495 | 664e0f19 | bellard | { |
496 | 5af45186 | bellard | Reg r; |
497 | 664e0f19 | bellard | r.W(0) = s->W(order & 3); |
498 | 664e0f19 | bellard | r.W(1) = s->W((order >> 2) & 3); |
499 | 664e0f19 | bellard | r.W(2) = s->W((order >> 4) & 3); |
500 | 664e0f19 | bellard | r.W(3) = s->W((order >> 6) & 3); |
501 | 664e0f19 | bellard | *d = r; |
502 | 664e0f19 | bellard | } |
503 | 664e0f19 | bellard | #else
|
504 | 5af45186 | bellard | void helper_shufps(Reg *d, Reg *s, int order) |
505 | d52cf7a6 | bellard | { |
506 | 5af45186 | bellard | Reg r; |
507 | d52cf7a6 | bellard | r.L(0) = d->L(order & 3); |
508 | d52cf7a6 | bellard | r.L(1) = d->L((order >> 2) & 3); |
509 | d52cf7a6 | bellard | r.L(2) = s->L((order >> 4) & 3); |
510 | d52cf7a6 | bellard | r.L(3) = s->L((order >> 6) & 3); |
511 | d52cf7a6 | bellard | *d = r; |
512 | d52cf7a6 | bellard | } |
513 | d52cf7a6 | bellard | |
514 | 5af45186 | bellard | void helper_shufpd(Reg *d, Reg *s, int order) |
515 | 664e0f19 | bellard | { |
516 | 5af45186 | bellard | Reg r; |
517 | d52cf7a6 | bellard | r.Q(0) = d->Q(order & 1); |
518 | 664e0f19 | bellard | r.Q(1) = s->Q((order >> 1) & 1); |
519 | 664e0f19 | bellard | *d = r; |
520 | 664e0f19 | bellard | } |
521 | 664e0f19 | bellard | |
522 | 5af45186 | bellard | void glue(helper_pshufd, SUFFIX) (Reg *d, Reg *s, int order) |
523 | 664e0f19 | bellard | { |
524 | 5af45186 | bellard | Reg r; |
525 | 664e0f19 | bellard | r.L(0) = s->L(order & 3); |
526 | 664e0f19 | bellard | r.L(1) = s->L((order >> 2) & 3); |
527 | 664e0f19 | bellard | r.L(2) = s->L((order >> 4) & 3); |
528 | 664e0f19 | bellard | r.L(3) = s->L((order >> 6) & 3); |
529 | 664e0f19 | bellard | *d = r; |
530 | 664e0f19 | bellard | } |
531 | 664e0f19 | bellard | |
532 | 5af45186 | bellard | void glue(helper_pshuflw, SUFFIX) (Reg *d, Reg *s, int order) |
533 | 664e0f19 | bellard | { |
534 | 5af45186 | bellard | Reg r; |
535 | 664e0f19 | bellard | r.W(0) = s->W(order & 3); |
536 | 664e0f19 | bellard | r.W(1) = s->W((order >> 2) & 3); |
537 | 664e0f19 | bellard | r.W(2) = s->W((order >> 4) & 3); |
538 | 664e0f19 | bellard | r.W(3) = s->W((order >> 6) & 3); |
539 | 664e0f19 | bellard | r.Q(1) = s->Q(1); |
540 | 664e0f19 | bellard | *d = r; |
541 | 664e0f19 | bellard | } |
542 | 664e0f19 | bellard | |
543 | 5af45186 | bellard | void glue(helper_pshufhw, SUFFIX) (Reg *d, Reg *s, int order) |
544 | 664e0f19 | bellard | { |
545 | 5af45186 | bellard | Reg r; |
546 | 664e0f19 | bellard | r.Q(0) = s->Q(0); |
547 | 664e0f19 | bellard | r.W(4) = s->W(4 + (order & 3)); |
548 | 664e0f19 | bellard | r.W(5) = s->W(4 + ((order >> 2) & 3)); |
549 | 664e0f19 | bellard | r.W(6) = s->W(4 + ((order >> 4) & 3)); |
550 | 664e0f19 | bellard | r.W(7) = s->W(4 + ((order >> 6) & 3)); |
551 | 664e0f19 | bellard | *d = r; |
552 | 664e0f19 | bellard | } |
553 | 664e0f19 | bellard | #endif
|
554 | 664e0f19 | bellard | |
555 | 664e0f19 | bellard | #if SHIFT == 1 |
556 | 664e0f19 | bellard | /* FPU ops */
|
557 | 664e0f19 | bellard | /* XXX: not accurate */
|
558 | 664e0f19 | bellard | |
559 | 5af45186 | bellard | #define SSE_HELPER_S(name, F)\
|
560 | 5af45186 | bellard | void helper_ ## name ## ps (Reg *d, Reg *s)\ |
561 | 664e0f19 | bellard | {\ |
562 | 7a0e1f41 | bellard | d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\ |
563 | 7a0e1f41 | bellard | d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1));\ |
564 | 7a0e1f41 | bellard | d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2));\ |
565 | 7a0e1f41 | bellard | d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3));\ |
566 | 664e0f19 | bellard | }\ |
567 | 664e0f19 | bellard | \ |
568 | 5af45186 | bellard | void helper_ ## name ## ss (Reg *d, Reg *s)\ |
569 | 664e0f19 | bellard | {\ |
570 | 7a0e1f41 | bellard | d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\ |
571 | 664e0f19 | bellard | }\ |
572 | 5af45186 | bellard | void helper_ ## name ## pd (Reg *d, Reg *s)\ |
573 | 664e0f19 | bellard | {\ |
574 | 7a0e1f41 | bellard | d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\ |
575 | 7a0e1f41 | bellard | d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1));\ |
576 | 664e0f19 | bellard | }\ |
577 | 664e0f19 | bellard | \ |
578 | 5af45186 | bellard | void helper_ ## name ## sd (Reg *d, Reg *s)\ |
579 | 664e0f19 | bellard | {\ |
580 | 7a0e1f41 | bellard | d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\ |
581 | 664e0f19 | bellard | } |
582 | 664e0f19 | bellard | |
583 | 7a0e1f41 | bellard | #define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status) |
584 | 7a0e1f41 | bellard | #define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status) |
585 | 7a0e1f41 | bellard | #define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status) |
586 | 7a0e1f41 | bellard | #define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status) |
587 | 7a0e1f41 | bellard | #define FPU_MIN(size, a, b) (a) < (b) ? (a) : (b)
|
588 | 7a0e1f41 | bellard | #define FPU_MAX(size, a, b) (a) > (b) ? (a) : (b)
|
589 | 7a0e1f41 | bellard | #define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status) |
590 | 664e0f19 | bellard | |
591 | 5af45186 | bellard | SSE_HELPER_S(add, FPU_ADD) |
592 | 5af45186 | bellard | SSE_HELPER_S(sub, FPU_SUB) |
593 | 5af45186 | bellard | SSE_HELPER_S(mul, FPU_MUL) |
594 | 5af45186 | bellard | SSE_HELPER_S(div, FPU_DIV) |
595 | 5af45186 | bellard | SSE_HELPER_S(min, FPU_MIN) |
596 | 5af45186 | bellard | SSE_HELPER_S(max, FPU_MAX) |
597 | 5af45186 | bellard | SSE_HELPER_S(sqrt, FPU_SQRT) |
598 | 664e0f19 | bellard | |
599 | 664e0f19 | bellard | |
600 | 664e0f19 | bellard | /* float to float conversions */
|
601 | 5af45186 | bellard | void helper_cvtps2pd(Reg *d, Reg *s)
|
602 | 664e0f19 | bellard | { |
603 | 8422b113 | bellard | float32 s0, s1; |
604 | 664e0f19 | bellard | s0 = s->XMM_S(0);
|
605 | 664e0f19 | bellard | s1 = s->XMM_S(1);
|
606 | 7a0e1f41 | bellard | d->XMM_D(0) = float32_to_float64(s0, &env->sse_status);
|
607 | 7a0e1f41 | bellard | d->XMM_D(1) = float32_to_float64(s1, &env->sse_status);
|
608 | 664e0f19 | bellard | } |
609 | 664e0f19 | bellard | |
610 | 5af45186 | bellard | void helper_cvtpd2ps(Reg *d, Reg *s)
|
611 | 664e0f19 | bellard | { |
612 | 7a0e1f41 | bellard | d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); |
613 | 7a0e1f41 | bellard | d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status); |
614 | 664e0f19 | bellard | d->Q(1) = 0; |
615 | 664e0f19 | bellard | } |
616 | 664e0f19 | bellard | |
617 | 5af45186 | bellard | void helper_cvtss2sd(Reg *d, Reg *s)
|
618 | 664e0f19 | bellard | { |
619 | 7a0e1f41 | bellard | d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status); |
620 | 664e0f19 | bellard | } |
621 | 664e0f19 | bellard | |
622 | 5af45186 | bellard | void helper_cvtsd2ss(Reg *d, Reg *s)
|
623 | 664e0f19 | bellard | { |
624 | 7a0e1f41 | bellard | d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); |
625 | 664e0f19 | bellard | } |
626 | 664e0f19 | bellard | |
627 | 664e0f19 | bellard | /* integer to float */
|
628 | 5af45186 | bellard | void helper_cvtdq2ps(Reg *d, Reg *s)
|
629 | 664e0f19 | bellard | { |
630 | 7a0e1f41 | bellard | d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status); |
631 | 7a0e1f41 | bellard | d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status); |
632 | 7a0e1f41 | bellard | d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status); |
633 | 7a0e1f41 | bellard | d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status); |
634 | 664e0f19 | bellard | } |
635 | 664e0f19 | bellard | |
636 | 5af45186 | bellard | void helper_cvtdq2pd(Reg *d, Reg *s)
|
637 | 664e0f19 | bellard | { |
638 | 664e0f19 | bellard | int32_t l0, l1; |
639 | 664e0f19 | bellard | l0 = (int32_t)s->XMM_L(0);
|
640 | 664e0f19 | bellard | l1 = (int32_t)s->XMM_L(1);
|
641 | 7a0e1f41 | bellard | d->XMM_D(0) = int32_to_float64(l0, &env->sse_status);
|
642 | 7a0e1f41 | bellard | d->XMM_D(1) = int32_to_float64(l1, &env->sse_status);
|
643 | 664e0f19 | bellard | } |
644 | 664e0f19 | bellard | |
645 | 5af45186 | bellard | void helper_cvtpi2ps(XMMReg *d, MMXReg *s)
|
646 | 664e0f19 | bellard | { |
647 | 7a0e1f41 | bellard | d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status); |
648 | 7a0e1f41 | bellard | d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status); |
649 | 664e0f19 | bellard | } |
650 | 664e0f19 | bellard | |
651 | 5af45186 | bellard | void helper_cvtpi2pd(XMMReg *d, MMXReg *s)
|
652 | 664e0f19 | bellard | { |
653 | 7a0e1f41 | bellard | d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status); |
654 | 7a0e1f41 | bellard | d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status); |
655 | 664e0f19 | bellard | } |
656 | 664e0f19 | bellard | |
657 | 5af45186 | bellard | void helper_cvtsi2ss(XMMReg *d, uint32_t val)
|
658 | 664e0f19 | bellard | { |
659 | 5af45186 | bellard | d->XMM_S(0) = int32_to_float32(val, &env->sse_status);
|
660 | 664e0f19 | bellard | } |
661 | 664e0f19 | bellard | |
662 | 5af45186 | bellard | void helper_cvtsi2sd(XMMReg *d, uint32_t val)
|
663 | 664e0f19 | bellard | { |
664 | 5af45186 | bellard | d->XMM_D(0) = int32_to_float64(val, &env->sse_status);
|
665 | 664e0f19 | bellard | } |
666 | 664e0f19 | bellard | |
667 | 664e0f19 | bellard | #ifdef TARGET_X86_64
|
668 | 5af45186 | bellard | void helper_cvtsq2ss(XMMReg *d, uint64_t val)
|
669 | 664e0f19 | bellard | { |
670 | 5af45186 | bellard | d->XMM_S(0) = int64_to_float32(val, &env->sse_status);
|
671 | 664e0f19 | bellard | } |
672 | 664e0f19 | bellard | |
673 | 5af45186 | bellard | void helper_cvtsq2sd(XMMReg *d, uint64_t val)
|
674 | 664e0f19 | bellard | { |
675 | 5af45186 | bellard | d->XMM_D(0) = int64_to_float64(val, &env->sse_status);
|
676 | 664e0f19 | bellard | } |
677 | 664e0f19 | bellard | #endif
|
678 | 664e0f19 | bellard | |
679 | 664e0f19 | bellard | /* float to integer */
|
680 | 5af45186 | bellard | void helper_cvtps2dq(XMMReg *d, XMMReg *s)
|
681 | 664e0f19 | bellard | { |
682 | 7a0e1f41 | bellard | d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); |
683 | 7a0e1f41 | bellard | d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); |
684 | 7a0e1f41 | bellard | d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status); |
685 | 7a0e1f41 | bellard | d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status); |
686 | 664e0f19 | bellard | } |
687 | 664e0f19 | bellard | |
688 | 5af45186 | bellard | void helper_cvtpd2dq(XMMReg *d, XMMReg *s)
|
689 | 664e0f19 | bellard | { |
690 | 7a0e1f41 | bellard | d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); |
691 | 7a0e1f41 | bellard | d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); |
692 | 664e0f19 | bellard | d->XMM_Q(1) = 0; |
693 | 664e0f19 | bellard | } |
694 | 664e0f19 | bellard | |
695 | 5af45186 | bellard | void helper_cvtps2pi(MMXReg *d, XMMReg *s)
|
696 | 664e0f19 | bellard | { |
697 | 7a0e1f41 | bellard | d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); |
698 | 7a0e1f41 | bellard | d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); |
699 | 664e0f19 | bellard | } |
700 | 664e0f19 | bellard | |
701 | 5af45186 | bellard | void helper_cvtpd2pi(MMXReg *d, XMMReg *s)
|
702 | 664e0f19 | bellard | { |
703 | 7a0e1f41 | bellard | d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); |
704 | 7a0e1f41 | bellard | d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); |
705 | 664e0f19 | bellard | } |
706 | 664e0f19 | bellard | |
707 | 5af45186 | bellard | int32_t helper_cvtss2si(XMMReg *s) |
708 | 664e0f19 | bellard | { |
709 | 5af45186 | bellard | return float32_to_int32(s->XMM_S(0), &env->sse_status); |
710 | 664e0f19 | bellard | } |
711 | 664e0f19 | bellard | |
712 | 5af45186 | bellard | int32_t helper_cvtsd2si(XMMReg *s) |
713 | 664e0f19 | bellard | { |
714 | 5af45186 | bellard | return float64_to_int32(s->XMM_D(0), &env->sse_status); |
715 | 664e0f19 | bellard | } |
716 | 664e0f19 | bellard | |
717 | 664e0f19 | bellard | #ifdef TARGET_X86_64
|
718 | 5af45186 | bellard | int64_t helper_cvtss2sq(XMMReg *s) |
719 | 664e0f19 | bellard | { |
720 | 5af45186 | bellard | return float32_to_int64(s->XMM_S(0), &env->sse_status); |
721 | 664e0f19 | bellard | } |
722 | 664e0f19 | bellard | |
723 | 5af45186 | bellard | int64_t helper_cvtsd2sq(XMMReg *s) |
724 | 664e0f19 | bellard | { |
725 | 5af45186 | bellard | return float64_to_int64(s->XMM_D(0), &env->sse_status); |
726 | 664e0f19 | bellard | } |
727 | 664e0f19 | bellard | #endif
|
728 | 664e0f19 | bellard | |
729 | 664e0f19 | bellard | /* float to integer truncated */
|
730 | 5af45186 | bellard | void helper_cvttps2dq(XMMReg *d, XMMReg *s)
|
731 | 664e0f19 | bellard | { |
732 | 7a0e1f41 | bellard | d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
733 | 7a0e1f41 | bellard | d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); |
734 | 7a0e1f41 | bellard | d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status); |
735 | 7a0e1f41 | bellard | d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status); |
736 | 664e0f19 | bellard | } |
737 | 664e0f19 | bellard | |
738 | 5af45186 | bellard | void helper_cvttpd2dq(XMMReg *d, XMMReg *s)
|
739 | 664e0f19 | bellard | { |
740 | 7a0e1f41 | bellard | d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
741 | 7a0e1f41 | bellard | d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); |
742 | 664e0f19 | bellard | d->XMM_Q(1) = 0; |
743 | 664e0f19 | bellard | } |
744 | 664e0f19 | bellard | |
745 | 5af45186 | bellard | void helper_cvttps2pi(MMXReg *d, XMMReg *s)
|
746 | 664e0f19 | bellard | { |
747 | 7a0e1f41 | bellard | d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
748 | 7a0e1f41 | bellard | d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); |
749 | 664e0f19 | bellard | } |
750 | 664e0f19 | bellard | |
751 | 5af45186 | bellard | void helper_cvttpd2pi(MMXReg *d, XMMReg *s)
|
752 | 664e0f19 | bellard | { |
753 | 7a0e1f41 | bellard | d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
754 | 7a0e1f41 | bellard | d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); |
755 | 664e0f19 | bellard | } |
756 | 664e0f19 | bellard | |
757 | 5af45186 | bellard | int32_t helper_cvttss2si(XMMReg *s) |
758 | 664e0f19 | bellard | { |
759 | 5af45186 | bellard | return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
760 | 664e0f19 | bellard | } |
761 | 664e0f19 | bellard | |
762 | 5af45186 | bellard | int32_t helper_cvttsd2si(XMMReg *s) |
763 | 664e0f19 | bellard | { |
764 | 5af45186 | bellard | return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
765 | 664e0f19 | bellard | } |
766 | 664e0f19 | bellard | |
767 | 664e0f19 | bellard | #ifdef TARGET_X86_64
|
768 | 5af45186 | bellard | int64_t helper_cvttss2sq(XMMReg *s) |
769 | 664e0f19 | bellard | { |
770 | 5af45186 | bellard | return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status); |
771 | 664e0f19 | bellard | } |
772 | 664e0f19 | bellard | |
773 | 5af45186 | bellard | int64_t helper_cvttsd2sq(XMMReg *s) |
774 | 664e0f19 | bellard | { |
775 | 5af45186 | bellard | return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status); |
776 | 664e0f19 | bellard | } |
777 | 664e0f19 | bellard | #endif
|
778 | 664e0f19 | bellard | |
779 | 5af45186 | bellard | void helper_rsqrtps(XMMReg *d, XMMReg *s)
|
780 | 664e0f19 | bellard | { |
781 | 664e0f19 | bellard | d->XMM_S(0) = approx_rsqrt(s->XMM_S(0)); |
782 | 664e0f19 | bellard | d->XMM_S(1) = approx_rsqrt(s->XMM_S(1)); |
783 | 664e0f19 | bellard | d->XMM_S(2) = approx_rsqrt(s->XMM_S(2)); |
784 | 664e0f19 | bellard | d->XMM_S(3) = approx_rsqrt(s->XMM_S(3)); |
785 | 664e0f19 | bellard | } |
786 | 664e0f19 | bellard | |
787 | 5af45186 | bellard | void helper_rsqrtss(XMMReg *d, XMMReg *s)
|
788 | 664e0f19 | bellard | { |
789 | 664e0f19 | bellard | d->XMM_S(0) = approx_rsqrt(s->XMM_S(0)); |
790 | 664e0f19 | bellard | } |
791 | 664e0f19 | bellard | |
792 | 5af45186 | bellard | void helper_rcpps(XMMReg *d, XMMReg *s)
|
793 | 664e0f19 | bellard | { |
794 | 664e0f19 | bellard | d->XMM_S(0) = approx_rcp(s->XMM_S(0)); |
795 | 664e0f19 | bellard | d->XMM_S(1) = approx_rcp(s->XMM_S(1)); |
796 | 664e0f19 | bellard | d->XMM_S(2) = approx_rcp(s->XMM_S(2)); |
797 | 664e0f19 | bellard | d->XMM_S(3) = approx_rcp(s->XMM_S(3)); |
798 | 664e0f19 | bellard | } |
799 | 664e0f19 | bellard | |
800 | 5af45186 | bellard | void helper_rcpss(XMMReg *d, XMMReg *s)
|
801 | 664e0f19 | bellard | { |
802 | 664e0f19 | bellard | d->XMM_S(0) = approx_rcp(s->XMM_S(0)); |
803 | 664e0f19 | bellard | } |
804 | 664e0f19 | bellard | |
805 | 5af45186 | bellard | void helper_haddps(XMMReg *d, XMMReg *s)
|
806 | 664e0f19 | bellard | { |
807 | 664e0f19 | bellard | XMMReg r; |
808 | 664e0f19 | bellard | r.XMM_S(0) = d->XMM_S(0) + d->XMM_S(1); |
809 | 664e0f19 | bellard | r.XMM_S(1) = d->XMM_S(2) + d->XMM_S(3); |
810 | 664e0f19 | bellard | r.XMM_S(2) = s->XMM_S(0) + s->XMM_S(1); |
811 | 664e0f19 | bellard | r.XMM_S(3) = s->XMM_S(2) + s->XMM_S(3); |
812 | 664e0f19 | bellard | *d = r; |
813 | 664e0f19 | bellard | } |
814 | 664e0f19 | bellard | |
815 | 5af45186 | bellard | void helper_haddpd(XMMReg *d, XMMReg *s)
|
816 | 664e0f19 | bellard | { |
817 | 664e0f19 | bellard | XMMReg r; |
818 | 664e0f19 | bellard | r.XMM_D(0) = d->XMM_D(0) + d->XMM_D(1); |
819 | 664e0f19 | bellard | r.XMM_D(1) = s->XMM_D(0) + s->XMM_D(1); |
820 | 664e0f19 | bellard | *d = r; |
821 | 664e0f19 | bellard | } |
822 | 664e0f19 | bellard | |
823 | 5af45186 | bellard | void helper_hsubps(XMMReg *d, XMMReg *s)
|
824 | 664e0f19 | bellard | { |
825 | 664e0f19 | bellard | XMMReg r; |
826 | 664e0f19 | bellard | r.XMM_S(0) = d->XMM_S(0) - d->XMM_S(1); |
827 | 664e0f19 | bellard | r.XMM_S(1) = d->XMM_S(2) - d->XMM_S(3); |
828 | 664e0f19 | bellard | r.XMM_S(2) = s->XMM_S(0) - s->XMM_S(1); |
829 | 664e0f19 | bellard | r.XMM_S(3) = s->XMM_S(2) - s->XMM_S(3); |
830 | 664e0f19 | bellard | *d = r; |
831 | 664e0f19 | bellard | } |
832 | 664e0f19 | bellard | |
833 | 5af45186 | bellard | void helper_hsubpd(XMMReg *d, XMMReg *s)
|
834 | 664e0f19 | bellard | { |
835 | 664e0f19 | bellard | XMMReg r; |
836 | 664e0f19 | bellard | r.XMM_D(0) = d->XMM_D(0) - d->XMM_D(1); |
837 | 664e0f19 | bellard | r.XMM_D(1) = s->XMM_D(0) - s->XMM_D(1); |
838 | 664e0f19 | bellard | *d = r; |
839 | 664e0f19 | bellard | } |
840 | 664e0f19 | bellard | |
841 | 5af45186 | bellard | void helper_addsubps(XMMReg *d, XMMReg *s)
|
842 | 664e0f19 | bellard | { |
843 | 664e0f19 | bellard | d->XMM_S(0) = d->XMM_S(0) - s->XMM_S(0); |
844 | 664e0f19 | bellard | d->XMM_S(1) = d->XMM_S(1) + s->XMM_S(1); |
845 | 664e0f19 | bellard | d->XMM_S(2) = d->XMM_S(2) - s->XMM_S(2); |
846 | 664e0f19 | bellard | d->XMM_S(3) = d->XMM_S(3) + s->XMM_S(3); |
847 | 664e0f19 | bellard | } |
848 | 664e0f19 | bellard | |
849 | 5af45186 | bellard | void helper_addsubpd(XMMReg *d, XMMReg *s)
|
850 | 664e0f19 | bellard | { |
851 | 664e0f19 | bellard | d->XMM_D(0) = d->XMM_D(0) - s->XMM_D(0); |
852 | 664e0f19 | bellard | d->XMM_D(1) = d->XMM_D(1) + s->XMM_D(1); |
853 | 664e0f19 | bellard | } |
854 | 664e0f19 | bellard | |
855 | 664e0f19 | bellard | /* XXX: unordered */
|
856 | 5af45186 | bellard | #define SSE_HELPER_CMP(name, F)\
|
857 | 5af45186 | bellard | void helper_ ## name ## ps (Reg *d, Reg *s)\ |
858 | 664e0f19 | bellard | {\ |
859 | 8422b113 | bellard | d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0));\ |
860 | 8422b113 | bellard | d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1));\ |
861 | 8422b113 | bellard | d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2));\ |
862 | 8422b113 | bellard | d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3));\ |
863 | 664e0f19 | bellard | }\ |
864 | 664e0f19 | bellard | \ |
865 | 5af45186 | bellard | void helper_ ## name ## ss (Reg *d, Reg *s)\ |
866 | 664e0f19 | bellard | {\ |
867 | 8422b113 | bellard | d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0));\ |
868 | 664e0f19 | bellard | }\ |
869 | 5af45186 | bellard | void helper_ ## name ## pd (Reg *d, Reg *s)\ |
870 | 664e0f19 | bellard | {\ |
871 | 8422b113 | bellard | d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0));\ |
872 | 8422b113 | bellard | d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1));\ |
873 | 664e0f19 | bellard | }\ |
874 | 664e0f19 | bellard | \ |
875 | 5af45186 | bellard | void helper_ ## name ## sd (Reg *d, Reg *s)\ |
876 | 664e0f19 | bellard | {\ |
877 | 8422b113 | bellard | d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0));\ |
878 | 664e0f19 | bellard | } |
879 | 664e0f19 | bellard | |
880 | 8422b113 | bellard | #define FPU_CMPEQ(size, a, b) float ## size ## _eq(a, b, &env->sse_status) ? -1 : 0 |
881 | 8422b113 | bellard | #define FPU_CMPLT(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? -1 : 0 |
882 | 8422b113 | bellard | #define FPU_CMPLE(size, a, b) float ## size ## _le(a, b, &env->sse_status) ? -1 : 0 |
883 | 8422b113 | bellard | #define FPU_CMPUNORD(size, a, b) float ## size ## _unordered(a, b, &env->sse_status) ? - 1 : 0 |
884 | 8422b113 | bellard | #define FPU_CMPNEQ(size, a, b) float ## size ## _eq(a, b, &env->sse_status) ? 0 : -1 |
885 | 8422b113 | bellard | #define FPU_CMPNLT(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? 0 : -1 |
886 | 8422b113 | bellard | #define FPU_CMPNLE(size, a, b) float ## size ## _le(a, b, &env->sse_status) ? 0 : -1 |
887 | 8422b113 | bellard | #define FPU_CMPORD(size, a, b) float ## size ## _unordered(a, b, &env->sse_status) ? 0 : -1 |
888 | 664e0f19 | bellard | |
889 | 5af45186 | bellard | SSE_HELPER_CMP(cmpeq, FPU_CMPEQ) |
890 | 5af45186 | bellard | SSE_HELPER_CMP(cmplt, FPU_CMPLT) |
891 | 5af45186 | bellard | SSE_HELPER_CMP(cmple, FPU_CMPLE) |
892 | 5af45186 | bellard | SSE_HELPER_CMP(cmpunord, FPU_CMPUNORD) |
893 | 5af45186 | bellard | SSE_HELPER_CMP(cmpneq, FPU_CMPNEQ) |
894 | 5af45186 | bellard | SSE_HELPER_CMP(cmpnlt, FPU_CMPNLT) |
895 | 5af45186 | bellard | SSE_HELPER_CMP(cmpnle, FPU_CMPNLE) |
896 | 5af45186 | bellard | SSE_HELPER_CMP(cmpord, FPU_CMPORD) |
897 | 664e0f19 | bellard | |
898 | 1e6eec8b | Blue Swirl | static const int comis_eflags[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C}; |
899 | 43fb823b | bellard | |
900 | 5af45186 | bellard | void helper_ucomiss(Reg *d, Reg *s)
|
901 | 664e0f19 | bellard | { |
902 | 43fb823b | bellard | int ret;
|
903 | 8422b113 | bellard | float32 s0, s1; |
904 | 664e0f19 | bellard | |
905 | 664e0f19 | bellard | s0 = d->XMM_S(0);
|
906 | 664e0f19 | bellard | s1 = s->XMM_S(0);
|
907 | 43fb823b | bellard | ret = float32_compare_quiet(s0, s1, &env->sse_status); |
908 | 43fb823b | bellard | CC_SRC = comis_eflags[ret + 1];
|
909 | 664e0f19 | bellard | } |
910 | 664e0f19 | bellard | |
911 | 5af45186 | bellard | void helper_comiss(Reg *d, Reg *s)
|
912 | 664e0f19 | bellard | { |
913 | 43fb823b | bellard | int ret;
|
914 | 8422b113 | bellard | float32 s0, s1; |
915 | 664e0f19 | bellard | |
916 | 664e0f19 | bellard | s0 = d->XMM_S(0);
|
917 | 664e0f19 | bellard | s1 = s->XMM_S(0);
|
918 | 43fb823b | bellard | ret = float32_compare(s0, s1, &env->sse_status); |
919 | 43fb823b | bellard | CC_SRC = comis_eflags[ret + 1];
|
920 | 664e0f19 | bellard | } |
921 | 664e0f19 | bellard | |
922 | 5af45186 | bellard | void helper_ucomisd(Reg *d, Reg *s)
|
923 | 664e0f19 | bellard | { |
924 | 43fb823b | bellard | int ret;
|
925 | 8422b113 | bellard | float64 d0, d1; |
926 | 664e0f19 | bellard | |
927 | 664e0f19 | bellard | d0 = d->XMM_D(0);
|
928 | 664e0f19 | bellard | d1 = s->XMM_D(0);
|
929 | 43fb823b | bellard | ret = float64_compare_quiet(d0, d1, &env->sse_status); |
930 | 43fb823b | bellard | CC_SRC = comis_eflags[ret + 1];
|
931 | 664e0f19 | bellard | } |
932 | 664e0f19 | bellard | |
933 | 5af45186 | bellard | void helper_comisd(Reg *d, Reg *s)
|
934 | 664e0f19 | bellard | { |
935 | 43fb823b | bellard | int ret;
|
936 | 8422b113 | bellard | float64 d0, d1; |
937 | 664e0f19 | bellard | |
938 | 664e0f19 | bellard | d0 = d->XMM_D(0);
|
939 | 664e0f19 | bellard | d1 = s->XMM_D(0);
|
940 | 43fb823b | bellard | ret = float64_compare(d0, d1, &env->sse_status); |
941 | 43fb823b | bellard | CC_SRC = comis_eflags[ret + 1];
|
942 | 664e0f19 | bellard | } |
943 | 664e0f19 | bellard | |
944 | 5af45186 | bellard | uint32_t helper_movmskps(Reg *s) |
945 | 664e0f19 | bellard | { |
946 | 664e0f19 | bellard | int b0, b1, b2, b3;
|
947 | 664e0f19 | bellard | b0 = s->XMM_L(0) >> 31; |
948 | 664e0f19 | bellard | b1 = s->XMM_L(1) >> 31; |
949 | 664e0f19 | bellard | b2 = s->XMM_L(2) >> 31; |
950 | 664e0f19 | bellard | b3 = s->XMM_L(3) >> 31; |
951 | 5af45186 | bellard | return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3); |
952 | 664e0f19 | bellard | } |
953 | 664e0f19 | bellard | |
954 | 5af45186 | bellard | uint32_t helper_movmskpd(Reg *s) |
955 | 664e0f19 | bellard | { |
956 | 664e0f19 | bellard | int b0, b1;
|
957 | 664e0f19 | bellard | b0 = s->XMM_L(1) >> 31; |
958 | 664e0f19 | bellard | b1 = s->XMM_L(3) >> 31; |
959 | 5af45186 | bellard | return b0 | (b1 << 1); |
960 | 664e0f19 | bellard | } |
961 | 664e0f19 | bellard | |
962 | 664e0f19 | bellard | #endif
|
963 | 664e0f19 | bellard | |
964 | 5af45186 | bellard | uint32_t glue(helper_pmovmskb, SUFFIX)(Reg *s) |
965 | 5af45186 | bellard | { |
966 | 5af45186 | bellard | uint32_t val; |
967 | 5af45186 | bellard | val = 0;
|
968 | 30913bae | aurel32 | val |= (s->B(0) >> 7); |
969 | 30913bae | aurel32 | val |= (s->B(1) >> 6) & 0x02; |
970 | 30913bae | aurel32 | val |= (s->B(2) >> 5) & 0x04; |
971 | 30913bae | aurel32 | val |= (s->B(3) >> 4) & 0x08; |
972 | 30913bae | aurel32 | val |= (s->B(4) >> 3) & 0x10; |
973 | 30913bae | aurel32 | val |= (s->B(5) >> 2) & 0x20; |
974 | 30913bae | aurel32 | val |= (s->B(6) >> 1) & 0x40; |
975 | 30913bae | aurel32 | val |= (s->B(7)) & 0x80; |
976 | 664e0f19 | bellard | #if SHIFT == 1 |
977 | 30913bae | aurel32 | val |= (s->B(8) << 1) & 0x0100; |
978 | 30913bae | aurel32 | val |= (s->B(9) << 2) & 0x0200; |
979 | 30913bae | aurel32 | val |= (s->B(10) << 3) & 0x0400; |
980 | 30913bae | aurel32 | val |= (s->B(11) << 4) & 0x0800; |
981 | 30913bae | aurel32 | val |= (s->B(12) << 5) & 0x1000; |
982 | 30913bae | aurel32 | val |= (s->B(13) << 6) & 0x2000; |
983 | 30913bae | aurel32 | val |= (s->B(14) << 7) & 0x4000; |
984 | 30913bae | aurel32 | val |= (s->B(15) << 8) & 0x8000; |
985 | 664e0f19 | bellard | #endif
|
986 | 5af45186 | bellard | return val;
|
987 | 664e0f19 | bellard | } |
988 | 664e0f19 | bellard | |
989 | 5af45186 | bellard | void glue(helper_packsswb, SUFFIX) (Reg *d, Reg *s)
|
990 | 664e0f19 | bellard | { |
991 | 5af45186 | bellard | Reg r; |
992 | 664e0f19 | bellard | |
993 | 664e0f19 | bellard | r.B(0) = satsb((int16_t)d->W(0)); |
994 | 664e0f19 | bellard | r.B(1) = satsb((int16_t)d->W(1)); |
995 | 664e0f19 | bellard | r.B(2) = satsb((int16_t)d->W(2)); |
996 | 664e0f19 | bellard | r.B(3) = satsb((int16_t)d->W(3)); |
997 | 664e0f19 | bellard | #if SHIFT == 1 |
998 | 664e0f19 | bellard | r.B(4) = satsb((int16_t)d->W(4)); |
999 | 664e0f19 | bellard | r.B(5) = satsb((int16_t)d->W(5)); |
1000 | 664e0f19 | bellard | r.B(6) = satsb((int16_t)d->W(6)); |
1001 | 664e0f19 | bellard | r.B(7) = satsb((int16_t)d->W(7)); |
1002 | 664e0f19 | bellard | #endif
|
1003 | 664e0f19 | bellard | r.B((4 << SHIFT) + 0) = satsb((int16_t)s->W(0)); |
1004 | 664e0f19 | bellard | r.B((4 << SHIFT) + 1) = satsb((int16_t)s->W(1)); |
1005 | 664e0f19 | bellard | r.B((4 << SHIFT) + 2) = satsb((int16_t)s->W(2)); |
1006 | 664e0f19 | bellard | r.B((4 << SHIFT) + 3) = satsb((int16_t)s->W(3)); |
1007 | 664e0f19 | bellard | #if SHIFT == 1 |
1008 | 664e0f19 | bellard | r.B(12) = satsb((int16_t)s->W(4)); |
1009 | 664e0f19 | bellard | r.B(13) = satsb((int16_t)s->W(5)); |
1010 | 664e0f19 | bellard | r.B(14) = satsb((int16_t)s->W(6)); |
1011 | 664e0f19 | bellard | r.B(15) = satsb((int16_t)s->W(7)); |
1012 | 664e0f19 | bellard | #endif
|
1013 | 664e0f19 | bellard | *d = r; |
1014 | 664e0f19 | bellard | } |
1015 | 664e0f19 | bellard | |
1016 | 5af45186 | bellard | void glue(helper_packuswb, SUFFIX) (Reg *d, Reg *s)
|
1017 | 664e0f19 | bellard | { |
1018 | 5af45186 | bellard | Reg r; |
1019 | 664e0f19 | bellard | |
1020 | 664e0f19 | bellard | r.B(0) = satub((int16_t)d->W(0)); |
1021 | 664e0f19 | bellard | r.B(1) = satub((int16_t)d->W(1)); |
1022 | 664e0f19 | bellard | r.B(2) = satub((int16_t)d->W(2)); |
1023 | 664e0f19 | bellard | r.B(3) = satub((int16_t)d->W(3)); |
1024 | 664e0f19 | bellard | #if SHIFT == 1 |
1025 | 664e0f19 | bellard | r.B(4) = satub((int16_t)d->W(4)); |
1026 | 664e0f19 | bellard | r.B(5) = satub((int16_t)d->W(5)); |
1027 | 664e0f19 | bellard | r.B(6) = satub((int16_t)d->W(6)); |
1028 | 664e0f19 | bellard | r.B(7) = satub((int16_t)d->W(7)); |
1029 | 664e0f19 | bellard | #endif
|
1030 | 664e0f19 | bellard | r.B((4 << SHIFT) + 0) = satub((int16_t)s->W(0)); |
1031 | 664e0f19 | bellard | r.B((4 << SHIFT) + 1) = satub((int16_t)s->W(1)); |
1032 | 664e0f19 | bellard | r.B((4 << SHIFT) + 2) = satub((int16_t)s->W(2)); |
1033 | 664e0f19 | bellard | r.B((4 << SHIFT) + 3) = satub((int16_t)s->W(3)); |
1034 | 664e0f19 | bellard | #if SHIFT == 1 |
1035 | 664e0f19 | bellard | r.B(12) = satub((int16_t)s->W(4)); |
1036 | 664e0f19 | bellard | r.B(13) = satub((int16_t)s->W(5)); |
1037 | 664e0f19 | bellard | r.B(14) = satub((int16_t)s->W(6)); |
1038 | 664e0f19 | bellard | r.B(15) = satub((int16_t)s->W(7)); |
1039 | 664e0f19 | bellard | #endif
|
1040 | 664e0f19 | bellard | *d = r; |
1041 | 664e0f19 | bellard | } |
1042 | 664e0f19 | bellard | |
1043 | 5af45186 | bellard | void glue(helper_packssdw, SUFFIX) (Reg *d, Reg *s)
|
1044 | 664e0f19 | bellard | { |
1045 | 5af45186 | bellard | Reg r; |
1046 | 664e0f19 | bellard | |
1047 | 664e0f19 | bellard | r.W(0) = satsw(d->L(0)); |
1048 | 664e0f19 | bellard | r.W(1) = satsw(d->L(1)); |
1049 | 664e0f19 | bellard | #if SHIFT == 1 |
1050 | 664e0f19 | bellard | r.W(2) = satsw(d->L(2)); |
1051 | 664e0f19 | bellard | r.W(3) = satsw(d->L(3)); |
1052 | 664e0f19 | bellard | #endif
|
1053 | 664e0f19 | bellard | r.W((2 << SHIFT) + 0) = satsw(s->L(0)); |
1054 | 664e0f19 | bellard | r.W((2 << SHIFT) + 1) = satsw(s->L(1)); |
1055 | 664e0f19 | bellard | #if SHIFT == 1 |
1056 | 664e0f19 | bellard | r.W(6) = satsw(s->L(2)); |
1057 | 664e0f19 | bellard | r.W(7) = satsw(s->L(3)); |
1058 | 664e0f19 | bellard | #endif
|
1059 | 664e0f19 | bellard | *d = r; |
1060 | 664e0f19 | bellard | } |
1061 | 664e0f19 | bellard | |
1062 | 664e0f19 | bellard | #define UNPCK_OP(base_name, base) \
|
1063 | 664e0f19 | bellard | \ |
1064 | 5af45186 | bellard | void glue(helper_punpck ## base_name ## bw, SUFFIX) (Reg *d, Reg *s) \ |
1065 | 664e0f19 | bellard | { \ |
1066 | 5af45186 | bellard | Reg r; \ |
1067 | 664e0f19 | bellard | \ |
1068 | 664e0f19 | bellard | r.B(0) = d->B((base << (SHIFT + 2)) + 0); \ |
1069 | 664e0f19 | bellard | r.B(1) = s->B((base << (SHIFT + 2)) + 0); \ |
1070 | 664e0f19 | bellard | r.B(2) = d->B((base << (SHIFT + 2)) + 1); \ |
1071 | 664e0f19 | bellard | r.B(3) = s->B((base << (SHIFT + 2)) + 1); \ |
1072 | 664e0f19 | bellard | r.B(4) = d->B((base << (SHIFT + 2)) + 2); \ |
1073 | 664e0f19 | bellard | r.B(5) = s->B((base << (SHIFT + 2)) + 2); \ |
1074 | 664e0f19 | bellard | r.B(6) = d->B((base << (SHIFT + 2)) + 3); \ |
1075 | 664e0f19 | bellard | r.B(7) = s->B((base << (SHIFT + 2)) + 3); \ |
1076 | 664e0f19 | bellard | XMM_ONLY( \ |
1077 | 664e0f19 | bellard | r.B(8) = d->B((base << (SHIFT + 2)) + 4); \ |
1078 | 664e0f19 | bellard | r.B(9) = s->B((base << (SHIFT + 2)) + 4); \ |
1079 | 664e0f19 | bellard | r.B(10) = d->B((base << (SHIFT + 2)) + 5); \ |
1080 | 664e0f19 | bellard | r.B(11) = s->B((base << (SHIFT + 2)) + 5); \ |
1081 | 664e0f19 | bellard | r.B(12) = d->B((base << (SHIFT + 2)) + 6); \ |
1082 | 664e0f19 | bellard | r.B(13) = s->B((base << (SHIFT + 2)) + 6); \ |
1083 | 664e0f19 | bellard | r.B(14) = d->B((base << (SHIFT + 2)) + 7); \ |
1084 | 664e0f19 | bellard | r.B(15) = s->B((base << (SHIFT + 2)) + 7); \ |
1085 | 664e0f19 | bellard | ) \ |
1086 | 664e0f19 | bellard | *d = r; \ |
1087 | 664e0f19 | bellard | } \ |
1088 | 664e0f19 | bellard | \ |
1089 | 5af45186 | bellard | void glue(helper_punpck ## base_name ## wd, SUFFIX) (Reg *d, Reg *s) \ |
1090 | 664e0f19 | bellard | { \ |
1091 | 5af45186 | bellard | Reg r; \ |
1092 | 664e0f19 | bellard | \ |
1093 | 664e0f19 | bellard | r.W(0) = d->W((base << (SHIFT + 1)) + 0); \ |
1094 | 664e0f19 | bellard | r.W(1) = s->W((base << (SHIFT + 1)) + 0); \ |
1095 | 664e0f19 | bellard | r.W(2) = d->W((base << (SHIFT + 1)) + 1); \ |
1096 | 664e0f19 | bellard | r.W(3) = s->W((base << (SHIFT + 1)) + 1); \ |
1097 | 664e0f19 | bellard | XMM_ONLY( \ |
1098 | 664e0f19 | bellard | r.W(4) = d->W((base << (SHIFT + 1)) + 2); \ |
1099 | 664e0f19 | bellard | r.W(5) = s->W((base << (SHIFT + 1)) + 2); \ |
1100 | 664e0f19 | bellard | r.W(6) = d->W((base << (SHIFT + 1)) + 3); \ |
1101 | 664e0f19 | bellard | r.W(7) = s->W((base << (SHIFT + 1)) + 3); \ |
1102 | 664e0f19 | bellard | ) \ |
1103 | 664e0f19 | bellard | *d = r; \ |
1104 | 664e0f19 | bellard | } \ |
1105 | 664e0f19 | bellard | \ |
1106 | 5af45186 | bellard | void glue(helper_punpck ## base_name ## dq, SUFFIX) (Reg *d, Reg *s) \ |
1107 | 664e0f19 | bellard | { \ |
1108 | 5af45186 | bellard | Reg r; \ |
1109 | 664e0f19 | bellard | \ |
1110 | 664e0f19 | bellard | r.L(0) = d->L((base << SHIFT) + 0); \ |
1111 | 664e0f19 | bellard | r.L(1) = s->L((base << SHIFT) + 0); \ |
1112 | 664e0f19 | bellard | XMM_ONLY( \ |
1113 | 664e0f19 | bellard | r.L(2) = d->L((base << SHIFT) + 1); \ |
1114 | 664e0f19 | bellard | r.L(3) = s->L((base << SHIFT) + 1); \ |
1115 | 664e0f19 | bellard | ) \ |
1116 | 664e0f19 | bellard | *d = r; \ |
1117 | 664e0f19 | bellard | } \ |
1118 | 664e0f19 | bellard | \ |
1119 | 664e0f19 | bellard | XMM_ONLY( \ |
1120 | 5af45186 | bellard | void glue(helper_punpck ## base_name ## qdq, SUFFIX) (Reg *d, Reg *s) \ |
1121 | 664e0f19 | bellard | { \ |
1122 | 5af45186 | bellard | Reg r; \ |
1123 | 664e0f19 | bellard | \ |
1124 | 664e0f19 | bellard | r.Q(0) = d->Q(base); \
|
1125 | 664e0f19 | bellard | r.Q(1) = s->Q(base); \
|
1126 | 664e0f19 | bellard | *d = r; \ |
1127 | 664e0f19 | bellard | } \ |
1128 | 664e0f19 | bellard | ) |
1129 | 664e0f19 | bellard | |
1130 | 664e0f19 | bellard | UNPCK_OP(l, 0)
|
1131 | 664e0f19 | bellard | UNPCK_OP(h, 1)
|
1132 | 664e0f19 | bellard | |
1133 | a35f3ec7 | aurel32 | /* 3DNow! float ops */
|
1134 | a35f3ec7 | aurel32 | #if SHIFT == 0 |
1135 | 5af45186 | bellard | void helper_pi2fd(MMXReg *d, MMXReg *s)
|
1136 | a35f3ec7 | aurel32 | { |
1137 | a35f3ec7 | aurel32 | d->MMX_S(0) = int32_to_float32(s->MMX_L(0), &env->mmx_status); |
1138 | a35f3ec7 | aurel32 | d->MMX_S(1) = int32_to_float32(s->MMX_L(1), &env->mmx_status); |
1139 | a35f3ec7 | aurel32 | } |
1140 | a35f3ec7 | aurel32 | |
1141 | 5af45186 | bellard | void helper_pi2fw(MMXReg *d, MMXReg *s)
|
1142 | a35f3ec7 | aurel32 | { |
1143 | a35f3ec7 | aurel32 | d->MMX_S(0) = int32_to_float32((int16_t)s->MMX_W(0), &env->mmx_status); |
1144 | a35f3ec7 | aurel32 | d->MMX_S(1) = int32_to_float32((int16_t)s->MMX_W(2), &env->mmx_status); |
1145 | a35f3ec7 | aurel32 | } |
1146 | a35f3ec7 | aurel32 | |
1147 | 5af45186 | bellard | void helper_pf2id(MMXReg *d, MMXReg *s)
|
1148 | a35f3ec7 | aurel32 | { |
1149 | a35f3ec7 | aurel32 | d->MMX_L(0) = float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status); |
1150 | a35f3ec7 | aurel32 | d->MMX_L(1) = float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status); |
1151 | a35f3ec7 | aurel32 | } |
1152 | a35f3ec7 | aurel32 | |
1153 | 5af45186 | bellard | void helper_pf2iw(MMXReg *d, MMXReg *s)
|
1154 | a35f3ec7 | aurel32 | { |
1155 | a35f3ec7 | aurel32 | d->MMX_L(0) = satsw(float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status)); |
1156 | a35f3ec7 | aurel32 | d->MMX_L(1) = satsw(float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status)); |
1157 | a35f3ec7 | aurel32 | } |
1158 | a35f3ec7 | aurel32 | |
1159 | 5af45186 | bellard | void helper_pfacc(MMXReg *d, MMXReg *s)
|
1160 | a35f3ec7 | aurel32 | { |
1161 | a35f3ec7 | aurel32 | MMXReg r; |
1162 | a35f3ec7 | aurel32 | r.MMX_S(0) = float32_add(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
1163 | a35f3ec7 | aurel32 | r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
1164 | a35f3ec7 | aurel32 | *d = r; |
1165 | a35f3ec7 | aurel32 | } |
1166 | a35f3ec7 | aurel32 | |
1167 | 5af45186 | bellard | void helper_pfadd(MMXReg *d, MMXReg *s)
|
1168 | a35f3ec7 | aurel32 | { |
1169 | a35f3ec7 | aurel32 | d->MMX_S(0) = float32_add(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
1170 | a35f3ec7 | aurel32 | d->MMX_S(1) = float32_add(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
1171 | a35f3ec7 | aurel32 | } |
1172 | a35f3ec7 | aurel32 | |
1173 | 5af45186 | bellard | void helper_pfcmpeq(MMXReg *d, MMXReg *s)
|
1174 | a35f3ec7 | aurel32 | { |
1175 | a35f3ec7 | aurel32 | d->MMX_L(0) = float32_eq(d->MMX_S(0), s->MMX_S(0), &env->mmx_status) ? -1 : 0; |
1176 | a35f3ec7 | aurel32 | d->MMX_L(1) = float32_eq(d->MMX_S(1), s->MMX_S(1), &env->mmx_status) ? -1 : 0; |
1177 | a35f3ec7 | aurel32 | } |
1178 | a35f3ec7 | aurel32 | |
1179 | 5af45186 | bellard | void helper_pfcmpge(MMXReg *d, MMXReg *s)
|
1180 | a35f3ec7 | aurel32 | { |
1181 | a35f3ec7 | aurel32 | d->MMX_L(0) = float32_le(s->MMX_S(0), d->MMX_S(0), &env->mmx_status) ? -1 : 0; |
1182 | a35f3ec7 | aurel32 | d->MMX_L(1) = float32_le(s->MMX_S(1), d->MMX_S(1), &env->mmx_status) ? -1 : 0; |
1183 | a35f3ec7 | aurel32 | } |
1184 | a35f3ec7 | aurel32 | |
1185 | 5af45186 | bellard | void helper_pfcmpgt(MMXReg *d, MMXReg *s)
|
1186 | a35f3ec7 | aurel32 | { |
1187 | a35f3ec7 | aurel32 | d->MMX_L(0) = float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status) ? -1 : 0; |
1188 | a35f3ec7 | aurel32 | d->MMX_L(1) = float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status) ? -1 : 0; |
1189 | a35f3ec7 | aurel32 | } |
1190 | a35f3ec7 | aurel32 | |
1191 | 5af45186 | bellard | void helper_pfmax(MMXReg *d, MMXReg *s)
|
1192 | a35f3ec7 | aurel32 | { |
1193 | a35f3ec7 | aurel32 | if (float32_lt(d->MMX_S(0), s->MMX_S(0), &env->mmx_status)) |
1194 | a35f3ec7 | aurel32 | d->MMX_S(0) = s->MMX_S(0); |
1195 | a35f3ec7 | aurel32 | if (float32_lt(d->MMX_S(1), s->MMX_S(1), &env->mmx_status)) |
1196 | a35f3ec7 | aurel32 | d->MMX_S(1) = s->MMX_S(1); |
1197 | a35f3ec7 | aurel32 | } |
1198 | a35f3ec7 | aurel32 | |
1199 | 5af45186 | bellard | void helper_pfmin(MMXReg *d, MMXReg *s)
|
1200 | a35f3ec7 | aurel32 | { |
1201 | a35f3ec7 | aurel32 | if (float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status)) |
1202 | a35f3ec7 | aurel32 | d->MMX_S(0) = s->MMX_S(0); |
1203 | a35f3ec7 | aurel32 | if (float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status)) |
1204 | a35f3ec7 | aurel32 | d->MMX_S(1) = s->MMX_S(1); |
1205 | a35f3ec7 | aurel32 | } |
1206 | a35f3ec7 | aurel32 | |
1207 | 5af45186 | bellard | void helper_pfmul(MMXReg *d, MMXReg *s)
|
1208 | a35f3ec7 | aurel32 | { |
1209 | a35f3ec7 | aurel32 | d->MMX_S(0) = float32_mul(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
1210 | a35f3ec7 | aurel32 | d->MMX_S(1) = float32_mul(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
1211 | a35f3ec7 | aurel32 | } |
1212 | a35f3ec7 | aurel32 | |
1213 | 5af45186 | bellard | void helper_pfnacc(MMXReg *d, MMXReg *s)
|
1214 | a35f3ec7 | aurel32 | { |
1215 | a35f3ec7 | aurel32 | MMXReg r; |
1216 | a35f3ec7 | aurel32 | r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
1217 | a35f3ec7 | aurel32 | r.MMX_S(1) = float32_sub(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
1218 | a35f3ec7 | aurel32 | *d = r; |
1219 | a35f3ec7 | aurel32 | } |
1220 | a35f3ec7 | aurel32 | |
1221 | 5af45186 | bellard | void helper_pfpnacc(MMXReg *d, MMXReg *s)
|
1222 | a35f3ec7 | aurel32 | { |
1223 | a35f3ec7 | aurel32 | MMXReg r; |
1224 | a35f3ec7 | aurel32 | r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
1225 | a35f3ec7 | aurel32 | r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
1226 | a35f3ec7 | aurel32 | *d = r; |
1227 | a35f3ec7 | aurel32 | } |
1228 | a35f3ec7 | aurel32 | |
1229 | 5af45186 | bellard | void helper_pfrcp(MMXReg *d, MMXReg *s)
|
1230 | a35f3ec7 | aurel32 | { |
1231 | a35f3ec7 | aurel32 | d->MMX_S(0) = approx_rcp(s->MMX_S(0)); |
1232 | a35f3ec7 | aurel32 | d->MMX_S(1) = d->MMX_S(0); |
1233 | a35f3ec7 | aurel32 | } |
1234 | a35f3ec7 | aurel32 | |
1235 | 5af45186 | bellard | void helper_pfrsqrt(MMXReg *d, MMXReg *s)
|
1236 | a35f3ec7 | aurel32 | { |
1237 | a35f3ec7 | aurel32 | d->MMX_L(1) = s->MMX_L(0) & 0x7fffffff; |
1238 | a35f3ec7 | aurel32 | d->MMX_S(1) = approx_rsqrt(d->MMX_S(1)); |
1239 | a35f3ec7 | aurel32 | d->MMX_L(1) |= s->MMX_L(0) & 0x80000000; |
1240 | a35f3ec7 | aurel32 | d->MMX_L(0) = d->MMX_L(1); |
1241 | a35f3ec7 | aurel32 | } |
1242 | a35f3ec7 | aurel32 | |
1243 | 5af45186 | bellard | void helper_pfsub(MMXReg *d, MMXReg *s)
|
1244 | a35f3ec7 | aurel32 | { |
1245 | a35f3ec7 | aurel32 | d->MMX_S(0) = float32_sub(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
1246 | a35f3ec7 | aurel32 | d->MMX_S(1) = float32_sub(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
1247 | a35f3ec7 | aurel32 | } |
1248 | a35f3ec7 | aurel32 | |
1249 | 5af45186 | bellard | void helper_pfsubr(MMXReg *d, MMXReg *s)
|
1250 | a35f3ec7 | aurel32 | { |
1251 | a35f3ec7 | aurel32 | d->MMX_S(0) = float32_sub(s->MMX_S(0), d->MMX_S(0), &env->mmx_status); |
1252 | a35f3ec7 | aurel32 | d->MMX_S(1) = float32_sub(s->MMX_S(1), d->MMX_S(1), &env->mmx_status); |
1253 | a35f3ec7 | aurel32 | } |
1254 | a35f3ec7 | aurel32 | |
1255 | 5af45186 | bellard | void helper_pswapd(MMXReg *d, MMXReg *s)
|
1256 | a35f3ec7 | aurel32 | { |
1257 | a35f3ec7 | aurel32 | MMXReg r; |
1258 | a35f3ec7 | aurel32 | r.MMX_L(0) = s->MMX_L(1); |
1259 | a35f3ec7 | aurel32 | r.MMX_L(1) = s->MMX_L(0); |
1260 | a35f3ec7 | aurel32 | *d = r; |
1261 | a35f3ec7 | aurel32 | } |
1262 | a35f3ec7 | aurel32 | #endif
|
1263 | a35f3ec7 | aurel32 | |
1264 | 4242b1bd | balrog | /* SSSE3 op helpers */
|
1265 | 4242b1bd | balrog | void glue(helper_pshufb, SUFFIX) (Reg *d, Reg *s)
|
1266 | 4242b1bd | balrog | { |
1267 | 4242b1bd | balrog | int i;
|
1268 | 4242b1bd | balrog | Reg r; |
1269 | 4242b1bd | balrog | |
1270 | 4242b1bd | balrog | for (i = 0; i < (8 << SHIFT); i++) |
1271 | 4242b1bd | balrog | r.B(i) = (s->B(i) & 0x80) ? 0 : (d->B(s->B(i) & ((8 << SHIFT) - 1))); |
1272 | 4242b1bd | balrog | |
1273 | 4242b1bd | balrog | *d = r; |
1274 | 4242b1bd | balrog | } |
1275 | 4242b1bd | balrog | |
1276 | 4242b1bd | balrog | void glue(helper_phaddw, SUFFIX) (Reg *d, Reg *s)
|
1277 | 4242b1bd | balrog | { |
1278 | 4242b1bd | balrog | d->W(0) = (int16_t)d->W(0) + (int16_t)d->W(1); |
1279 | 4242b1bd | balrog | d->W(1) = (int16_t)d->W(2) + (int16_t)d->W(3); |
1280 | 4242b1bd | balrog | XMM_ONLY(d->W(2) = (int16_t)d->W(4) + (int16_t)d->W(5)); |
1281 | 4242b1bd | balrog | XMM_ONLY(d->W(3) = (int16_t)d->W(6) + (int16_t)d->W(7)); |
1282 | 4242b1bd | balrog | d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) + (int16_t)s->W(1); |
1283 | 4242b1bd | balrog | d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) + (int16_t)s->W(3); |
1284 | 4242b1bd | balrog | XMM_ONLY(d->W(6) = (int16_t)s->W(4) + (int16_t)s->W(5)); |
1285 | 4242b1bd | balrog | XMM_ONLY(d->W(7) = (int16_t)s->W(6) + (int16_t)s->W(7)); |
1286 | 4242b1bd | balrog | } |
1287 | 4242b1bd | balrog | |
1288 | 4242b1bd | balrog | void glue(helper_phaddd, SUFFIX) (Reg *d, Reg *s)
|
1289 | 4242b1bd | balrog | { |
1290 | 4242b1bd | balrog | d->L(0) = (int32_t)d->L(0) + (int32_t)d->L(1); |
1291 | 4242b1bd | balrog | XMM_ONLY(d->L(1) = (int32_t)d->L(2) + (int32_t)d->L(3)); |
1292 | 4242b1bd | balrog | d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) + (int32_t)s->L(1); |
1293 | 4242b1bd | balrog | XMM_ONLY(d->L(3) = (int32_t)s->L(2) + (int32_t)s->L(3)); |
1294 | 4242b1bd | balrog | } |
1295 | 4242b1bd | balrog | |
1296 | 4242b1bd | balrog | void glue(helper_phaddsw, SUFFIX) (Reg *d, Reg *s)
|
1297 | 4242b1bd | balrog | { |
1298 | 4242b1bd | balrog | d->W(0) = satsw((int16_t)d->W(0) + (int16_t)d->W(1)); |
1299 | 4242b1bd | balrog | d->W(1) = satsw((int16_t)d->W(2) + (int16_t)d->W(3)); |
1300 | 4242b1bd | balrog | XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) + (int16_t)d->W(5))); |
1301 | 4242b1bd | balrog | XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) + (int16_t)d->W(7))); |
1302 | 4242b1bd | balrog | d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) + (int16_t)s->W(1)); |
1303 | 4242b1bd | balrog | d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) + (int16_t)s->W(3)); |
1304 | 4242b1bd | balrog | XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) + (int16_t)s->W(5))); |
1305 | 4242b1bd | balrog | XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) + (int16_t)s->W(7))); |
1306 | 4242b1bd | balrog | } |
1307 | 4242b1bd | balrog | |
1308 | 4242b1bd | balrog | void glue(helper_pmaddubsw, SUFFIX) (Reg *d, Reg *s)
|
1309 | 4242b1bd | balrog | { |
1310 | 4242b1bd | balrog | d->W(0) = satsw((int8_t)s->B( 0) * (uint8_t)d->B( 0) + |
1311 | 4242b1bd | balrog | (int8_t)s->B( 1) * (uint8_t)d->B( 1)); |
1312 | 4242b1bd | balrog | d->W(1) = satsw((int8_t)s->B( 2) * (uint8_t)d->B( 2) + |
1313 | 4242b1bd | balrog | (int8_t)s->B( 3) * (uint8_t)d->B( 3)); |
1314 | 4242b1bd | balrog | d->W(2) = satsw((int8_t)s->B( 4) * (uint8_t)d->B( 4) + |
1315 | 4242b1bd | balrog | (int8_t)s->B( 5) * (uint8_t)d->B( 5)); |
1316 | 4242b1bd | balrog | d->W(3) = satsw((int8_t)s->B( 6) * (uint8_t)d->B( 6) + |
1317 | 4242b1bd | balrog | (int8_t)s->B( 7) * (uint8_t)d->B( 7)); |
1318 | 4242b1bd | balrog | #if SHIFT == 1 |
1319 | 4242b1bd | balrog | d->W(4) = satsw((int8_t)s->B( 8) * (uint8_t)d->B( 8) + |
1320 | 4242b1bd | balrog | (int8_t)s->B( 9) * (uint8_t)d->B( 9)); |
1321 | 4242b1bd | balrog | d->W(5) = satsw((int8_t)s->B(10) * (uint8_t)d->B(10) + |
1322 | 4242b1bd | balrog | (int8_t)s->B(11) * (uint8_t)d->B(11)); |
1323 | 4242b1bd | balrog | d->W(6) = satsw((int8_t)s->B(12) * (uint8_t)d->B(12) + |
1324 | 4242b1bd | balrog | (int8_t)s->B(13) * (uint8_t)d->B(13)); |
1325 | 4242b1bd | balrog | d->W(7) = satsw((int8_t)s->B(14) * (uint8_t)d->B(14) + |
1326 | 4242b1bd | balrog | (int8_t)s->B(15) * (uint8_t)d->B(15)); |
1327 | 4242b1bd | balrog | #endif
|
1328 | 4242b1bd | balrog | } |
1329 | 4242b1bd | balrog | |
1330 | 4242b1bd | balrog | void glue(helper_phsubw, SUFFIX) (Reg *d, Reg *s)
|
1331 | 4242b1bd | balrog | { |
1332 | 4242b1bd | balrog | d->W(0) = (int16_t)d->W(0) - (int16_t)d->W(1); |
1333 | 4242b1bd | balrog | d->W(1) = (int16_t)d->W(2) - (int16_t)d->W(3); |
1334 | 4242b1bd | balrog | XMM_ONLY(d->W(2) = (int16_t)d->W(4) - (int16_t)d->W(5)); |
1335 | 4242b1bd | balrog | XMM_ONLY(d->W(3) = (int16_t)d->W(6) - (int16_t)d->W(7)); |
1336 | 4242b1bd | balrog | d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) - (int16_t)s->W(1); |
1337 | 4242b1bd | balrog | d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) - (int16_t)s->W(3); |
1338 | 4242b1bd | balrog | XMM_ONLY(d->W(6) = (int16_t)s->W(4) - (int16_t)s->W(5)); |
1339 | 4242b1bd | balrog | XMM_ONLY(d->W(7) = (int16_t)s->W(6) - (int16_t)s->W(7)); |
1340 | 4242b1bd | balrog | } |
1341 | 4242b1bd | balrog | |
1342 | 4242b1bd | balrog | void glue(helper_phsubd, SUFFIX) (Reg *d, Reg *s)
|
1343 | 4242b1bd | balrog | { |
1344 | 4242b1bd | balrog | d->L(0) = (int32_t)d->L(0) - (int32_t)d->L(1); |
1345 | 4242b1bd | balrog | XMM_ONLY(d->L(1) = (int32_t)d->L(2) - (int32_t)d->L(3)); |
1346 | 4242b1bd | balrog | d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) - (int32_t)s->L(1); |
1347 | 4242b1bd | balrog | XMM_ONLY(d->L(3) = (int32_t)s->L(2) - (int32_t)s->L(3)); |
1348 | 4242b1bd | balrog | } |
1349 | 4242b1bd | balrog | |
1350 | 4242b1bd | balrog | void glue(helper_phsubsw, SUFFIX) (Reg *d, Reg *s)
|
1351 | 4242b1bd | balrog | { |
1352 | 4242b1bd | balrog | d->W(0) = satsw((int16_t)d->W(0) - (int16_t)d->W(1)); |
1353 | 4242b1bd | balrog | d->W(1) = satsw((int16_t)d->W(2) - (int16_t)d->W(3)); |
1354 | 4242b1bd | balrog | XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) - (int16_t)d->W(5))); |
1355 | 4242b1bd | balrog | XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) - (int16_t)d->W(7))); |
1356 | 4242b1bd | balrog | d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) - (int16_t)s->W(1)); |
1357 | 4242b1bd | balrog | d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) - (int16_t)s->W(3)); |
1358 | 4242b1bd | balrog | XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) - (int16_t)s->W(5))); |
1359 | 4242b1bd | balrog | XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) - (int16_t)s->W(7))); |
1360 | 4242b1bd | balrog | } |
1361 | 4242b1bd | balrog | |
1362 | 4242b1bd | balrog | #define FABSB(_, x) x > INT8_MAX ? -(int8_t ) x : x
|
1363 | 4242b1bd | balrog | #define FABSW(_, x) x > INT16_MAX ? -(int16_t) x : x
|
1364 | 4242b1bd | balrog | #define FABSL(_, x) x > INT32_MAX ? -(int32_t) x : x
|
1365 | 4242b1bd | balrog | SSE_HELPER_B(helper_pabsb, FABSB) |
1366 | 4242b1bd | balrog | SSE_HELPER_W(helper_pabsw, FABSW) |
1367 | 4242b1bd | balrog | SSE_HELPER_L(helper_pabsd, FABSL) |
1368 | 4242b1bd | balrog | |
1369 | 4242b1bd | balrog | #define FMULHRSW(d, s) ((int16_t) d * (int16_t) s + 0x4000) >> 15 |
1370 | 4242b1bd | balrog | SSE_HELPER_W(helper_pmulhrsw, FMULHRSW) |
1371 | 4242b1bd | balrog | |
1372 | 4242b1bd | balrog | #define FSIGNB(d, s) s <= INT8_MAX ? s ? d : 0 : -(int8_t ) d |
1373 | 4242b1bd | balrog | #define FSIGNW(d, s) s <= INT16_MAX ? s ? d : 0 : -(int16_t) d |
1374 | 4242b1bd | balrog | #define FSIGNL(d, s) s <= INT32_MAX ? s ? d : 0 : -(int32_t) d |
1375 | 4242b1bd | balrog | SSE_HELPER_B(helper_psignb, FSIGNB) |
1376 | 4242b1bd | balrog | SSE_HELPER_W(helper_psignw, FSIGNW) |
1377 | 4242b1bd | balrog | SSE_HELPER_L(helper_psignd, FSIGNL) |
1378 | 4242b1bd | balrog | |
1379 | 4242b1bd | balrog | void glue(helper_palignr, SUFFIX) (Reg *d, Reg *s, int32_t shift)
|
1380 | 4242b1bd | balrog | { |
1381 | 4242b1bd | balrog | Reg r; |
1382 | 4242b1bd | balrog | |
1383 | 4242b1bd | balrog | /* XXX could be checked during translation */
|
1384 | 4242b1bd | balrog | if (shift >= (16 << SHIFT)) { |
1385 | 4242b1bd | balrog | r.Q(0) = 0; |
1386 | 4242b1bd | balrog | XMM_ONLY(r.Q(1) = 0); |
1387 | 4242b1bd | balrog | } else {
|
1388 | 4242b1bd | balrog | shift <<= 3;
|
1389 | 4242b1bd | balrog | #define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0) |
1390 | 4242b1bd | balrog | #if SHIFT == 0 |
1391 | 4242b1bd | balrog | r.Q(0) = SHR(s->Q(0), shift - 0) | |
1392 | 4242b1bd | balrog | SHR(d->Q(0), shift - 64); |
1393 | 4242b1bd | balrog | #else
|
1394 | 4242b1bd | balrog | r.Q(0) = SHR(s->Q(0), shift - 0) | |
1395 | 4242b1bd | balrog | SHR(s->Q(1), shift - 64) | |
1396 | 4242b1bd | balrog | SHR(d->Q(0), shift - 128) | |
1397 | 4242b1bd | balrog | SHR(d->Q(1), shift - 192); |
1398 | 4242b1bd | balrog | r.Q(1) = SHR(s->Q(0), shift + 64) | |
1399 | 4242b1bd | balrog | SHR(s->Q(1), shift - 0) | |
1400 | 4242b1bd | balrog | SHR(d->Q(0), shift - 64) | |
1401 | 4242b1bd | balrog | SHR(d->Q(1), shift - 128); |
1402 | 4242b1bd | balrog | #endif
|
1403 | 4242b1bd | balrog | #undef SHR
|
1404 | 4242b1bd | balrog | } |
1405 | 4242b1bd | balrog | |
1406 | 4242b1bd | balrog | *d = r; |
1407 | 4242b1bd | balrog | } |
1408 | 4242b1bd | balrog | |
1409 | 222a3336 | balrog | #define XMM0 env->xmm_regs[0] |
1410 | 222a3336 | balrog | |
1411 | 222a3336 | balrog | #if SHIFT == 1 |
1412 | 222a3336 | balrog | #define SSE_HELPER_V(name, elem, num, F)\
|
1413 | 222a3336 | balrog | void glue(name, SUFFIX) (Reg *d, Reg *s)\
|
1414 | 222a3336 | balrog | {\ |
1415 | 222a3336 | balrog | d->elem(0) = F(d->elem(0), s->elem(0), XMM0.elem(0));\ |
1416 | 222a3336 | balrog | d->elem(1) = F(d->elem(1), s->elem(1), XMM0.elem(1));\ |
1417 | 222a3336 | balrog | if (num > 2) {\ |
1418 | 222a3336 | balrog | d->elem(2) = F(d->elem(2), s->elem(2), XMM0.elem(2));\ |
1419 | 222a3336 | balrog | d->elem(3) = F(d->elem(3), s->elem(3), XMM0.elem(3));\ |
1420 | 222a3336 | balrog | if (num > 4) {\ |
1421 | 222a3336 | balrog | d->elem(4) = F(d->elem(4), s->elem(4), XMM0.elem(4));\ |
1422 | 222a3336 | balrog | d->elem(5) = F(d->elem(5), s->elem(5), XMM0.elem(5));\ |
1423 | 222a3336 | balrog | d->elem(6) = F(d->elem(6), s->elem(6), XMM0.elem(6));\ |
1424 | 222a3336 | balrog | d->elem(7) = F(d->elem(7), s->elem(7), XMM0.elem(7));\ |
1425 | 222a3336 | balrog | if (num > 8) {\ |
1426 | 222a3336 | balrog | d->elem(8) = F(d->elem(8), s->elem(8), XMM0.elem(8));\ |
1427 | 222a3336 | balrog | d->elem(9) = F(d->elem(9), s->elem(9), XMM0.elem(9));\ |
1428 | 222a3336 | balrog | d->elem(10) = F(d->elem(10), s->elem(10), XMM0.elem(10));\ |
1429 | 222a3336 | balrog | d->elem(11) = F(d->elem(11), s->elem(11), XMM0.elem(11));\ |
1430 | 222a3336 | balrog | d->elem(12) = F(d->elem(12), s->elem(12), XMM0.elem(12));\ |
1431 | 222a3336 | balrog | d->elem(13) = F(d->elem(13), s->elem(13), XMM0.elem(13));\ |
1432 | 222a3336 | balrog | d->elem(14) = F(d->elem(14), s->elem(14), XMM0.elem(14));\ |
1433 | 222a3336 | balrog | d->elem(15) = F(d->elem(15), s->elem(15), XMM0.elem(15));\ |
1434 | 222a3336 | balrog | }\ |
1435 | 222a3336 | balrog | }\ |
1436 | 222a3336 | balrog | }\ |
1437 | 222a3336 | balrog | } |
1438 | 222a3336 | balrog | |
1439 | 222a3336 | balrog | #define SSE_HELPER_I(name, elem, num, F)\
|
1440 | 222a3336 | balrog | void glue(name, SUFFIX) (Reg *d, Reg *s, uint32_t imm)\
|
1441 | 222a3336 | balrog | {\ |
1442 | 222a3336 | balrog | d->elem(0) = F(d->elem(0), s->elem(0), ((imm >> 0) & 1));\ |
1443 | 222a3336 | balrog | d->elem(1) = F(d->elem(1), s->elem(1), ((imm >> 1) & 1));\ |
1444 | 222a3336 | balrog | if (num > 2) {\ |
1445 | 222a3336 | balrog | d->elem(2) = F(d->elem(2), s->elem(2), ((imm >> 2) & 1));\ |
1446 | 222a3336 | balrog | d->elem(3) = F(d->elem(3), s->elem(3), ((imm >> 3) & 1));\ |
1447 | 222a3336 | balrog | if (num > 4) {\ |
1448 | 222a3336 | balrog | d->elem(4) = F(d->elem(4), s->elem(4), ((imm >> 4) & 1));\ |
1449 | 222a3336 | balrog | d->elem(5) = F(d->elem(5), s->elem(5), ((imm >> 5) & 1));\ |
1450 | 222a3336 | balrog | d->elem(6) = F(d->elem(6), s->elem(6), ((imm >> 6) & 1));\ |
1451 | 222a3336 | balrog | d->elem(7) = F(d->elem(7), s->elem(7), ((imm >> 7) & 1));\ |
1452 | 222a3336 | balrog | if (num > 8) {\ |
1453 | 222a3336 | balrog | d->elem(8) = F(d->elem(8), s->elem(8), ((imm >> 8) & 1));\ |
1454 | 222a3336 | balrog | d->elem(9) = F(d->elem(9), s->elem(9), ((imm >> 9) & 1));\ |
1455 | 222a3336 | balrog | d->elem(10) = F(d->elem(10), s->elem(10), ((imm >> 10) & 1));\ |
1456 | 222a3336 | balrog | d->elem(11) = F(d->elem(11), s->elem(11), ((imm >> 11) & 1));\ |
1457 | 222a3336 | balrog | d->elem(12) = F(d->elem(12), s->elem(12), ((imm >> 12) & 1));\ |
1458 | 222a3336 | balrog | d->elem(13) = F(d->elem(13), s->elem(13), ((imm >> 13) & 1));\ |
1459 | 222a3336 | balrog | d->elem(14) = F(d->elem(14), s->elem(14), ((imm >> 14) & 1));\ |
1460 | 222a3336 | balrog | d->elem(15) = F(d->elem(15), s->elem(15), ((imm >> 15) & 1));\ |
1461 | 222a3336 | balrog | }\ |
1462 | 222a3336 | balrog | }\ |
1463 | 222a3336 | balrog | }\ |
1464 | 222a3336 | balrog | } |
1465 | 222a3336 | balrog | |
1466 | 222a3336 | balrog | /* SSE4.1 op helpers */
|
1467 | 222a3336 | balrog | #define FBLENDVB(d, s, m) (m & 0x80) ? s : d |
1468 | 222a3336 | balrog | #define FBLENDVPS(d, s, m) (m & 0x80000000) ? s : d |
1469 | 000cacf6 | balrog | #define FBLENDVPD(d, s, m) (m & 0x8000000000000000LL) ? s : d |
1470 | 222a3336 | balrog | SSE_HELPER_V(helper_pblendvb, B, 16, FBLENDVB)
|
1471 | 222a3336 | balrog | SSE_HELPER_V(helper_blendvps, L, 4, FBLENDVPS)
|
1472 | 222a3336 | balrog | SSE_HELPER_V(helper_blendvpd, Q, 2, FBLENDVPD)
|
1473 | 222a3336 | balrog | |
1474 | 222a3336 | balrog | void glue(helper_ptest, SUFFIX) (Reg *d, Reg *s)
|
1475 | 222a3336 | balrog | { |
1476 | 222a3336 | balrog | uint64_t zf = (s->Q(0) & d->Q(0)) | (s->Q(1) & d->Q(1)); |
1477 | 222a3336 | balrog | uint64_t cf = (s->Q(0) & ~d->Q(0)) | (s->Q(1) & ~d->Q(1)); |
1478 | 222a3336 | balrog | |
1479 | 222a3336 | balrog | CC_SRC = (zf ? 0 : CC_Z) | (cf ? 0 : CC_C); |
1480 | 222a3336 | balrog | } |
1481 | 222a3336 | balrog | |
1482 | 222a3336 | balrog | #define SSE_HELPER_F(name, elem, num, F)\
|
1483 | 222a3336 | balrog | void glue(name, SUFFIX) (Reg *d, Reg *s)\
|
1484 | 222a3336 | balrog | {\ |
1485 | 222a3336 | balrog | d->elem(0) = F(0);\ |
1486 | 222a3336 | balrog | d->elem(1) = F(1);\ |
1487 | dcfd12b8 | balrog | if (num > 2) {\ |
1488 | dcfd12b8 | balrog | d->elem(2) = F(2);\ |
1489 | dcfd12b8 | balrog | d->elem(3) = F(3);\ |
1490 | dcfd12b8 | balrog | if (num > 4) {\ |
1491 | dcfd12b8 | balrog | d->elem(4) = F(4);\ |
1492 | dcfd12b8 | balrog | d->elem(5) = F(5);\ |
1493 | 222a3336 | balrog | d->elem(6) = F(6);\ |
1494 | 222a3336 | balrog | d->elem(7) = F(7);\ |
1495 | 222a3336 | balrog | }\ |
1496 | 222a3336 | balrog | }\ |
1497 | 222a3336 | balrog | } |
1498 | 222a3336 | balrog | |
1499 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxbw, W, 8, (int8_t) s->B)
|
1500 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxbd, L, 4, (int8_t) s->B)
|
1501 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxbq, Q, 2, (int8_t) s->B)
|
1502 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxwd, L, 4, (int16_t) s->W)
|
1503 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxwq, Q, 2, (int16_t) s->W)
|
1504 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxdq, Q, 2, (int32_t) s->L)
|
1505 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxbw, W, 8, s->B)
|
1506 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxbd, L, 4, s->B)
|
1507 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxbq, Q, 2, s->B)
|
1508 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxwd, L, 4, s->W)
|
1509 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxwq, Q, 2, s->W)
|
1510 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxdq, Q, 2, s->L)
|
1511 | 222a3336 | balrog | |
1512 | 222a3336 | balrog | void glue(helper_pmuldq, SUFFIX) (Reg *d, Reg *s)
|
1513 | 222a3336 | balrog | { |
1514 | 222a3336 | balrog | d->Q(0) = (int64_t) (int32_t) d->L(0) * (int32_t) s->L(0); |
1515 | 222a3336 | balrog | d->Q(1) = (int64_t) (int32_t) d->L(2) * (int32_t) s->L(2); |
1516 | 222a3336 | balrog | } |
1517 | 222a3336 | balrog | |
1518 | 222a3336 | balrog | #define FCMPEQQ(d, s) d == s ? -1 : 0 |
1519 | 222a3336 | balrog | SSE_HELPER_Q(helper_pcmpeqq, FCMPEQQ) |
1520 | 222a3336 | balrog | |
1521 | 222a3336 | balrog | void glue(helper_packusdw, SUFFIX) (Reg *d, Reg *s)
|
1522 | 222a3336 | balrog | { |
1523 | 222a3336 | balrog | d->W(0) = satuw((int32_t) d->L(0)); |
1524 | 222a3336 | balrog | d->W(1) = satuw((int32_t) d->L(1)); |
1525 | 222a3336 | balrog | d->W(2) = satuw((int32_t) d->L(2)); |
1526 | 222a3336 | balrog | d->W(3) = satuw((int32_t) d->L(3)); |
1527 | 222a3336 | balrog | d->W(4) = satuw((int32_t) s->L(0)); |
1528 | 222a3336 | balrog | d->W(5) = satuw((int32_t) s->L(1)); |
1529 | 222a3336 | balrog | d->W(6) = satuw((int32_t) s->L(2)); |
1530 | 222a3336 | balrog | d->W(7) = satuw((int32_t) s->L(3)); |
1531 | 222a3336 | balrog | } |
1532 | 222a3336 | balrog | |
1533 | 222a3336 | balrog | #define FMINSB(d, s) MIN((int8_t) d, (int8_t) s)
|
1534 | 222a3336 | balrog | #define FMINSD(d, s) MIN((int32_t) d, (int32_t) s)
|
1535 | 222a3336 | balrog | #define FMAXSB(d, s) MAX((int8_t) d, (int8_t) s)
|
1536 | 222a3336 | balrog | #define FMAXSD(d, s) MAX((int32_t) d, (int32_t) s)
|
1537 | 222a3336 | balrog | SSE_HELPER_B(helper_pminsb, FMINSB) |
1538 | 222a3336 | balrog | SSE_HELPER_L(helper_pminsd, FMINSD) |
1539 | 222a3336 | balrog | SSE_HELPER_W(helper_pminuw, MIN) |
1540 | 222a3336 | balrog | SSE_HELPER_L(helper_pminud, MIN) |
1541 | 222a3336 | balrog | SSE_HELPER_B(helper_pmaxsb, FMAXSB) |
1542 | 222a3336 | balrog | SSE_HELPER_L(helper_pmaxsd, FMAXSD) |
1543 | 222a3336 | balrog | SSE_HELPER_W(helper_pmaxuw, MAX) |
1544 | 222a3336 | balrog | SSE_HELPER_L(helper_pmaxud, MAX) |
1545 | 222a3336 | balrog | |
1546 | 222a3336 | balrog | #define FMULLD(d, s) (int32_t) d * (int32_t) s
|
1547 | 222a3336 | balrog | SSE_HELPER_L(helper_pmulld, FMULLD) |
1548 | 222a3336 | balrog | |
1549 | 222a3336 | balrog | void glue(helper_phminposuw, SUFFIX) (Reg *d, Reg *s)
|
1550 | 222a3336 | balrog | { |
1551 | 222a3336 | balrog | int idx = 0; |
1552 | 222a3336 | balrog | |
1553 | 222a3336 | balrog | if (s->W(1) < s->W(idx)) |
1554 | 222a3336 | balrog | idx = 1;
|
1555 | 222a3336 | balrog | if (s->W(2) < s->W(idx)) |
1556 | 222a3336 | balrog | idx = 2;
|
1557 | 222a3336 | balrog | if (s->W(3) < s->W(idx)) |
1558 | 222a3336 | balrog | idx = 3;
|
1559 | 222a3336 | balrog | if (s->W(4) < s->W(idx)) |
1560 | 222a3336 | balrog | idx = 4;
|
1561 | 222a3336 | balrog | if (s->W(5) < s->W(idx)) |
1562 | 222a3336 | balrog | idx = 5;
|
1563 | 222a3336 | balrog | if (s->W(6) < s->W(idx)) |
1564 | 222a3336 | balrog | idx = 6;
|
1565 | 222a3336 | balrog | if (s->W(7) < s->W(idx)) |
1566 | 222a3336 | balrog | idx = 7;
|
1567 | 222a3336 | balrog | |
1568 | 222a3336 | balrog | d->Q(1) = 0; |
1569 | 222a3336 | balrog | d->L(1) = 0; |
1570 | 222a3336 | balrog | d->W(1) = idx;
|
1571 | 222a3336 | balrog | d->W(0) = s->W(idx);
|
1572 | 222a3336 | balrog | } |
1573 | 222a3336 | balrog | |
1574 | 222a3336 | balrog | void glue(helper_roundps, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
|
1575 | 222a3336 | balrog | { |
1576 | 222a3336 | balrog | signed char prev_rounding_mode; |
1577 | 222a3336 | balrog | |
1578 | 222a3336 | balrog | prev_rounding_mode = env->sse_status.float_rounding_mode; |
1579 | 222a3336 | balrog | if (!(mode & (1 << 2))) |
1580 | 222a3336 | balrog | switch (mode & 3) { |
1581 | 222a3336 | balrog | case 0: |
1582 | 222a3336 | balrog | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
1583 | 222a3336 | balrog | break;
|
1584 | 222a3336 | balrog | case 1: |
1585 | 222a3336 | balrog | set_float_rounding_mode(float_round_down, &env->sse_status); |
1586 | 222a3336 | balrog | break;
|
1587 | 222a3336 | balrog | case 2: |
1588 | 222a3336 | balrog | set_float_rounding_mode(float_round_up, &env->sse_status); |
1589 | 222a3336 | balrog | break;
|
1590 | 222a3336 | balrog | case 3: |
1591 | 222a3336 | balrog | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
1592 | 222a3336 | balrog | break;
|
1593 | 222a3336 | balrog | } |
1594 | 222a3336 | balrog | |
1595 | 222a3336 | balrog | d->L(0) = float64_round_to_int(s->L(0), &env->sse_status); |
1596 | 222a3336 | balrog | d->L(1) = float64_round_to_int(s->L(1), &env->sse_status); |
1597 | 222a3336 | balrog | d->L(2) = float64_round_to_int(s->L(2), &env->sse_status); |
1598 | 222a3336 | balrog | d->L(3) = float64_round_to_int(s->L(3), &env->sse_status); |
1599 | 222a3336 | balrog | |
1600 | 222a3336 | balrog | #if 0 /* TODO */
|
1601 | 222a3336 | balrog | if (mode & (1 << 3))
|
1602 | 222a3336 | balrog | set_float_exception_flags(
|
1603 | 222a3336 | balrog | get_float_exception_flags(&env->sse_status) &
|
1604 | 222a3336 | balrog | ~float_flag_inexact,
|
1605 | 222a3336 | balrog | &env->sse_status);
|
1606 | 222a3336 | balrog | #endif
|
1607 | 222a3336 | balrog | env->sse_status.float_rounding_mode = prev_rounding_mode; |
1608 | 222a3336 | balrog | } |
1609 | 222a3336 | balrog | |
1610 | 222a3336 | balrog | void glue(helper_roundpd, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
|
1611 | 222a3336 | balrog | { |
1612 | 222a3336 | balrog | signed char prev_rounding_mode; |
1613 | 222a3336 | balrog | |
1614 | 222a3336 | balrog | prev_rounding_mode = env->sse_status.float_rounding_mode; |
1615 | 222a3336 | balrog | if (!(mode & (1 << 2))) |
1616 | 222a3336 | balrog | switch (mode & 3) { |
1617 | 222a3336 | balrog | case 0: |
1618 | 222a3336 | balrog | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
1619 | 222a3336 | balrog | break;
|
1620 | 222a3336 | balrog | case 1: |
1621 | 222a3336 | balrog | set_float_rounding_mode(float_round_down, &env->sse_status); |
1622 | 222a3336 | balrog | break;
|
1623 | 222a3336 | balrog | case 2: |
1624 | 222a3336 | balrog | set_float_rounding_mode(float_round_up, &env->sse_status); |
1625 | 222a3336 | balrog | break;
|
1626 | 222a3336 | balrog | case 3: |
1627 | 222a3336 | balrog | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
1628 | 222a3336 | balrog | break;
|
1629 | 222a3336 | balrog | } |
1630 | 222a3336 | balrog | |
1631 | 222a3336 | balrog | d->Q(0) = float64_round_to_int(s->Q(0), &env->sse_status); |
1632 | 222a3336 | balrog | d->Q(1) = float64_round_to_int(s->Q(1), &env->sse_status); |
1633 | 222a3336 | balrog | |
1634 | 222a3336 | balrog | #if 0 /* TODO */
|
1635 | 222a3336 | balrog | if (mode & (1 << 3))
|
1636 | 222a3336 | balrog | set_float_exception_flags(
|
1637 | 222a3336 | balrog | get_float_exception_flags(&env->sse_status) &
|
1638 | 222a3336 | balrog | ~float_flag_inexact,
|
1639 | 222a3336 | balrog | &env->sse_status);
|
1640 | 222a3336 | balrog | #endif
|
1641 | 222a3336 | balrog | env->sse_status.float_rounding_mode = prev_rounding_mode; |
1642 | 222a3336 | balrog | } |
1643 | 222a3336 | balrog | |
1644 | 222a3336 | balrog | void glue(helper_roundss, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
|
1645 | 222a3336 | balrog | { |
1646 | 222a3336 | balrog | signed char prev_rounding_mode; |
1647 | 222a3336 | balrog | |
1648 | 222a3336 | balrog | prev_rounding_mode = env->sse_status.float_rounding_mode; |
1649 | 222a3336 | balrog | if (!(mode & (1 << 2))) |
1650 | 222a3336 | balrog | switch (mode & 3) { |
1651 | 222a3336 | balrog | case 0: |
1652 | 222a3336 | balrog | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
1653 | 222a3336 | balrog | break;
|
1654 | 222a3336 | balrog | case 1: |
1655 | 222a3336 | balrog | set_float_rounding_mode(float_round_down, &env->sse_status); |
1656 | 222a3336 | balrog | break;
|
1657 | 222a3336 | balrog | case 2: |
1658 | 222a3336 | balrog | set_float_rounding_mode(float_round_up, &env->sse_status); |
1659 | 222a3336 | balrog | break;
|
1660 | 222a3336 | balrog | case 3: |
1661 | 222a3336 | balrog | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
1662 | 222a3336 | balrog | break;
|
1663 | 222a3336 | balrog | } |
1664 | 222a3336 | balrog | |
1665 | 222a3336 | balrog | d->L(0) = float64_round_to_int(s->L(0), &env->sse_status); |
1666 | 222a3336 | balrog | |
1667 | 222a3336 | balrog | #if 0 /* TODO */
|
1668 | 222a3336 | balrog | if (mode & (1 << 3))
|
1669 | 222a3336 | balrog | set_float_exception_flags(
|
1670 | 222a3336 | balrog | get_float_exception_flags(&env->sse_status) &
|
1671 | 222a3336 | balrog | ~float_flag_inexact,
|
1672 | 222a3336 | balrog | &env->sse_status);
|
1673 | 222a3336 | balrog | #endif
|
1674 | 222a3336 | balrog | env->sse_status.float_rounding_mode = prev_rounding_mode; |
1675 | 222a3336 | balrog | } |
1676 | 222a3336 | balrog | |
1677 | 222a3336 | balrog | void glue(helper_roundsd, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
|
1678 | 222a3336 | balrog | { |
1679 | 222a3336 | balrog | signed char prev_rounding_mode; |
1680 | 222a3336 | balrog | |
1681 | 222a3336 | balrog | prev_rounding_mode = env->sse_status.float_rounding_mode; |
1682 | 222a3336 | balrog | if (!(mode & (1 << 2))) |
1683 | 222a3336 | balrog | switch (mode & 3) { |
1684 | 222a3336 | balrog | case 0: |
1685 | 222a3336 | balrog | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
1686 | 222a3336 | balrog | break;
|
1687 | 222a3336 | balrog | case 1: |
1688 | 222a3336 | balrog | set_float_rounding_mode(float_round_down, &env->sse_status); |
1689 | 222a3336 | balrog | break;
|
1690 | 222a3336 | balrog | case 2: |
1691 | 222a3336 | balrog | set_float_rounding_mode(float_round_up, &env->sse_status); |
1692 | 222a3336 | balrog | break;
|
1693 | 222a3336 | balrog | case 3: |
1694 | 222a3336 | balrog | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
1695 | 222a3336 | balrog | break;
|
1696 | 222a3336 | balrog | } |
1697 | 222a3336 | balrog | |
1698 | 222a3336 | balrog | d->Q(0) = float64_round_to_int(s->Q(0), &env->sse_status); |
1699 | 222a3336 | balrog | |
1700 | 222a3336 | balrog | #if 0 /* TODO */
|
1701 | 222a3336 | balrog | if (mode & (1 << 3))
|
1702 | 222a3336 | balrog | set_float_exception_flags(
|
1703 | 222a3336 | balrog | get_float_exception_flags(&env->sse_status) &
|
1704 | 222a3336 | balrog | ~float_flag_inexact,
|
1705 | 222a3336 | balrog | &env->sse_status);
|
1706 | 222a3336 | balrog | #endif
|
1707 | 222a3336 | balrog | env->sse_status.float_rounding_mode = prev_rounding_mode; |
1708 | 222a3336 | balrog | } |
1709 | 222a3336 | balrog | |
1710 | 222a3336 | balrog | #define FBLENDP(d, s, m) m ? s : d
|
1711 | 222a3336 | balrog | SSE_HELPER_I(helper_blendps, L, 4, FBLENDP)
|
1712 | 222a3336 | balrog | SSE_HELPER_I(helper_blendpd, Q, 2, FBLENDP)
|
1713 | 222a3336 | balrog | SSE_HELPER_I(helper_pblendw, W, 8, FBLENDP)
|
1714 | 222a3336 | balrog | |
1715 | 222a3336 | balrog | void glue(helper_dpps, SUFFIX) (Reg *d, Reg *s, uint32_t mask)
|
1716 | 222a3336 | balrog | { |
1717 | 222a3336 | balrog | float32 iresult = 0 /*float32_zero*/; |
1718 | 222a3336 | balrog | |
1719 | 222a3336 | balrog | if (mask & (1 << 4)) |
1720 | 222a3336 | balrog | iresult = float32_add(iresult, |
1721 | 222a3336 | balrog | float32_mul(d->L(0), s->L(0), &env->sse_status), |
1722 | 222a3336 | balrog | &env->sse_status); |
1723 | 222a3336 | balrog | if (mask & (1 << 5)) |
1724 | 222a3336 | balrog | iresult = float32_add(iresult, |
1725 | 222a3336 | balrog | float32_mul(d->L(1), s->L(1), &env->sse_status), |
1726 | 222a3336 | balrog | &env->sse_status); |
1727 | 222a3336 | balrog | if (mask & (1 << 6)) |
1728 | 222a3336 | balrog | iresult = float32_add(iresult, |
1729 | 222a3336 | balrog | float32_mul(d->L(2), s->L(2), &env->sse_status), |
1730 | 222a3336 | balrog | &env->sse_status); |
1731 | 222a3336 | balrog | if (mask & (1 << 7)) |
1732 | 222a3336 | balrog | iresult = float32_add(iresult, |
1733 | 222a3336 | balrog | float32_mul(d->L(3), s->L(3), &env->sse_status), |
1734 | 222a3336 | balrog | &env->sse_status); |
1735 | 222a3336 | balrog | d->L(0) = (mask & (1 << 0)) ? iresult : 0 /*float32_zero*/; |
1736 | 222a3336 | balrog | d->L(1) = (mask & (1 << 1)) ? iresult : 0 /*float32_zero*/; |
1737 | 222a3336 | balrog | d->L(2) = (mask & (1 << 2)) ? iresult : 0 /*float32_zero*/; |
1738 | 222a3336 | balrog | d->L(3) = (mask & (1 << 3)) ? iresult : 0 /*float32_zero*/; |
1739 | 222a3336 | balrog | } |
1740 | 222a3336 | balrog | |
1741 | 222a3336 | balrog | void glue(helper_dppd, SUFFIX) (Reg *d, Reg *s, uint32_t mask)
|
1742 | 222a3336 | balrog | { |
1743 | 222a3336 | balrog | float64 iresult = 0 /*float64_zero*/; |
1744 | 222a3336 | balrog | |
1745 | 222a3336 | balrog | if (mask & (1 << 4)) |
1746 | 222a3336 | balrog | iresult = float64_add(iresult, |
1747 | 222a3336 | balrog | float64_mul(d->Q(0), s->Q(0), &env->sse_status), |
1748 | 222a3336 | balrog | &env->sse_status); |
1749 | 222a3336 | balrog | if (mask & (1 << 5)) |
1750 | 222a3336 | balrog | iresult = float64_add(iresult, |
1751 | 222a3336 | balrog | float64_mul(d->Q(1), s->Q(1), &env->sse_status), |
1752 | 222a3336 | balrog | &env->sse_status); |
1753 | 222a3336 | balrog | d->Q(0) = (mask & (1 << 0)) ? iresult : 0 /*float64_zero*/; |
1754 | 222a3336 | balrog | d->Q(1) = (mask & (1 << 1)) ? iresult : 0 /*float64_zero*/; |
1755 | 222a3336 | balrog | } |
1756 | 222a3336 | balrog | |
1757 | 222a3336 | balrog | void glue(helper_mpsadbw, SUFFIX) (Reg *d, Reg *s, uint32_t offset)
|
1758 | 222a3336 | balrog | { |
1759 | 222a3336 | balrog | int s0 = (offset & 3) << 2; |
1760 | 222a3336 | balrog | int d0 = (offset & 4) << 0; |
1761 | 222a3336 | balrog | int i;
|
1762 | 222a3336 | balrog | Reg r; |
1763 | 222a3336 | balrog | |
1764 | 222a3336 | balrog | for (i = 0; i < 8; i++, d0++) { |
1765 | 222a3336 | balrog | r.W(i) = 0;
|
1766 | 222a3336 | balrog | r.W(i) += abs1(d->B(d0 + 0) - s->B(s0 + 0)); |
1767 | 222a3336 | balrog | r.W(i) += abs1(d->B(d0 + 1) - s->B(s0 + 1)); |
1768 | 222a3336 | balrog | r.W(i) += abs1(d->B(d0 + 2) - s->B(s0 + 2)); |
1769 | 222a3336 | balrog | r.W(i) += abs1(d->B(d0 + 3) - s->B(s0 + 3)); |
1770 | 222a3336 | balrog | } |
1771 | 222a3336 | balrog | |
1772 | 222a3336 | balrog | *d = r; |
1773 | 222a3336 | balrog | } |
1774 | 222a3336 | balrog | |
1775 | 222a3336 | balrog | /* SSE4.2 op helpers */
|
1776 | 222a3336 | balrog | /* it's unclear whether signed or unsigned */
|
1777 | 222a3336 | balrog | #define FCMPGTQ(d, s) d > s ? -1 : 0 |
1778 | 222a3336 | balrog | SSE_HELPER_Q(helper_pcmpgtq, FCMPGTQ) |
1779 | 222a3336 | balrog | |
1780 | 222a3336 | balrog | static inline int pcmp_elen(int reg, uint32_t ctrl) |
1781 | 222a3336 | balrog | { |
1782 | 222a3336 | balrog | int val;
|
1783 | 222a3336 | balrog | |
1784 | 222a3336 | balrog | /* Presence of REX.W is indicated by a bit higher than 7 set */
|
1785 | 222a3336 | balrog | if (ctrl >> 8) |
1786 | 222a3336 | balrog | val = abs1((int64_t) env->regs[reg]); |
1787 | 222a3336 | balrog | else
|
1788 | 222a3336 | balrog | val = abs1((int32_t) env->regs[reg]); |
1789 | 222a3336 | balrog | |
1790 | 222a3336 | balrog | if (ctrl & 1) { |
1791 | 222a3336 | balrog | if (val > 8) |
1792 | 222a3336 | balrog | return 8; |
1793 | 222a3336 | balrog | } else
|
1794 | 222a3336 | balrog | if (val > 16) |
1795 | 222a3336 | balrog | return 16; |
1796 | 222a3336 | balrog | |
1797 | 222a3336 | balrog | return val;
|
1798 | 222a3336 | balrog | } |
1799 | 222a3336 | balrog | |
1800 | 222a3336 | balrog | static inline int pcmp_ilen(Reg *r, uint8_t ctrl) |
1801 | 222a3336 | balrog | { |
1802 | 222a3336 | balrog | int val = 0; |
1803 | 222a3336 | balrog | |
1804 | 222a3336 | balrog | if (ctrl & 1) { |
1805 | 222a3336 | balrog | while (val < 8 && r->W(val)) |
1806 | 222a3336 | balrog | val++; |
1807 | 222a3336 | balrog | } else
|
1808 | 222a3336 | balrog | while (val < 16 && r->B(val)) |
1809 | 222a3336 | balrog | val++; |
1810 | 222a3336 | balrog | |
1811 | 222a3336 | balrog | return val;
|
1812 | 222a3336 | balrog | } |
1813 | 222a3336 | balrog | |
1814 | 222a3336 | balrog | static inline int pcmp_val(Reg *r, uint8_t ctrl, int i) |
1815 | 222a3336 | balrog | { |
1816 | 222a3336 | balrog | switch ((ctrl >> 0) & 3) { |
1817 | 222a3336 | balrog | case 0: |
1818 | 222a3336 | balrog | return r->B(i);
|
1819 | 222a3336 | balrog | case 1: |
1820 | 222a3336 | balrog | return r->W(i);
|
1821 | 222a3336 | balrog | case 2: |
1822 | 222a3336 | balrog | return (int8_t) r->B(i);
|
1823 | 222a3336 | balrog | case 3: |
1824 | 222a3336 | balrog | default:
|
1825 | 222a3336 | balrog | return (int16_t) r->W(i);
|
1826 | 222a3336 | balrog | } |
1827 | 222a3336 | balrog | } |
1828 | 222a3336 | balrog | |
1829 | 222a3336 | balrog | static inline unsigned pcmpxstrx(Reg *d, Reg *s, |
1830 | 222a3336 | balrog | int8_t ctrl, int valids, int validd) |
1831 | 222a3336 | balrog | { |
1832 | 222a3336 | balrog | unsigned int res = 0; |
1833 | 222a3336 | balrog | int v;
|
1834 | 222a3336 | balrog | int j, i;
|
1835 | 222a3336 | balrog | int upper = (ctrl & 1) ? 7 : 15; |
1836 | 222a3336 | balrog | |
1837 | 222a3336 | balrog | valids--; |
1838 | 222a3336 | balrog | validd--; |
1839 | 222a3336 | balrog | |
1840 | 222a3336 | balrog | CC_SRC = (valids < upper ? CC_Z : 0) | (validd < upper ? CC_S : 0); |
1841 | 222a3336 | balrog | |
1842 | 222a3336 | balrog | switch ((ctrl >> 2) & 3) { |
1843 | 222a3336 | balrog | case 0: |
1844 | 222a3336 | balrog | for (j = valids; j >= 0; j--) { |
1845 | 222a3336 | balrog | res <<= 1;
|
1846 | 222a3336 | balrog | v = pcmp_val(s, ctrl, j); |
1847 | 222a3336 | balrog | for (i = validd; i >= 0; i--) |
1848 | 222a3336 | balrog | res |= (v == pcmp_val(d, ctrl, i)); |
1849 | 222a3336 | balrog | } |
1850 | 222a3336 | balrog | break;
|
1851 | 222a3336 | balrog | case 1: |
1852 | 222a3336 | balrog | for (j = valids; j >= 0; j--) { |
1853 | 222a3336 | balrog | res <<= 1;
|
1854 | 222a3336 | balrog | v = pcmp_val(s, ctrl, j); |
1855 | 222a3336 | balrog | for (i = ((validd - 1) | 1); i >= 0; i -= 2) |
1856 | 222a3336 | balrog | res |= (pcmp_val(d, ctrl, i - 0) <= v &&
|
1857 | 222a3336 | balrog | pcmp_val(d, ctrl, i - 1) >= v);
|
1858 | 222a3336 | balrog | } |
1859 | 222a3336 | balrog | break;
|
1860 | 222a3336 | balrog | case 2: |
1861 | 222a3336 | balrog | res = (2 << (upper - MAX(valids, validd))) - 1; |
1862 | 222a3336 | balrog | res <<= MAX(valids, validd) - MIN(valids, validd); |
1863 | 222a3336 | balrog | for (i = MIN(valids, validd); i >= 0; i--) { |
1864 | 222a3336 | balrog | res <<= 1;
|
1865 | 222a3336 | balrog | v = pcmp_val(s, ctrl, i); |
1866 | 222a3336 | balrog | res |= (v == pcmp_val(d, ctrl, i)); |
1867 | 222a3336 | balrog | } |
1868 | 222a3336 | balrog | break;
|
1869 | 222a3336 | balrog | case 3: |
1870 | 222a3336 | balrog | for (j = valids - validd; j >= 0; j--) { |
1871 | 222a3336 | balrog | res <<= 1;
|
1872 | 222a3336 | balrog | res |= 1;
|
1873 | 222a3336 | balrog | for (i = MIN(upper - j, validd); i >= 0; i--) |
1874 | 222a3336 | balrog | res &= (pcmp_val(s, ctrl, i + j) == pcmp_val(d, ctrl, i)); |
1875 | 222a3336 | balrog | } |
1876 | 222a3336 | balrog | break;
|
1877 | 222a3336 | balrog | } |
1878 | 222a3336 | balrog | |
1879 | 222a3336 | balrog | switch ((ctrl >> 4) & 3) { |
1880 | 222a3336 | balrog | case 1: |
1881 | 222a3336 | balrog | res ^= (2 << upper) - 1; |
1882 | 222a3336 | balrog | break;
|
1883 | 222a3336 | balrog | case 3: |
1884 | 222a3336 | balrog | res ^= (2 << valids) - 1; |
1885 | 222a3336 | balrog | break;
|
1886 | 222a3336 | balrog | } |
1887 | 222a3336 | balrog | |
1888 | 222a3336 | balrog | if (res)
|
1889 | 222a3336 | balrog | CC_SRC |= CC_C; |
1890 | 222a3336 | balrog | if (res & 1) |
1891 | 222a3336 | balrog | CC_SRC |= CC_O; |
1892 | 222a3336 | balrog | |
1893 | 222a3336 | balrog | return res;
|
1894 | 222a3336 | balrog | } |
1895 | 222a3336 | balrog | |
1896 | 222a3336 | balrog | static inline int rffs1(unsigned int val) |
1897 | 222a3336 | balrog | { |
1898 | 222a3336 | balrog | int ret = 1, hi; |
1899 | 222a3336 | balrog | |
1900 | 222a3336 | balrog | for (hi = sizeof(val) * 4; hi; hi /= 2) |
1901 | 222a3336 | balrog | if (val >> hi) {
|
1902 | 222a3336 | balrog | val >>= hi; |
1903 | 222a3336 | balrog | ret += hi; |
1904 | 222a3336 | balrog | } |
1905 | 222a3336 | balrog | |
1906 | 222a3336 | balrog | return ret;
|
1907 | 222a3336 | balrog | } |
1908 | 222a3336 | balrog | |
1909 | 222a3336 | balrog | static inline int ffs1(unsigned int val) |
1910 | 222a3336 | balrog | { |
1911 | 222a3336 | balrog | int ret = 1, hi; |
1912 | 222a3336 | balrog | |
1913 | 222a3336 | balrog | for (hi = sizeof(val) * 4; hi; hi /= 2) |
1914 | 222a3336 | balrog | if (val << hi) {
|
1915 | 222a3336 | balrog | val <<= hi; |
1916 | 222a3336 | balrog | ret += hi; |
1917 | 222a3336 | balrog | } |
1918 | 222a3336 | balrog | |
1919 | 222a3336 | balrog | return ret;
|
1920 | 222a3336 | balrog | } |
1921 | 222a3336 | balrog | |
1922 | 222a3336 | balrog | void glue(helper_pcmpestri, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
|
1923 | 222a3336 | balrog | { |
1924 | 222a3336 | balrog | unsigned int res = pcmpxstrx(d, s, ctrl, |
1925 | 222a3336 | balrog | pcmp_elen(R_EDX, ctrl), |
1926 | 222a3336 | balrog | pcmp_elen(R_EAX, ctrl)); |
1927 | 222a3336 | balrog | |
1928 | 222a3336 | balrog | if (res)
|
1929 | 222a3336 | balrog | env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1; |
1930 | 222a3336 | balrog | else
|
1931 | 222a3336 | balrog | env->regs[R_ECX] = 16 >> (ctrl & (1 << 0)); |
1932 | 222a3336 | balrog | } |
1933 | 222a3336 | balrog | |
1934 | 222a3336 | balrog | void glue(helper_pcmpestrm, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
|
1935 | 222a3336 | balrog | { |
1936 | 222a3336 | balrog | int i;
|
1937 | 222a3336 | balrog | unsigned int res = pcmpxstrx(d, s, ctrl, |
1938 | 222a3336 | balrog | pcmp_elen(R_EDX, ctrl), |
1939 | 222a3336 | balrog | pcmp_elen(R_EAX, ctrl)); |
1940 | 222a3336 | balrog | |
1941 | 222a3336 | balrog | if ((ctrl >> 6) & 1) { |
1942 | 222a3336 | balrog | if (ctrl & 1) |
1943 | 222a3336 | balrog | for (i = 0; i <= 8; i--, res >>= 1) |
1944 | 222a3336 | balrog | d->W(i) = (res & 1) ? ~0 : 0; |
1945 | 222a3336 | balrog | else
|
1946 | 222a3336 | balrog | for (i = 0; i <= 16; i--, res >>= 1) |
1947 | 222a3336 | balrog | d->B(i) = (res & 1) ? ~0 : 0; |
1948 | 222a3336 | balrog | } else {
|
1949 | 222a3336 | balrog | d->Q(1) = 0; |
1950 | 222a3336 | balrog | d->Q(0) = res;
|
1951 | 222a3336 | balrog | } |
1952 | 222a3336 | balrog | } |
1953 | 222a3336 | balrog | |
1954 | 222a3336 | balrog | void glue(helper_pcmpistri, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
|
1955 | 222a3336 | balrog | { |
1956 | 222a3336 | balrog | unsigned int res = pcmpxstrx(d, s, ctrl, |
1957 | 222a3336 | balrog | pcmp_ilen(s, ctrl), |
1958 | 222a3336 | balrog | pcmp_ilen(d, ctrl)); |
1959 | 222a3336 | balrog | |
1960 | 222a3336 | balrog | if (res)
|
1961 | 222a3336 | balrog | env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1; |
1962 | 222a3336 | balrog | else
|
1963 | 222a3336 | balrog | env->regs[R_ECX] = 16 >> (ctrl & (1 << 0)); |
1964 | 222a3336 | balrog | } |
1965 | 222a3336 | balrog | |
1966 | 222a3336 | balrog | void glue(helper_pcmpistrm, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
|
1967 | 222a3336 | balrog | { |
1968 | 222a3336 | balrog | int i;
|
1969 | 222a3336 | balrog | unsigned int res = pcmpxstrx(d, s, ctrl, |
1970 | 222a3336 | balrog | pcmp_ilen(s, ctrl), |
1971 | 222a3336 | balrog | pcmp_ilen(d, ctrl)); |
1972 | 222a3336 | balrog | |
1973 | 222a3336 | balrog | if ((ctrl >> 6) & 1) { |
1974 | 222a3336 | balrog | if (ctrl & 1) |
1975 | 222a3336 | balrog | for (i = 0; i <= 8; i--, res >>= 1) |
1976 | 222a3336 | balrog | d->W(i) = (res & 1) ? ~0 : 0; |
1977 | 222a3336 | balrog | else
|
1978 | 222a3336 | balrog | for (i = 0; i <= 16; i--, res >>= 1) |
1979 | 222a3336 | balrog | d->B(i) = (res & 1) ? ~0 : 0; |
1980 | 222a3336 | balrog | } else {
|
1981 | 222a3336 | balrog | d->Q(1) = 0; |
1982 | 222a3336 | balrog | d->Q(0) = res;
|
1983 | 222a3336 | balrog | } |
1984 | 222a3336 | balrog | } |
1985 | 222a3336 | balrog | |
1986 | 222a3336 | balrog | #define CRCPOLY 0x1edc6f41 |
1987 | 222a3336 | balrog | #define CRCPOLY_BITREV 0x82f63b78 |
1988 | 222a3336 | balrog | target_ulong helper_crc32(uint32_t crc1, target_ulong msg, uint32_t len) |
1989 | 222a3336 | balrog | { |
1990 | 222a3336 | balrog | target_ulong crc = (msg & ((target_ulong) -1 >>
|
1991 | 222a3336 | balrog | (TARGET_LONG_BITS - len))) ^ crc1; |
1992 | 222a3336 | balrog | |
1993 | 222a3336 | balrog | while (len--)
|
1994 | 222a3336 | balrog | crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_BITREV : 0); |
1995 | 222a3336 | balrog | |
1996 | 222a3336 | balrog | return crc;
|
1997 | 222a3336 | balrog | } |
1998 | 222a3336 | balrog | |
1999 | 222a3336 | balrog | #define POPMASK(i) ((target_ulong) -1 / ((1LL << (1 << i)) + 1)) |
2000 | 222a3336 | balrog | #define POPCOUNT(n, i) (n & POPMASK(i)) + ((n >> (1 << i)) & POPMASK(i)) |
2001 | 222a3336 | balrog | target_ulong helper_popcnt(target_ulong n, uint32_t type) |
2002 | 222a3336 | balrog | { |
2003 | 222a3336 | balrog | CC_SRC = n ? 0 : CC_Z;
|
2004 | 222a3336 | balrog | |
2005 | 222a3336 | balrog | n = POPCOUNT(n, 0);
|
2006 | 222a3336 | balrog | n = POPCOUNT(n, 1);
|
2007 | 222a3336 | balrog | n = POPCOUNT(n, 2);
|
2008 | 222a3336 | balrog | n = POPCOUNT(n, 3);
|
2009 | 222a3336 | balrog | if (type == 1) |
2010 | 222a3336 | balrog | return n & 0xff; |
2011 | 222a3336 | balrog | |
2012 | 222a3336 | balrog | n = POPCOUNT(n, 4);
|
2013 | 222a3336 | balrog | #ifndef TARGET_X86_64
|
2014 | 222a3336 | balrog | return n;
|
2015 | 222a3336 | balrog | #else
|
2016 | 222a3336 | balrog | if (type == 2) |
2017 | 222a3336 | balrog | return n & 0xff; |
2018 | 222a3336 | balrog | |
2019 | 222a3336 | balrog | return POPCOUNT(n, 5); |
2020 | 222a3336 | balrog | #endif
|
2021 | 222a3336 | balrog | } |
2022 | 222a3336 | balrog | #endif
|
2023 | 222a3336 | balrog | |
2024 | 664e0f19 | bellard | #undef SHIFT
|
2025 | 664e0f19 | bellard | #undef XMM_ONLY
|
2026 | 664e0f19 | bellard | #undef Reg
|
2027 | 664e0f19 | bellard | #undef B
|
2028 | 664e0f19 | bellard | #undef W
|
2029 | 664e0f19 | bellard | #undef L
|
2030 | 664e0f19 | bellard | #undef Q
|
2031 | 664e0f19 | bellard | #undef SUFFIX |