Archipelago » qemu

/* This should not be used by devices.  */

ram_addr_t qemu_ram_addr_from_host(void *ptr);

                           CPUWriteMemoryFunc **mem_write,

                           void *opaque);

void cpu_unregister_io_memory(int table_address);

    mmio = qemu_mallocz(sizeof(subpage_t));

    mmio->base = base;

#if defined(DEBUG_SUBPAGE)

    printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,

           mmio, base, TARGET_PAGE_SIZE, subpage_memory);

    return -1;

}

static void io_mem_init(void)

{

    int i;

    for (i=0; i<5; i++)

        io_mem_used[i] = 1;

                                          watch_mem_write, NULL);

#ifdef CONFIG_KQEMU

    if (kqemu_phys_ram_base) {

   modified. If it is zero, a new io zone is allocated. The return

   value can be used with cpu_register_physical_memory(). (-1) is

   returned if error. */

{

    int i, subwidth = 0;

        if (io_index == -1)

            return io_index;

    } else {

        if (io_index >= IO_MEM_NB_ENTRIES)

            return -1;

    }

    return (io_index << IO_MEM_SHIFT) | subwidth;

}

void cpu_unregister_io_memory(int io_table_address)

{

    int i;

    s->bus = pci_register_bus(NULL, "pci",

                              pci_apb_set_irq, pci_pbm_map_irq, pic, 0, 32);

                                            pci_apb_config_write, s);

                                        apb_config_write, s);

                                          pci_apb_write, s);

                                          pci_apb_iowrite, s);

    cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config);

    if (apic_io_memory == 0) {

        /* NOTE: the APIC is directly connected to the CPU - it is not

           on the global memory bus. */

                                                apic_mem_write, NULL);

        cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,

                                     apic_io_memory);

    for (i = 0; i < NCPU; i++) {

        sysbus_init_irq(&s->busdev, &s->parent_irq[i]);

    }

                                          gic_dist_writefn, s);

    gic_reset(s);

    register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);

    /* The MPcore bootloader uses these flags to start secondary CPUs.

       We don't use a bootloader, so do this here.  */

    s->flags = 3;

                                       arm_sysctl_writefn, s);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    /* ??? Save/restore.  */

    s->timer[1] = arm_timer_init(1000000);

    s->timer[0]->irq = qi[0];

    s->timer[1]->irq = qi[1];

                                       sp804_writefn, s);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);

    sysbus_init_irq(dev, &s->timer[1]->irq);

    sysbus_init_irq(dev, &s->timer[2]->irq);

                                       icp_pit_writefn, s);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    /* This device has no state to save/restore.  The component timers will

    int iomemtype;

    s->base = qdev_get_prop_int(&dev->qdev, "base", 0);

                                       &s->base);

    sysbus_init_mmio(dev, 0x02000000, iomemtype);

}

      /* Attach a NAND flash to CS1.  */

    nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);

    cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);

    gpio_state.nand = &nand_state;

    cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);

    register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);

    register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);

                                                  cirrus_vga_mem_write, s);

    cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,

                                 s->vga.vga_io_memory);

    /* I/O handler for LFB */

    s->cirrus_linear_io_addr =

    /* I/O handler for LFB */

    s->cirrus_linear_bitblt_io_addr =

                               cirrus_linear_bitblt_write, s);

    /* I/O handler for memory-mapped I/O */

    s->cirrus_mmio_io_addr =

    s->real_vram_size =

        (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;

    s = qemu_mallocz(sizeof(CSState));

    cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);

    register_savevm("cs4231", base, 1, cs_save, cs_load, s);

    qemu_register_reset(cs_reset, 0, s);

    s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;

    s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);

    register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);

    qemu_register_reset(cuda_reset, 0, s);

    cuda_reset(s);

    qemu_register_reset(nic_reset, 0, s);

    nic_reset(s);

    cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);

}

    }

    /* Read/write memory */

    cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);

    /* Read/write protected memory */

    cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP);

    return s;

}

    pci_conf[0x3d] = 1; // interrupt pin 0

            e1000_mmio_write, d);

    pci_register_io_region((PCIDevice *)d, 0, PNPMMIO_SIZE,

    s->regs[0] = version;

    s->irq = irq;

    cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);

    if (version == ECC_MCC) { // SS-600MP only

                                               ecc_diag_mem_write, s);

        cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,

                                     ecc_io_memory);

    /* Handler for memory-mapped I/O */

    d->eepro100.mmio_index =

    pci_register_io_region(&d->dev, 0, PCI_MEM_SIZE,

                           PCI_ADDRESS_SPACE_MEM |

    s = qemu_mallocz(sizeof(SerialState));

                                            escc_mem_write,

                                            s);

    if (base)

    s->chn[0].disabled = disabled;

    s->chn[1].disabled = disabled;

                                                     escc_mem_write,

                                                     s);

    cpu_register_physical_memory(base, ESCC_SIZE << it_shift,

    s->dma_memory_write = qdev_get_prop_ptr(&dev->qdev, "dma_memory_write");

    s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma_opaque");

    sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);

    esp_reset(s);

	ctrl->nr_channels = nr_channels;

	ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);

	cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);

	return ctrl;

}

	tdk_init(&eth->phy);

	mdio_attach(&eth->mdio_bus, &eth->phy, eth->phyaddr);

	cpu_register_physical_memory (base, 0x5c, eth->ethregs);

	eth->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,

    sysbus_init_irq(dev, &s->parent_irq);

    sysbus_init_irq(dev, &s->parent_nmi);

    sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs);

}

    s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);

    sysbus_init_irq(dev, &s->irq);

    sysbus_init_mmio(dev, R_MAX * 4, ser_regs);

    s->chr = qdev_init_chardev(&dev->qdev);

    if (s->chr)

    sysbus_init_irq(dev, &t->irq);

    sysbus_init_irq(dev, &t->nmi);

    sysbus_init_mmio(dev, 0x5c, timer_regs);

    qemu_register_reset(etraxfs_timer_reset, 0, t);

    fdctrl->sun4m = 0;

    if (mem_mapped) {

                                        fdctrl);

        cpu_register_physical_memory(io_base, 0x08, io_mem);

    } else {

    fdctrl = fdctrl_init_common(irq, -1, io_base, fds);

    fdctrl->sun4m = 1;

                                    fdctrl_mem_write_strict,

                                    fdctrl);

    cpu_register_physical_memory(io_base, 0x08, io_mem);

        register_ioport_write(data_port, 1, 1, fw_cfg_io_writeb, s);

    }

    if (ctl_addr) {

                                           fw_cfg_ctl_mem_write, s);

        cpu_register_physical_memory(ctl_addr, FW_CFG_SIZE, io_ctl_memory);

    }

    if (data_addr) {

                                           fw_cfg_data_mem_write, s);

        cpu_register_physical_memory(data_addr, FW_CFG_SIZE, io_data_memory);

    }

    cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);

    cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);

    return 0;

                              pci_grackle_set_irq, pci_grackle_map_irq,

                              pic, 0, 4);

                                            pci_grackle_config_write, s);

                                          pci_grackle_write, s);

    cpu_register_physical_memory(base, 0x1000, pci_mem_config);

    cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);

    s->pci->bus = pci_register_bus(NULL, "pci",

                                   pci_gt64120_set_irq, pci_gt64120_map_irq,

                                   pic, 144, 4);

    d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),

                            0, gt64120_read_config, gt64120_write_config);

    s = qemu_mallocz(sizeof(HeathrowPICS));

    /* only 1 CPU */

    s->irqs = irqs[0];

    register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,

                    heathrow_pic_load, s);

    register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);

    qemu_register_reset(hpet_reset, 0, s);

    /* HPET Area */

                                       hpet_ram_write, s);

    cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);

}

    if (dbdma)

        DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);

                                             pmac_ide_write, d);

    register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d);

    qemu_register_reset(pmac_ide_reset, 0, d);

    s->dev = ide;

    s->shift = shift;

    cpu_register_physical_memory(membase, 16 << shift, mem1);

    cpu_register_physical_memory(membase2, 2 << shift, mem2);

}

    s->cm_init = 0x00000112;

    s->flash_offset = qemu_ram_alloc(0x100000);

                                       integratorcm_writefn, s);

    sysbus_init_mmio(dev, 0x00800000, iomemtype);

    integratorcm_do_remap(s, 1);

    qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);

    sysbus_init_irq(dev, &s->parent_irq);

    sysbus_init_irq(dev, &s->parent_fiq);

                                       icp_pic_writefn, s);

    sysbus_init_mmio(dev, 0x00800000, iomemtype);

}

{

    int iomemtype;

                                       icp_control_writefn, NULL);

    cpu_register_physical_memory(base, 0x00800000, iomemtype);

    /* ??? Save/restore.  */

    s = qemu_mallocz(sizeof(IOAPICState));

    ioapic_reset(s);

                                       ioapic_mem_write, s);

    cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);

    s->version = version;

    s->irq = irq;

                                             iommu_mem_write, s);

    cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);

void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)

{

    if (!isa_mmio_iomemtype) {

                                                    isa_mmio_write, NULL);

    }

    cpu_register_physical_memory(base, size, isa_mmio_iomemtype);

    s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;

    cpu_register_physical_memory(base, 1, io);

    s->ds = graphic_console_init(jazz_led_update_display,

    /* Interrupt pin 1 */

    pci_conf[0x3d] = 0x01;

                                             lsi_mmio_writefn, s);

                                            lsi_ram_writefn, s);

    pci_register_io_region((struct PCIDevice *)s, 0, 256,

        register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);

    }

    if (mem_base != 0) {

        cpu_register_physical_memory(mem_base, size, s->mem_index);

    }

    if (type == 59) {

    s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);

    register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);

    qemu_register_reset(dbdma_reset, 0, s);

    dbdma_reset(s);

    s->size = size;

    s->it_shift = it_shift;

    *mem_index = s->mem_index;

    register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,

                    s);

    s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;

    qemu_mod_timer(s->second_timer2, s->next_second_time);

    cpu_register_physical_memory(base, 2 << it_shift, io_memory);

    register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);

    int iomemtype;

    s = (m5206_mbar_state *)qemu_mallocz(sizeof(m5206_mbar_state));

                                       m5206_mbar_writefn, s);

    cpu_register_physical_memory(base, 0x00001000, iomemtype);

    QEMUBH *bh;

    int i;

                                       m5208_sys_writefn, NULL);

    /* SDRAMC.  */

    cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);

        s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state));

        bh = qemu_bh_new(m5208_timer_trigger, s);

        s->timer = ptimer_init(bh);

                                           m5208_timer_writefn, s);

        cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,

                                     iomemtype);

    s = (mcf_fec_state *)qemu_mallocz(sizeof(mcf_fec_state));

    s->irq = irq;

                                           mcf_fec_writefn, s);

    cpu_register_physical_memory(base, 0x400, s->mmio_index);

    s->env = env;

    mcf_intc_reset(s);

                                       mcf_intc_writefn, s);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    int iomemtype;

    s = mcf_uart_init(irq, chr);

                                       mcf_uart_writefn, s);

    cpu_register_physical_memory(base, 0x40, iomemtype);

}

    /* Chipset */

    rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);

    cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);

    /* ISA devices */

    /* Real time clock */

    rtc_init(0x70, i8259[8], 1980);

    cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);

    /* Keyboard (i8042) */

    s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));

                                   malta_fpga_write, s);

    cpu_register_physical_memory(base, 0x900, malta);

    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);

    if (!mips_qemu_iomemtype) {

                                                     mips_qemu_write, NULL);

    }

    cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);

    int i;

    gic_init(&s->gic);

                                          mpcore_priv_writefn, s);

    sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);

    for (i = 0; i < 8; i++) {

	qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);

	s->pins = qi;

		mst_fpga_writefn, s);

	cpu_register_physical_memory(base, 0x00100000, iomemtype);

	register_savevm("mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s);

    s->wm = i2c_create_slave(i2c->bus, "wm8750", MP_WM_ADDR);

    wm8750_data_req_set(s->wm, audio_callback, s);

                       musicpal_audio_writefn, s);

    cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);

    s->vc = qdev_get_vlan_client(&dev->qdev,

                                 eth_can_receive, eth_receive, NULL,

                                 eth_cleanup, s);

                                           mv88w8618_eth_writefn, s);

    sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);

}

    musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);

    int iomemtype;

                                       musicpal_lcd_writefn, s);

    sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);

    cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype);

    qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);

    sysbus_init_irq(dev, &s->parent_irq);

                                       mv88w8618_pic_writefn, s);

    sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);

        mv88w8618_timer_init(dev, &s->timer[i], 1000000);

    }

                                       mv88w8618_pit_writefn, s);

    sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);

}

    mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);

    s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */

                       mv88w8618_flashcfg_writefn, s);

    sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);

}

{

    int iomemtype;

                                       musicpal_misc_writefn, NULL);

    cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);

}

{

    int iomemtype;

                                       mv88w8618_wlan_writefn, NULL);

    sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);

}

{

    int iomemtype;

                                       musicpal_gpio_writefn, NULL);

    cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype);

}

static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };

static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };

                CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,

                void *opaque)

{

    s->mem_write = mem_write;

    s->opaque = opaque;

    s->in = 0;

}

#  define cpu_register_io_memory	debug_register_io_memory

# endif

# ifdef L4_MUX_HACK

#  undef l4_register_io_memory

                CPUWriteMemoryFunc **mem_write, void *opaque);

# endif

    omap_inth_reset(s);

                    omap_inth_writefn, s);

    cpu_register_physical_memory(base, size, iomemtype);

    omap_inth_reset(s);

                    omap2_inth_writefn, s);

    cpu_register_physical_memory(base, size, iomemtype);

    omap_mpu_timer_reset(s);

    omap_timer_clk_setup(s);

                    omap_mpu_timer_writefn, s);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    omap_wd_timer_reset(s);

    omap_timer_clk_setup(&s->timer);

                    omap_wd_timer_writefn, s);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    omap_os_timer_reset(s);

    omap_timer_clk_setup(&s->timer);

                    omap_os_timer_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

static void omap_ulpd_pm_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

                    omap_ulpd_pm_writefn, mpu);

    cpu_register_physical_memory(base, 0x800, iomemtype);

static void omap_pin_cfg_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

                    omap_pin_cfg_writefn, mpu);

    cpu_register_physical_memory(base, 0x800, iomemtype);

static void omap_id_init(struct omap_mpu_state_s *mpu)

{

                    omap_id_writefn, mpu);

    cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);

    cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);

static void omap_mpui_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

                    omap_mpui_writefn, mpu);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    s->abort = abort_irq;

    omap_tipb_bridge_reset(s);

                    omap_tipb_bridge_writefn, s);

    cpu_register_physical_memory(base, 0x100, iomemtype);

static void omap_tcmi_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

                    omap_tcmi_writefn, mpu);

    cpu_register_physical_memory(base, 0x100, iomemtype);

static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,

                omap_clk clk)

{

                    omap_dpll_writefn, s);

    s->dpll = clk;

    target_phys_addr_t base = omap_l4_attach(ta, 0, 0);

    struct omap_uart_s *s = omap_uart_init(base, irq,

                    fclk, iclk, txdma, rxdma, chr);

                    omap_uart_writefn, s);

    s->ta = ta;

                target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)

{

    int iomemtype[2] = {

    };

    s->clkm.arm_idlect1 = 0x03ff;

    s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);

    omap_mpuio_reset(s);

                    omap_mpuio_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);

    omap_gpio_reset(s);

                    omap_gpio_writefn, s);

    cpu_register_physical_memory(base, 0x1000, iomemtype);

    s->txdrq = dma;

    omap_uwire_reset(s);

                    omap_uwire_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    omap_pwl_reset(s);

                    omap_pwl_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    s->pwt.clk = clk;

    omap_pwt_reset(s);

                    omap_pwt_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

}

    omap_rtc_reset(s);

                    omap_rtc_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);

    omap_mcbsp_reset(s);

                    omap_mcbsp_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    omap_lpg_reset(s);

                    omap_lpg_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)

{

                    omap_mpui_io_writefn, mpu);

    cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);

}

    omap_gp_timer_reset(s);

    omap_gp_timer_clk_setup(s);

                    omap_gp_timer_writefn, s);

    omap_l4_attach(ta, 0, iomemtype);

    struct omap_synctimer_s *s = &mpu->synctimer;

    omap_synctimer_reset(s);

                      omap_synctimer_readfn, omap_synctimer_writefn, s));

}

    s->wkup = wkup;

    s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);

                    omap_gpio_module_writefn, s);

    omap_l4_attach(ta, region, iomemtype);

}

    omap_gpif_reset(s);

                    omap_gpif_top_writefn, s);

    omap_l4_attach(ta, 1, iomemtype);

    }

    omap_mcspi_reset(s);

                    omap_mcspi_writefn, s);

    omap_l4_attach(ta, 0, iomemtype);

#ifdef HAS_AUDIO

    AUD_register_card("OMAP EAC", &s->codec.card);

                    omap_eac_writefn, s);

    omap_l4_attach(ta, 0, iomemtype);

#endif

    s->chr = chr ?: qemu_chr_open("null", "null", NULL);

                    omap_sti_writefn, s);

    omap_l4_attach(ta, 0, iomemtype);

                    omap_sti_fifo_writefn, s);

    cpu_register_physical_memory(channel_base, 0x10000, iomemtype);

static CPUWriteMemoryFunc **omap_l4_io_writew_fn;

static void **omap_l4_io_opaque;

                CPUWriteMemoryFunc **mem_write, void *opaque)

{

    omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;

    omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));

    omap_cpu_io_entry =

                            omap_l4_io_writefn, bus);

# define L4_PAGES	(0xb4000 / TARGET_PAGE_SIZE)

    omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);

    ta->status = 0x00000000;

    ta->control = 0x00000200;	/* XXX 01000200 for L4TAO */

                    omap_l4ta_writefn, ta);

    ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);

void omap_tap_init(struct omap_target_agent_s *ta,

                struct omap_mpu_state_s *mpu)

{

                            omap_tap_readfn, omap_tap_writefn, mpu));

}

    s->mpu = mpu;

    omap_prcm_coldreset(s);

                    omap_prcm_writefn, s);

    omap_l4_attach(ta, 0, iomemtype);

    omap_l4_attach(ta, 1, iomemtype);

    s->mpu = mpu;

    omap_sysctl_reset(s);

                    omap_sysctl_writefn, s);

    omap_l4_attach(ta, 0, iomemtype);

    omap_sdrc_reset(s);

                    omap_sdrc_writefn, s);

    cpu_register_physical_memory(base, 0x1000, iomemtype);

    omap_gpmc_reset(s);

                    omap_gpmc_writefn, s);

    cpu_register_physical_memory(base, 0x1000, iomemtype);

    omap_dma_reset(s->dma);

    omap_dma_clk_update(s, 0, 1);

                    omap_dma_writefn, s);

    cpu_register_physical_memory(base, memsize, iomemtype);

    omap_dma_reset(s->dma);

    omap_dma_clk_update(s, 0, !!s->dma->freq);

                    omap_dma4_writefn, s);

    cpu_register_physical_memory(base, 0x1000, iomemtype);

    s->drq = drq;

    omap_dss_reset(s);

                    omap_diss1_writefn, s);

                    omap_disc1_writefn, s);

                    omap_rfbi1_writefn, s);

                    omap_venc1_writefn, s);

                    omap_im3_writefn, s);

    omap_l4_attach(ta, 0, iomemtype[0]);

    omap_l4_attach(ta, 1, iomemtype[1]);

    s->bus = i2c_init_bus(NULL, "i2c");

    omap_i2c_reset(s);

                    omap_i2c_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    s->bus = i2c_init_bus(NULL, "i2c");

    omap_i2c_reset(s);

                    omap_i2c_writefn, s);

    omap_l4_attach(ta, 0, iomemtype);

    s->emiff_base = emiff_base;

    omap_lcdc_reset(s);

                    omap_lcdc_writefn, s);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    omap_mmc_reset(s);

                    omap_mmc_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    omap_mmc_reset(s);

                    omap_mmc_writefn, s);

    omap_l4_attach(ta, 0, iomemtype);

    cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,

                    (phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM);

    cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,

                    OMAP_CS0_SIZE - flash_size, io);

    cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);

    cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);

    fl_idx = 0;

        cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,

                        (phys_flash = qemu_ram_alloc(flash1_size)) |

                        IO_MEM_ROM);

        cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,

                        OMAP_CS1_SIZE - flash1_size, io);

        }

        fl_idx++;

    } else {

        cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);

    }