Archipelago » qemu

    omap_inth_reset(s);

                    omap_inth_writefn, s);

    cpu_register_physical_memory(base, size, iomemtype);

    omap_inth_reset(s);

                    omap2_inth_writefn, s);

    cpu_register_physical_memory(base, size, iomemtype);

    omap_mpu_timer_reset(s);

    omap_timer_clk_setup(s);

                    omap_mpu_timer_writefn, s);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    omap_wd_timer_reset(s);

    omap_timer_clk_setup(&s->timer);

                    omap_wd_timer_writefn, s);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    omap_os_timer_reset(s);

    omap_timer_clk_setup(&s->timer);

                    omap_os_timer_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

static void omap_ulpd_pm_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

                    omap_ulpd_pm_writefn, mpu);

    cpu_register_physical_memory(base, 0x800, iomemtype);

static void omap_pin_cfg_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

                    omap_pin_cfg_writefn, mpu);

    cpu_register_physical_memory(base, 0x800, iomemtype);

static void omap_id_init(struct omap_mpu_state_s *mpu)

{

                    omap_id_writefn, mpu);

    cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);

    cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);

static void omap_mpui_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

                    omap_mpui_writefn, mpu);

    cpu_register_physical_memory(base, 0x100, iomemtype);

    s->abort = abort_irq;

    omap_tipb_bridge_reset(s);

                    omap_tipb_bridge_writefn, s);

    cpu_register_physical_memory(base, 0x100, iomemtype);

static void omap_tcmi_init(target_phys_addr_t base,

                struct omap_mpu_state_s *mpu)

{

                    omap_tcmi_writefn, mpu);

    cpu_register_physical_memory(base, 0x100, iomemtype);

static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,

                omap_clk clk)

{

                    omap_dpll_writefn, s);

    s->dpll = clk;

    target_phys_addr_t base = omap_l4_attach(ta, 0, 0);

    struct omap_uart_s *s = omap_uart_init(base, irq,

                    fclk, iclk, txdma, rxdma, chr);

                    omap_uart_writefn, s);

    s->ta = ta;

                target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)

{

    int iomemtype[2] = {

    };

    s->clkm.arm_idlect1 = 0x03ff;

    s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);

    omap_mpuio_reset(s);

                    omap_mpuio_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);

    omap_gpio_reset(s);

                    omap_gpio_writefn, s);

    cpu_register_physical_memory(base, 0x1000, iomemtype);

    s->txdrq = dma;

    omap_uwire_reset(s);

                    omap_uwire_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    omap_pwl_reset(s);

                    omap_pwl_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    s->pwt.clk = clk;

    omap_pwt_reset(s);

                    omap_pwt_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

}

    omap_rtc_reset(s);

                    omap_rtc_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);

    omap_mcbsp_reset(s);

                    omap_mcbsp_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

    omap_lpg_reset(s);

                    omap_lpg_writefn, s);

    cpu_register_physical_memory(base, 0x800, iomemtype);

static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)

{

                    omap_mpui_io_writefn, mpu);

    cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);

}