root / target-ppc / op_helper.c @ 1ef59d0a
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1 | 9a64fbe4 | bellard | /*
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2 | 9a64fbe4 | bellard | * PPC emulation helpers for qemu.
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3 | 9a64fbe4 | bellard | *
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4 | 9a64fbe4 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 9a64fbe4 | bellard | *
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6 | 9a64fbe4 | bellard | * This library is free software; you can redistribute it and/or
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7 | 9a64fbe4 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 9a64fbe4 | bellard | * License as published by the Free Software Foundation; either
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9 | 9a64fbe4 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 9a64fbe4 | bellard | *
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11 | 9a64fbe4 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 9a64fbe4 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 9a64fbe4 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 9a64fbe4 | bellard | * Lesser General Public License for more details.
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15 | 9a64fbe4 | bellard | *
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16 | 9a64fbe4 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 9a64fbe4 | bellard | * License along with this library; if not, write to the Free Software
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18 | 9a64fbe4 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 9a64fbe4 | bellard | */
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20 | 9a64fbe4 | bellard | #include <math.h> |
21 | 9a64fbe4 | bellard | #include "exec.h" |
22 | 9a64fbe4 | bellard | |
23 | 9a64fbe4 | bellard | #define MEMSUFFIX _raw
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24 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
25 | a541f297 | bellard | #if !defined(CONFIG_USER_ONLY)
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26 | 9a64fbe4 | bellard | #define MEMSUFFIX _user
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27 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
28 | 9a64fbe4 | bellard | #define MEMSUFFIX _kernel
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29 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
30 | 9a64fbe4 | bellard | #endif
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31 | 9a64fbe4 | bellard | |
32 | 9a64fbe4 | bellard | /*****************************************************************************/
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33 | 9a64fbe4 | bellard | /* Exceptions processing helpers */
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34 | 9a64fbe4 | bellard | void do_queue_exception_err (uint32_t exception, int error_code) |
35 | 9a64fbe4 | bellard | { |
36 | 9a64fbe4 | bellard | /* Queue real PPC exceptions */
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37 | 9a64fbe4 | bellard | if (exception < EXCP_PPC_MAX) {
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38 | 9a64fbe4 | bellard | env->exceptions |= 1 << exception;
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39 | 9a64fbe4 | bellard | env->errors[exception] = error_code; |
40 | 9a64fbe4 | bellard | } else {
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41 | 9a64fbe4 | bellard | /* Preserve compatibility with qemu core */
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42 | 9a64fbe4 | bellard | env->exceptions |= 1;
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43 | 9a64fbe4 | bellard | env->exception_index = exception; |
44 | 9a64fbe4 | bellard | env->error_code = error_code; |
45 | 9a64fbe4 | bellard | } |
46 | 9a64fbe4 | bellard | } |
47 | 9a64fbe4 | bellard | |
48 | 9a64fbe4 | bellard | void do_queue_exception (uint32_t exception)
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49 | 9a64fbe4 | bellard | { |
50 | 9a64fbe4 | bellard | do_queue_exception_err(exception, 0);
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51 | 9a64fbe4 | bellard | } |
52 | 9a64fbe4 | bellard | |
53 | 9a64fbe4 | bellard | void do_check_exception_state (void) |
54 | 9a64fbe4 | bellard | { |
55 | 9a64fbe4 | bellard | if ((env->exceptions & 1) == 1 || check_exception_state(env)) { |
56 | 9a64fbe4 | bellard | env->exceptions &= ~1;
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57 | 9a64fbe4 | bellard | cpu_loop_exit(); |
58 | 9a64fbe4 | bellard | } |
59 | 9a64fbe4 | bellard | } |
60 | 9a64fbe4 | bellard | |
61 | 9a64fbe4 | bellard | /*****************************************************************************/
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62 | 9a64fbe4 | bellard | /* Helpers for "fat" micro operations */
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63 | 9a64fbe4 | bellard | /* Special registers load and store */
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64 | 9a64fbe4 | bellard | void do_load_cr (void) |
65 | 9a64fbe4 | bellard | { |
66 | 9a64fbe4 | bellard | T0 = (env->crf[0] << 28) | |
67 | 9a64fbe4 | bellard | (env->crf[1] << 24) | |
68 | 9a64fbe4 | bellard | (env->crf[2] << 20) | |
69 | 9a64fbe4 | bellard | (env->crf[3] << 16) | |
70 | 9a64fbe4 | bellard | (env->crf[4] << 12) | |
71 | 9a64fbe4 | bellard | (env->crf[5] << 8) | |
72 | 9a64fbe4 | bellard | (env->crf[6] << 4) | |
73 | 9a64fbe4 | bellard | (env->crf[7] << 0); |
74 | 9a64fbe4 | bellard | } |
75 | 9a64fbe4 | bellard | |
76 | 9a64fbe4 | bellard | void do_store_cr (uint32_t mask)
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77 | 9a64fbe4 | bellard | { |
78 | 9a64fbe4 | bellard | int i, sh;
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79 | 9a64fbe4 | bellard | |
80 | 9a64fbe4 | bellard | for (i = 0, sh = 7; i < 8; i++, sh --) { |
81 | 9a64fbe4 | bellard | if (mask & (1 << sh)) |
82 | 9a64fbe4 | bellard | env->crf[i] = (T0 >> (sh * 4)) & 0xF; |
83 | 9a64fbe4 | bellard | } |
84 | 9a64fbe4 | bellard | } |
85 | 9a64fbe4 | bellard | |
86 | 9a64fbe4 | bellard | void do_load_xer (void) |
87 | 9a64fbe4 | bellard | { |
88 | 9a64fbe4 | bellard | T0 = (xer_so << XER_SO) | |
89 | 9a64fbe4 | bellard | (xer_ov << XER_OV) | |
90 | 9a64fbe4 | bellard | (xer_ca << XER_CA) | |
91 | 9a64fbe4 | bellard | (xer_bc << XER_BC); |
92 | 9a64fbe4 | bellard | } |
93 | 9a64fbe4 | bellard | |
94 | 9a64fbe4 | bellard | void do_store_xer (void) |
95 | 9a64fbe4 | bellard | { |
96 | 9a64fbe4 | bellard | xer_so = (T0 >> XER_SO) & 0x01;
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97 | 9a64fbe4 | bellard | xer_ov = (T0 >> XER_OV) & 0x01;
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98 | 9a64fbe4 | bellard | xer_ca = (T0 >> XER_CA) & 0x01;
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99 | 9a64fbe4 | bellard | xer_bc = (T0 >> XER_BC) & 0x1f;
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100 | 9a64fbe4 | bellard | } |
101 | 9a64fbe4 | bellard | |
102 | 9a64fbe4 | bellard | void do_load_msr (void) |
103 | 9a64fbe4 | bellard | { |
104 | 9a64fbe4 | bellard | T0 = (msr_pow << MSR_POW) | |
105 | 9a64fbe4 | bellard | (msr_ile << MSR_ILE) | |
106 | 9a64fbe4 | bellard | (msr_ee << MSR_EE) | |
107 | 9a64fbe4 | bellard | (msr_pr << MSR_PR) | |
108 | 9a64fbe4 | bellard | (msr_fp << MSR_FP) | |
109 | 9a64fbe4 | bellard | (msr_me << MSR_ME) | |
110 | 9a64fbe4 | bellard | (msr_fe0 << MSR_FE0) | |
111 | 9a64fbe4 | bellard | (msr_se << MSR_SE) | |
112 | 9a64fbe4 | bellard | (msr_be << MSR_BE) | |
113 | 9a64fbe4 | bellard | (msr_fe1 << MSR_FE1) | |
114 | 9a64fbe4 | bellard | (msr_ip << MSR_IP) | |
115 | 9a64fbe4 | bellard | (msr_ir << MSR_IR) | |
116 | 9a64fbe4 | bellard | (msr_dr << MSR_DR) | |
117 | 9a64fbe4 | bellard | (msr_ri << MSR_RI) | |
118 | 9a64fbe4 | bellard | (msr_le << MSR_LE); |
119 | 9a64fbe4 | bellard | } |
120 | 9a64fbe4 | bellard | |
121 | 9a64fbe4 | bellard | void do_store_msr (void) |
122 | 9a64fbe4 | bellard | { |
123 | 9a64fbe4 | bellard | if (((T0 >> MSR_IR) & 0x01) != msr_ir || |
124 | a541f297 | bellard | ((T0 >> MSR_DR) & 0x01) != msr_dr) {
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125 | 9a64fbe4 | bellard | /* Flush all tlb when changing translation mode or privilege level */
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126 | 9a64fbe4 | bellard | do_tlbia(); |
127 | 9a64fbe4 | bellard | } |
128 | 9a64fbe4 | bellard | #if 0
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129 | 9a64fbe4 | bellard | if ((T0 >> MSR_IP) & 0x01) {
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130 | 9a64fbe4 | bellard | printf("Halting CPU. Stop emulation\n");
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131 | 9a64fbe4 | bellard | do_queue_exception(EXCP_HLT);
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132 | 9a64fbe4 | bellard | cpu_loop_exit();
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133 | 9a64fbe4 | bellard | }
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134 | 9a64fbe4 | bellard | #endif
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135 | 9a64fbe4 | bellard | msr_pow = (T0 >> MSR_POW) & 0x03;
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136 | 9a64fbe4 | bellard | msr_ile = (T0 >> MSR_ILE) & 0x01;
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137 | 9a64fbe4 | bellard | msr_ee = (T0 >> MSR_EE) & 0x01;
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138 | 9a64fbe4 | bellard | msr_pr = (T0 >> MSR_PR) & 0x01;
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139 | 9a64fbe4 | bellard | msr_fp = (T0 >> MSR_FP) & 0x01;
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140 | 9a64fbe4 | bellard | msr_me = (T0 >> MSR_ME) & 0x01;
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141 | 9a64fbe4 | bellard | msr_fe0 = (T0 >> MSR_FE0) & 0x01;
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142 | 9a64fbe4 | bellard | msr_se = (T0 >> MSR_SE) & 0x01;
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143 | 9a64fbe4 | bellard | msr_be = (T0 >> MSR_BE) & 0x01;
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144 | 9a64fbe4 | bellard | msr_fe1 = (T0 >> MSR_FE1) & 0x01;
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145 | 9a64fbe4 | bellard | msr_ip = (T0 >> MSR_IP) & 0x01;
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146 | 9a64fbe4 | bellard | msr_ir = (T0 >> MSR_IR) & 0x01;
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147 | 9a64fbe4 | bellard | msr_dr = (T0 >> MSR_DR) & 0x01;
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148 | 9a64fbe4 | bellard | msr_ri = (T0 >> MSR_RI) & 0x01;
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149 | 9a64fbe4 | bellard | msr_le = (T0 >> MSR_LE) & 0x01;
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150 | 9a64fbe4 | bellard | } |
151 | 9a64fbe4 | bellard | |
152 | 9a64fbe4 | bellard | /* shift right arithmetic helper */
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153 | 9a64fbe4 | bellard | void do_sraw (void) |
154 | 9a64fbe4 | bellard | { |
155 | 9a64fbe4 | bellard | int32_t ret; |
156 | 9a64fbe4 | bellard | |
157 | 9a64fbe4 | bellard | xer_ca = 0;
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158 | 9a64fbe4 | bellard | if (T1 & 0x20) { |
159 | 9a64fbe4 | bellard | ret = (-1) * (T0 >> 31); |
160 | 9a64fbe4 | bellard | if (ret < 0) |
161 | 9a64fbe4 | bellard | xer_ca = 1;
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162 | 9a64fbe4 | bellard | } else {
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163 | 9a64fbe4 | bellard | ret = (int32_t)T0 >> (T1 & 0x1f);
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164 | 9a64fbe4 | bellard | if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0) |
165 | 9a64fbe4 | bellard | xer_ca = 1;
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166 | 9a64fbe4 | bellard | } |
167 | 9a64fbe4 | bellard | (int32_t)T0 = ret; |
168 | 9a64fbe4 | bellard | } |
169 | 9a64fbe4 | bellard | |
170 | 9a64fbe4 | bellard | /* Floating point operations helpers */
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171 | 9a64fbe4 | bellard | void do_load_fpscr (void) |
172 | 9a64fbe4 | bellard | { |
173 | 9a64fbe4 | bellard | /* The 32 MSB of the target fpr are undefined.
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174 | 9a64fbe4 | bellard | * They'll be zero...
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175 | 9a64fbe4 | bellard | */
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176 | 9a64fbe4 | bellard | union {
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177 | 9a64fbe4 | bellard | double d;
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178 | 9a64fbe4 | bellard | struct {
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179 | 9a64fbe4 | bellard | uint32_t u[2];
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180 | 9a64fbe4 | bellard | } s; |
181 | 9a64fbe4 | bellard | } u; |
182 | 9a64fbe4 | bellard | int i;
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183 | 9a64fbe4 | bellard | |
184 | 9a64fbe4 | bellard | u.s.u[0] = 0; |
185 | 9a64fbe4 | bellard | u.s.u[1] = 0; |
186 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) |
187 | 9a64fbe4 | bellard | u.s.u[1] |= env->fpscr[i] << (4 * i); |
188 | 9a64fbe4 | bellard | FT0 = u.d; |
189 | 9a64fbe4 | bellard | } |
190 | 9a64fbe4 | bellard | |
191 | 9a64fbe4 | bellard | void do_store_fpscr (uint32_t mask)
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192 | 9a64fbe4 | bellard | { |
193 | 9a64fbe4 | bellard | /*
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194 | 9a64fbe4 | bellard | * We use only the 32 LSB of the incoming fpr
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195 | 9a64fbe4 | bellard | */
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196 | 9a64fbe4 | bellard | union {
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197 | 9a64fbe4 | bellard | double d;
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198 | 9a64fbe4 | bellard | struct {
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199 | 9a64fbe4 | bellard | uint32_t u[2];
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200 | 9a64fbe4 | bellard | } s; |
201 | 9a64fbe4 | bellard | } u; |
202 | 9a64fbe4 | bellard | int i;
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203 | 9a64fbe4 | bellard | |
204 | 9a64fbe4 | bellard | u.d = FT0; |
205 | 9a64fbe4 | bellard | if (mask & 0x80) |
206 | 9a64fbe4 | bellard | env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9); |
207 | 9a64fbe4 | bellard | for (i = 1; i < 7; i++) { |
208 | 9a64fbe4 | bellard | if (mask & (1 << (7 - i))) |
209 | 9a64fbe4 | bellard | env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF; |
210 | 9a64fbe4 | bellard | } |
211 | 9a64fbe4 | bellard | /* TODO: update FEX & VX */
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212 | 9a64fbe4 | bellard | /* Set rounding mode */
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213 | 9a64fbe4 | bellard | switch (env->fpscr[0] & 0x3) { |
214 | 9a64fbe4 | bellard | case 0: |
215 | 9a64fbe4 | bellard | /* Best approximation (round to nearest) */
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216 | 9a64fbe4 | bellard | fesetround(FE_TONEAREST); |
217 | 9a64fbe4 | bellard | break;
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218 | 9a64fbe4 | bellard | case 1: |
219 | 9a64fbe4 | bellard | /* Smaller magnitude (round toward zero) */
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220 | 9a64fbe4 | bellard | fesetround(FE_TOWARDZERO); |
221 | 9a64fbe4 | bellard | break;
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222 | 9a64fbe4 | bellard | case 2: |
223 | 9a64fbe4 | bellard | /* Round toward +infinite */
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224 | 9a64fbe4 | bellard | fesetround(FE_UPWARD); |
225 | 9a64fbe4 | bellard | break;
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226 | 9a64fbe4 | bellard | case 3: |
227 | 9a64fbe4 | bellard | /* Round toward -infinite */
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228 | 9a64fbe4 | bellard | fesetround(FE_DOWNWARD); |
229 | 9a64fbe4 | bellard | break;
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230 | 9a64fbe4 | bellard | } |
231 | 9a64fbe4 | bellard | } |
232 | 9a64fbe4 | bellard | |
233 | 9a64fbe4 | bellard | void do_fctiw (void) |
234 | 9a64fbe4 | bellard | { |
235 | 9a64fbe4 | bellard | union {
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236 | 9a64fbe4 | bellard | double d;
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237 | 9a64fbe4 | bellard | uint64_t i; |
238 | 9a64fbe4 | bellard | } *p = (void *)&FT1;
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239 | 9a64fbe4 | bellard | |
240 | 9a64fbe4 | bellard | if (FT0 > (double)0x7FFFFFFF) |
241 | 9a64fbe4 | bellard | p->i = 0x7FFFFFFFULL << 32; |
242 | 9a64fbe4 | bellard | else if (FT0 < -(double)0x80000000) |
243 | 9a64fbe4 | bellard | p->i = 0x80000000ULL << 32; |
244 | 9a64fbe4 | bellard | else
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245 | 9a64fbe4 | bellard | p->i = 0;
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246 | 9a64fbe4 | bellard | p->i |= (uint32_t)FT0; |
247 | 9a64fbe4 | bellard | FT0 = p->d; |
248 | 9a64fbe4 | bellard | } |
249 | 9a64fbe4 | bellard | |
250 | 9a64fbe4 | bellard | void do_fctiwz (void) |
251 | 9a64fbe4 | bellard | { |
252 | 9a64fbe4 | bellard | union {
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253 | 9a64fbe4 | bellard | double d;
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254 | 9a64fbe4 | bellard | uint64_t i; |
255 | 9a64fbe4 | bellard | } *p = (void *)&FT1;
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256 | 9a64fbe4 | bellard | int cround = fegetround();
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257 | 9a64fbe4 | bellard | |
258 | 9a64fbe4 | bellard | fesetround(FE_TOWARDZERO); |
259 | 9a64fbe4 | bellard | if (FT0 > (double)0x7FFFFFFF) |
260 | 9a64fbe4 | bellard | p->i = 0x7FFFFFFFULL << 32; |
261 | 9a64fbe4 | bellard | else if (FT0 < -(double)0x80000000) |
262 | 9a64fbe4 | bellard | p->i = 0x80000000ULL << 32; |
263 | 9a64fbe4 | bellard | else
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264 | 9a64fbe4 | bellard | p->i = 0;
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265 | 9a64fbe4 | bellard | p->i |= (uint32_t)FT0; |
266 | 9a64fbe4 | bellard | FT0 = p->d; |
267 | 9a64fbe4 | bellard | fesetround(cround); |
268 | 9a64fbe4 | bellard | } |
269 | 9a64fbe4 | bellard | |
270 | 1ef59d0a | bellard | void do_fnmadds (void) |
271 | 1ef59d0a | bellard | { |
272 | 1ef59d0a | bellard | FTS0 = -((FTS0 * FTS1) + FTS2); |
273 | 1ef59d0a | bellard | } |
274 | 1ef59d0a | bellard | |
275 | 1ef59d0a | bellard | void do_fnmsubs (void) |
276 | 1ef59d0a | bellard | { |
277 | 1ef59d0a | bellard | FTS0 = -((FTS0 * FTS1) - FTS2); |
278 | 1ef59d0a | bellard | } |
279 | 1ef59d0a | bellard | |
280 | 9a64fbe4 | bellard | void do_fsqrt (void) |
281 | 9a64fbe4 | bellard | { |
282 | 9a64fbe4 | bellard | FT0 = sqrt(FT0); |
283 | 9a64fbe4 | bellard | } |
284 | 9a64fbe4 | bellard | |
285 | 9a64fbe4 | bellard | void do_fsqrts (void) |
286 | 9a64fbe4 | bellard | { |
287 | 9a64fbe4 | bellard | FT0 = (float)sqrt((float)FT0); |
288 | 9a64fbe4 | bellard | } |
289 | 9a64fbe4 | bellard | |
290 | 9a64fbe4 | bellard | void do_fres (void) |
291 | 9a64fbe4 | bellard | { |
292 | 9a64fbe4 | bellard | FT0 = 1.0 / FT0; |
293 | 9a64fbe4 | bellard | } |
294 | 9a64fbe4 | bellard | |
295 | 9a64fbe4 | bellard | void do_fsqrte (void) |
296 | 9a64fbe4 | bellard | { |
297 | 9a64fbe4 | bellard | FT0 = 1.0 / sqrt(FT0); |
298 | 9a64fbe4 | bellard | } |
299 | 9a64fbe4 | bellard | |
300 | 9a64fbe4 | bellard | void do_fsel (void) |
301 | 9a64fbe4 | bellard | { |
302 | 9a64fbe4 | bellard | if (FT0 >= 0) |
303 | 9a64fbe4 | bellard | FT0 = FT2; |
304 | 9a64fbe4 | bellard | else
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305 | 9a64fbe4 | bellard | FT0 = FT1; |
306 | 9a64fbe4 | bellard | } |
307 | 9a64fbe4 | bellard | |
308 | 9a64fbe4 | bellard | void do_fcmpu (void) |
309 | 9a64fbe4 | bellard | { |
310 | 9a64fbe4 | bellard | env->fpscr[4] &= ~0x1; |
311 | 9a64fbe4 | bellard | if (isnan(FT0) || isnan(FT1)) {
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312 | 9a64fbe4 | bellard | T0 = 0x01;
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313 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x1; |
314 | 9a64fbe4 | bellard | env->fpscr[6] |= 0x1; |
315 | 9a64fbe4 | bellard | } else if (FT0 < FT1) { |
316 | 9a64fbe4 | bellard | T0 = 0x08;
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317 | 9a64fbe4 | bellard | } else if (FT0 > FT1) { |
318 | 9a64fbe4 | bellard | T0 = 0x04;
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319 | 9a64fbe4 | bellard | } else {
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320 | 9a64fbe4 | bellard | T0 = 0x02;
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321 | 9a64fbe4 | bellard | } |
322 | 9a64fbe4 | bellard | env->fpscr[3] |= T0;
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323 | 9a64fbe4 | bellard | } |
324 | 9a64fbe4 | bellard | |
325 | 9a64fbe4 | bellard | void do_fcmpo (void) |
326 | 9a64fbe4 | bellard | { |
327 | 9a64fbe4 | bellard | env->fpscr[4] &= ~0x1; |
328 | 9a64fbe4 | bellard | if (isnan(FT0) || isnan(FT1)) {
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329 | 9a64fbe4 | bellard | T0 = 0x01;
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330 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x1; |
331 | 9a64fbe4 | bellard | /* I don't know how to test "quiet" nan... */
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332 | 9a64fbe4 | bellard | if (0 /* || ! quiet_nan(...) */) { |
333 | 9a64fbe4 | bellard | env->fpscr[6] |= 0x1; |
334 | 9a64fbe4 | bellard | if (!(env->fpscr[1] & 0x8)) |
335 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x8; |
336 | 9a64fbe4 | bellard | } else {
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337 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x8; |
338 | 9a64fbe4 | bellard | } |
339 | 9a64fbe4 | bellard | } else if (FT0 < FT1) { |
340 | 9a64fbe4 | bellard | T0 = 0x08;
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341 | 9a64fbe4 | bellard | } else if (FT0 > FT1) { |
342 | 9a64fbe4 | bellard | T0 = 0x04;
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343 | 9a64fbe4 | bellard | } else {
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344 | 9a64fbe4 | bellard | T0 = 0x02;
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345 | 9a64fbe4 | bellard | } |
346 | 9a64fbe4 | bellard | env->fpscr[3] |= T0;
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347 | 9a64fbe4 | bellard | } |
348 | 9a64fbe4 | bellard | |
349 | 9a64fbe4 | bellard | void do_fabs (void) |
350 | 9a64fbe4 | bellard | { |
351 | 9a64fbe4 | bellard | FT0 = fabsl(FT0); |
352 | 9a64fbe4 | bellard | } |
353 | 9a64fbe4 | bellard | |
354 | 9a64fbe4 | bellard | void do_fnabs (void) |
355 | 9a64fbe4 | bellard | { |
356 | 9a64fbe4 | bellard | FT0 = -fabsl(FT0); |
357 | 9a64fbe4 | bellard | } |
358 | 9a64fbe4 | bellard | |
359 | 9a64fbe4 | bellard | /* Instruction cache invalidation helper */
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360 | 985a19d6 | bellard | #define ICACHE_LINE_SIZE 32 |
361 | 985a19d6 | bellard | |
362 | 9a64fbe4 | bellard | void do_icbi (void) |
363 | 9a64fbe4 | bellard | { |
364 | 985a19d6 | bellard | /* Invalidate one cache line */
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365 | 985a19d6 | bellard | T0 &= ~(ICACHE_LINE_SIZE - 1);
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366 | 985a19d6 | bellard | tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE); |
367 | 9a64fbe4 | bellard | } |
368 | 9a64fbe4 | bellard | |
369 | 9a64fbe4 | bellard | /* TLB invalidation helpers */
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370 | 9a64fbe4 | bellard | void do_tlbia (void) |
371 | 9a64fbe4 | bellard | { |
372 | ad081323 | bellard | tlb_flush(env, 1);
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373 | 9a64fbe4 | bellard | } |
374 | 9a64fbe4 | bellard | |
375 | 9a64fbe4 | bellard | void do_tlbie (void) |
376 | 9a64fbe4 | bellard | { |
377 | 9a64fbe4 | bellard | tlb_flush_page(env, T0); |
378 | 9a64fbe4 | bellard | } |
379 | 9a64fbe4 | bellard | |
380 | 9a64fbe4 | bellard | /*****************************************************************************/
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381 | 9a64fbe4 | bellard | /* Special helpers for debug */
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382 | a541f297 | bellard | extern FILE *stdout;
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383 | a541f297 | bellard | |
384 | a541f297 | bellard | void dump_state (void) |
385 | a541f297 | bellard | { |
386 | a541f297 | bellard | cpu_ppc_dump_state(env, stdout, 0);
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387 | a541f297 | bellard | } |
388 | a541f297 | bellard | |
389 | 9a64fbe4 | bellard | void dump_rfi (void) |
390 | 9a64fbe4 | bellard | { |
391 | 9a64fbe4 | bellard | #if 0
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392 | a541f297 | bellard | printf("Return from interrupt %d => 0x%08x\n", pos, env->nip);
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393 | a541f297 | bellard | // cpu_ppc_dump_state(env, stdout, 0);
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394 | 9a64fbe4 | bellard | #endif
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395 | 9a64fbe4 | bellard | } |
396 | 9a64fbe4 | bellard | |
397 | 9a64fbe4 | bellard | void dump_store_sr (int srnum) |
398 | 9a64fbe4 | bellard | { |
399 | 9a64fbe4 | bellard | #if 0
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400 | 9a64fbe4 | bellard | printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
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401 | 9a64fbe4 | bellard | #endif
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402 | 9a64fbe4 | bellard | } |
403 | 9a64fbe4 | bellard | |
404 | 9a64fbe4 | bellard | static void _dump_store_bat (char ID, int ul, int nr) |
405 | 9a64fbe4 | bellard | { |
406 | 9a64fbe4 | bellard | printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
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407 | 9a64fbe4 | bellard | ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip); |
408 | 9a64fbe4 | bellard | } |
409 | 9a64fbe4 | bellard | |
410 | 9a64fbe4 | bellard | void dump_store_ibat (int ul, int nr) |
411 | 9a64fbe4 | bellard | { |
412 | 9a64fbe4 | bellard | _dump_store_bat('I', ul, nr);
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413 | 9a64fbe4 | bellard | } |
414 | 9a64fbe4 | bellard | |
415 | 9a64fbe4 | bellard | void dump_store_dbat (int ul, int nr) |
416 | 9a64fbe4 | bellard | { |
417 | 9a64fbe4 | bellard | _dump_store_bat('D', ul, nr);
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418 | 9a64fbe4 | bellard | } |
419 | 9a64fbe4 | bellard | |
420 | 9a64fbe4 | bellard | void dump_store_tb (int ul) |
421 | 9a64fbe4 | bellard | { |
422 | 9a64fbe4 | bellard | printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0); |
423 | 9a64fbe4 | bellard | } |
424 | 9a64fbe4 | bellard | |
425 | 9a64fbe4 | bellard | void dump_update_tb(uint32_t param)
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426 | 9a64fbe4 | bellard | { |
427 | 9a64fbe4 | bellard | #if 0
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428 | 9a64fbe4 | bellard | printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
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429 | 9a64fbe4 | bellard | #endif
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430 | 9a64fbe4 | bellard | } |