Revision 1f5063fb target-sparc/translate.c

b/target-sparc/translate.c
3515 3515 
                case 0x010: /* VIS I array8 */
3516 3516 
                    gen_movl_reg_T0(rs1);
3517 3517 
                    gen_movl_reg_T1(rs2);
3518 
                    gen_op_array8();
3518 
                    tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3519 
                                       cpu_T[1]);
3519 3520 
                    gen_movl_T0_reg(rd);
3520 3521 
                    break;
3521 3522 
                case 0x012: /* VIS I array16 */
3522 3523 
                    gen_movl_reg_T0(rs1);
3523 3524 
                    gen_movl_reg_T1(rs2);
3524 
                    gen_op_array16();
3525 
                    tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3526 
                                       cpu_T[1]);
3527 
                    tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1);
3525 3528 
                    gen_movl_T0_reg(rd);
3526 3529 
                    break;
3527 3530 
                case 0x014: /* VIS I array32 */
3528 3531 
                    gen_movl_reg_T0(rs1);
3529 3532 
                    gen_movl_reg_T1(rs2);
3530 
                    gen_op_array32();
3533 
                    tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3534 
                                       cpu_T[1]);
3535 
                    tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
3531 3536 
                    gen_movl_T0_reg(rd);
3532 3537 
                    break;
3533 3538 
                case 0x018: /* VIS I alignaddr */
3534 3539 
                    gen_movl_reg_T0(rs1);
3535 3540 
                    gen_movl_reg_T1(rs2);
3536 
                    gen_op_alignaddr();
3541 
                    tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0],
3542 
                                       cpu_T[1]);
3537 3543 
                    gen_movl_T0_reg(rd);
3538 3544 
                    break;
3539 3545 
                case 0x019: /* VIS II bmask */

Also available in: Unified diff