Revision 1f587329 target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 25 | 25 |
Rest of V9 instructions, VIS instructions |
| 26 | 26 |
NPC/PC static optimisations (use JUMP_TB when possible) |
| 27 | 27 |
Optimize synthetic instructions |
| 28 |
128-bit float |
|
| 29 | 28 |
*/ |
| 30 | 29 |
|
| 31 | 30 |
#include <stdarg.h> |
| ... | ... | |
| 93 | 92 |
|
| 94 | 93 |
#ifdef TARGET_SPARC64 |
| 95 | 94 |
#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
| 95 |
#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
|
| 96 | 96 |
#else |
| 97 | 97 |
#define DFPREG(r) (r & 0x1e) |
| 98 |
#define QFPREG(r) (r & 0x1c) |
|
| 98 | 99 |
#endif |
| 99 | 100 |
|
| 100 | 101 |
#ifdef USE_DIRECT_JUMP |
| ... | ... | |
| 351 | 352 |
GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf); |
| 352 | 353 |
GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); |
| 353 | 354 |
|
| 355 |
#if defined(CONFIG_USER_ONLY) |
|
| 356 |
GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf); |
|
| 357 |
GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf); |
|
| 358 |
GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf); |
|
| 359 |
GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf); |
|
| 360 |
#endif |
|
| 361 |
|
|
| 354 | 362 |
/* moves */ |
| 355 | 363 |
#ifdef CONFIG_USER_ONLY |
| 356 | 364 |
#define supervisor(dc) 0 |
| ... | ... | |
| 1060 | 1068 |
gen_op_fcmpd_fcc3, |
| 1061 | 1069 |
}; |
| 1062 | 1070 |
|
| 1071 |
#if defined(CONFIG_USER_ONLY) |
|
| 1072 |
static GenOpFunc * const gen_fcmpq[4] = {
|
|
| 1073 |
gen_op_fcmpq, |
|
| 1074 |
gen_op_fcmpq_fcc1, |
|
| 1075 |
gen_op_fcmpq_fcc2, |
|
| 1076 |
gen_op_fcmpq_fcc3, |
|
| 1077 |
}; |
|
| 1078 |
#endif |
|
| 1079 |
|
|
| 1063 | 1080 |
static GenOpFunc * const gen_fcmpes[4] = {
|
| 1064 | 1081 |
gen_op_fcmpes, |
| 1065 | 1082 |
gen_op_fcmpes_fcc1, |
| ... | ... | |
| 1074 | 1091 |
gen_op_fcmped_fcc3, |
| 1075 | 1092 |
}; |
| 1076 | 1093 |
|
| 1094 |
#if defined(CONFIG_USER_ONLY) |
|
| 1095 |
static GenOpFunc * const gen_fcmpeq[4] = {
|
|
| 1096 |
gen_op_fcmpeq, |
|
| 1097 |
gen_op_fcmpeq_fcc1, |
|
| 1098 |
gen_op_fcmpeq_fcc2, |
|
| 1099 |
gen_op_fcmpeq_fcc3, |
|
| 1100 |
}; |
|
| 1101 |
#endif |
|
| 1077 | 1102 |
#endif |
| 1078 | 1103 |
|
| 1079 | 1104 |
static int gen_trap_ifnofpu(DisasContext * dc) |
| ... | ... | |
| 1484 | 1509 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1485 | 1510 |
break; |
| 1486 | 1511 |
case 0x2b: /* fsqrtq */ |
| 1512 |
#if defined(CONFIG_USER_ONLY) |
|
| 1513 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1514 |
gen_op_fsqrtq(); |
|
| 1515 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1516 |
break; |
|
| 1517 |
#else |
|
| 1487 | 1518 |
goto nfpu_insn; |
| 1519 |
#endif |
|
| 1488 | 1520 |
case 0x41: |
| 1489 | 1521 |
gen_op_load_fpr_FT0(rs1); |
| 1490 | 1522 |
gen_op_load_fpr_FT1(rs2); |
| ... | ... | |
| 1498 | 1530 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1499 | 1531 |
break; |
| 1500 | 1532 |
case 0x43: /* faddq */ |
| 1533 |
#if defined(CONFIG_USER_ONLY) |
|
| 1534 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
|
| 1535 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1536 |
gen_op_faddq(); |
|
| 1537 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1538 |
break; |
|
| 1539 |
#else |
|
| 1501 | 1540 |
goto nfpu_insn; |
| 1541 |
#endif |
|
| 1502 | 1542 |
case 0x45: |
| 1503 | 1543 |
gen_op_load_fpr_FT0(rs1); |
| 1504 | 1544 |
gen_op_load_fpr_FT1(rs2); |
| ... | ... | |
| 1512 | 1552 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1513 | 1553 |
break; |
| 1514 | 1554 |
case 0x47: /* fsubq */ |
| 1555 |
#if defined(CONFIG_USER_ONLY) |
|
| 1556 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
|
| 1557 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1558 |
gen_op_fsubq(); |
|
| 1559 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1560 |
break; |
|
| 1561 |
#else |
|
| 1515 | 1562 |
goto nfpu_insn; |
| 1563 |
#endif |
|
| 1516 | 1564 |
case 0x49: |
| 1517 | 1565 |
gen_op_load_fpr_FT0(rs1); |
| 1518 | 1566 |
gen_op_load_fpr_FT1(rs2); |
| ... | ... | |
| 1526 | 1574 |
gen_op_store_DT0_fpr(rd); |
| 1527 | 1575 |
break; |
| 1528 | 1576 |
case 0x4b: /* fmulq */ |
| 1577 |
#if defined(CONFIG_USER_ONLY) |
|
| 1578 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
|
| 1579 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1580 |
gen_op_fmulq(); |
|
| 1581 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1582 |
break; |
|
| 1583 |
#else |
|
| 1529 | 1584 |
goto nfpu_insn; |
| 1585 |
#endif |
|
| 1530 | 1586 |
case 0x4d: |
| 1531 | 1587 |
gen_op_load_fpr_FT0(rs1); |
| 1532 | 1588 |
gen_op_load_fpr_FT1(rs2); |
| ... | ... | |
| 1540 | 1596 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1541 | 1597 |
break; |
| 1542 | 1598 |
case 0x4f: /* fdivq */ |
| 1599 |
#if defined(CONFIG_USER_ONLY) |
|
| 1600 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
|
| 1601 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1602 |
gen_op_fdivq(); |
|
| 1603 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1604 |
break; |
|
| 1605 |
#else |
|
| 1543 | 1606 |
goto nfpu_insn; |
| 1607 |
#endif |
|
| 1544 | 1608 |
case 0x69: |
| 1545 | 1609 |
gen_op_load_fpr_FT0(rs1); |
| 1546 | 1610 |
gen_op_load_fpr_FT1(rs2); |
| ... | ... | |
| 1548 | 1612 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1549 | 1613 |
break; |
| 1550 | 1614 |
case 0x6e: /* fdmulq */ |
| 1615 |
#if defined(CONFIG_USER_ONLY) |
|
| 1616 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
|
| 1617 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
|
| 1618 |
gen_op_fdmulq(); |
|
| 1619 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1620 |
break; |
|
| 1621 |
#else |
|
| 1551 | 1622 |
goto nfpu_insn; |
| 1623 |
#endif |
|
| 1552 | 1624 |
case 0xc4: |
| 1553 | 1625 |
gen_op_load_fpr_FT1(rs2); |
| 1554 | 1626 |
gen_op_fitos(); |
| ... | ... | |
| 1560 | 1632 |
gen_op_store_FT0_fpr(rd); |
| 1561 | 1633 |
break; |
| 1562 | 1634 |
case 0xc7: /* fqtos */ |
| 1635 |
#if defined(CONFIG_USER_ONLY) |
|
| 1636 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1637 |
gen_op_fqtos(); |
|
| 1638 |
gen_op_store_FT0_fpr(rd); |
|
| 1639 |
break; |
|
| 1640 |
#else |
|
| 1563 | 1641 |
goto nfpu_insn; |
| 1642 |
#endif |
|
| 1564 | 1643 |
case 0xc8: |
| 1565 | 1644 |
gen_op_load_fpr_FT1(rs2); |
| 1566 | 1645 |
gen_op_fitod(); |
| ... | ... | |
| 1572 | 1651 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1573 | 1652 |
break; |
| 1574 | 1653 |
case 0xcb: /* fqtod */ |
| 1654 |
#if defined(CONFIG_USER_ONLY) |
|
| 1655 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1656 |
gen_op_fqtod(); |
|
| 1657 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
|
| 1658 |
break; |
|
| 1659 |
#else |
|
| 1575 | 1660 |
goto nfpu_insn; |
| 1661 |
#endif |
|
| 1576 | 1662 |
case 0xcc: /* fitoq */ |
| 1663 |
#if defined(CONFIG_USER_ONLY) |
|
| 1664 |
gen_op_load_fpr_FT1(rs2); |
|
| 1665 |
gen_op_fitoq(); |
|
| 1666 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1667 |
break; |
|
| 1668 |
#else |
|
| 1577 | 1669 |
goto nfpu_insn; |
| 1670 |
#endif |
|
| 1578 | 1671 |
case 0xcd: /* fstoq */ |
| 1672 |
#if defined(CONFIG_USER_ONLY) |
|
| 1673 |
gen_op_load_fpr_FT1(rs2); |
|
| 1674 |
gen_op_fstoq(); |
|
| 1675 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1676 |
break; |
|
| 1677 |
#else |
|
| 1579 | 1678 |
goto nfpu_insn; |
| 1679 |
#endif |
|
| 1580 | 1680 |
case 0xce: /* fdtoq */ |
| 1681 |
#if defined(CONFIG_USER_ONLY) |
|
| 1682 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
|
| 1683 |
gen_op_fdtoq(); |
|
| 1684 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1685 |
break; |
|
| 1686 |
#else |
|
| 1581 | 1687 |
goto nfpu_insn; |
| 1688 |
#endif |
|
| 1582 | 1689 |
case 0xd1: |
| 1583 | 1690 |
gen_op_load_fpr_FT1(rs2); |
| 1584 | 1691 |
gen_op_fstoi(); |
| ... | ... | |
| 1590 | 1697 |
gen_op_store_FT0_fpr(rd); |
| 1591 | 1698 |
break; |
| 1592 | 1699 |
case 0xd3: /* fqtoi */ |
| 1700 |
#if defined(CONFIG_USER_ONLY) |
|
| 1701 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1702 |
gen_op_fqtoi(); |
|
| 1703 |
gen_op_store_FT0_fpr(rd); |
|
| 1704 |
break; |
|
| 1705 |
#else |
|
| 1593 | 1706 |
goto nfpu_insn; |
| 1707 |
#endif |
|
| 1594 | 1708 |
#ifdef TARGET_SPARC64 |
| 1595 | 1709 |
case 0x2: /* V9 fmovd */ |
| 1596 | 1710 |
gen_op_load_fpr_DT0(DFPREG(rs2)); |
| 1597 | 1711 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1598 | 1712 |
break; |
| 1713 |
case 0x3: /* V9 fmovq */ |
|
| 1714 |
#if defined(CONFIG_USER_ONLY) |
|
| 1715 |
gen_op_load_fpr_QT0(QFPREG(rs2)); |
|
| 1716 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1717 |
break; |
|
| 1718 |
#else |
|
| 1719 |
goto nfpu_insn; |
|
| 1720 |
#endif |
|
| 1599 | 1721 |
case 0x6: /* V9 fnegd */ |
| 1600 | 1722 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 1601 | 1723 |
gen_op_fnegd(); |
| 1602 | 1724 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1603 | 1725 |
break; |
| 1726 |
case 0x7: /* V9 fnegq */ |
|
| 1727 |
#if defined(CONFIG_USER_ONLY) |
|
| 1728 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1729 |
gen_op_fnegq(); |
|
| 1730 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1731 |
break; |
|
| 1732 |
#else |
|
| 1733 |
goto nfpu_insn; |
|
| 1734 |
#endif |
|
| 1604 | 1735 |
case 0xa: /* V9 fabsd */ |
| 1605 | 1736 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 1606 | 1737 |
gen_op_fabsd(); |
| 1607 | 1738 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1608 | 1739 |
break; |
| 1740 |
case 0xb: /* V9 fabsq */ |
|
| 1741 |
#if defined(CONFIG_USER_ONLY) |
|
| 1742 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1743 |
gen_op_fabsq(); |
|
| 1744 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1745 |
break; |
|
| 1746 |
#else |
|
| 1747 |
goto nfpu_insn; |
|
| 1748 |
#endif |
|
| 1609 | 1749 |
case 0x81: /* V9 fstox */ |
| 1610 | 1750 |
gen_op_load_fpr_FT1(rs2); |
| 1611 | 1751 |
gen_op_fstox(); |
| ... | ... | |
| 1616 | 1756 |
gen_op_fdtox(); |
| 1617 | 1757 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1618 | 1758 |
break; |
| 1759 |
case 0x83: /* V9 fqtox */ |
|
| 1760 |
#if defined(CONFIG_USER_ONLY) |
|
| 1761 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1762 |
gen_op_fqtox(); |
|
| 1763 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
|
| 1764 |
break; |
|
| 1765 |
#else |
|
| 1766 |
goto nfpu_insn; |
|
| 1767 |
#endif |
|
| 1619 | 1768 |
case 0x84: /* V9 fxtos */ |
| 1620 | 1769 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 1621 | 1770 |
gen_op_fxtos(); |
| ... | ... | |
| 1626 | 1775 |
gen_op_fxtod(); |
| 1627 | 1776 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 1628 | 1777 |
break; |
| 1629 |
case 0x3: /* V9 fmovq */ |
|
| 1630 |
case 0x7: /* V9 fnegq */ |
|
| 1631 |
case 0xb: /* V9 fabsq */ |
|
| 1632 |
case 0x83: /* V9 fqtox */ |
|
| 1633 | 1778 |
case 0x8c: /* V9 fxtoq */ |
| 1779 |
#if defined(CONFIG_USER_ONLY) |
|
| 1780 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
|
| 1781 |
gen_op_fxtoq(); |
|
| 1782 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1783 |
break; |
|
| 1784 |
#else |
|
| 1634 | 1785 |
goto nfpu_insn; |
| 1635 | 1786 |
#endif |
| 1787 |
#endif |
|
| 1636 | 1788 |
default: |
| 1637 | 1789 |
goto illegal_insn; |
| 1638 | 1790 |
} |
| ... | ... | |
| 1670 | 1822 |
gen_op_store_DT0_fpr(rd); |
| 1671 | 1823 |
break; |
| 1672 | 1824 |
} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
|
| 1825 |
#if defined(CONFIG_USER_ONLY) |
|
| 1826 |
cond = GET_FIELD_SP(insn, 14, 17); |
|
| 1827 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 1828 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1829 |
flush_T2(dc); |
|
| 1830 |
rs1 = GET_FIELD(insn, 13, 17); |
|
| 1831 |
gen_movl_reg_T0(rs1); |
|
| 1832 |
gen_cond_reg(cond); |
|
| 1833 |
gen_op_fmovq_cc(); |
|
| 1834 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1835 |
break; |
|
| 1836 |
#else |
|
| 1673 | 1837 |
goto nfpu_insn; |
| 1838 |
#endif |
|
| 1674 | 1839 |
} |
| 1675 | 1840 |
#endif |
| 1676 | 1841 |
switch (xop) {
|
| ... | ... | |
| 1694 | 1859 |
gen_op_store_DT0_fpr(rd); |
| 1695 | 1860 |
break; |
| 1696 | 1861 |
case 0x003: /* V9 fmovqcc %fcc0 */ |
| 1862 |
#if defined(CONFIG_USER_ONLY) |
|
| 1863 |
cond = GET_FIELD_SP(insn, 14, 17); |
|
| 1864 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 1865 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1866 |
flush_T2(dc); |
|
| 1867 |
gen_fcond[0][cond](); |
|
| 1868 |
gen_op_fmovq_cc(); |
|
| 1869 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1870 |
break; |
|
| 1871 |
#else |
|
| 1697 | 1872 |
goto nfpu_insn; |
| 1873 |
#endif |
|
| 1698 | 1874 |
case 0x041: /* V9 fmovscc %fcc1 */ |
| 1699 | 1875 |
cond = GET_FIELD_SP(insn, 14, 17); |
| 1700 | 1876 |
gen_op_load_fpr_FT0(rd); |
| ... | ... | |
| 1714 | 1890 |
gen_op_store_DT0_fpr(rd); |
| 1715 | 1891 |
break; |
| 1716 | 1892 |
case 0x043: /* V9 fmovqcc %fcc1 */ |
| 1893 |
#if defined(CONFIG_USER_ONLY) |
|
| 1894 |
cond = GET_FIELD_SP(insn, 14, 17); |
|
| 1895 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 1896 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1897 |
flush_T2(dc); |
|
| 1898 |
gen_fcond[1][cond](); |
|
| 1899 |
gen_op_fmovq_cc(); |
|
| 1900 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1901 |
break; |
|
| 1902 |
#else |
|
| 1717 | 1903 |
goto nfpu_insn; |
| 1904 |
#endif |
|
| 1718 | 1905 |
case 0x081: /* V9 fmovscc %fcc2 */ |
| 1719 | 1906 |
cond = GET_FIELD_SP(insn, 14, 17); |
| 1720 | 1907 |
gen_op_load_fpr_FT0(rd); |
| ... | ... | |
| 1734 | 1921 |
gen_op_store_DT0_fpr(rd); |
| 1735 | 1922 |
break; |
| 1736 | 1923 |
case 0x083: /* V9 fmovqcc %fcc2 */ |
| 1924 |
#if defined(CONFIG_USER_ONLY) |
|
| 1925 |
cond = GET_FIELD_SP(insn, 14, 17); |
|
| 1926 |
gen_op_load_fpr_QT0(rd); |
|
| 1927 |
gen_op_load_fpr_QT1(rs2); |
|
| 1928 |
flush_T2(dc); |
|
| 1929 |
gen_fcond[2][cond](); |
|
| 1930 |
gen_op_fmovq_cc(); |
|
| 1931 |
gen_op_store_QT0_fpr(rd); |
|
| 1932 |
break; |
|
| 1933 |
#else |
|
| 1737 | 1934 |
goto nfpu_insn; |
| 1935 |
#endif |
|
| 1738 | 1936 |
case 0x0c1: /* V9 fmovscc %fcc3 */ |
| 1739 | 1937 |
cond = GET_FIELD_SP(insn, 14, 17); |
| 1740 | 1938 |
gen_op_load_fpr_FT0(rd); |
| ... | ... | |
| 1754 | 1952 |
gen_op_store_DT0_fpr(rd); |
| 1755 | 1953 |
break; |
| 1756 | 1954 |
case 0x0c3: /* V9 fmovqcc %fcc3 */ |
| 1955 |
#if defined(CONFIG_USER_ONLY) |
|
| 1956 |
cond = GET_FIELD_SP(insn, 14, 17); |
|
| 1957 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 1958 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 1959 |
flush_T2(dc); |
|
| 1960 |
gen_fcond[3][cond](); |
|
| 1961 |
gen_op_fmovq_cc(); |
|
| 1962 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 1963 |
break; |
|
| 1964 |
#else |
|
| 1757 | 1965 |
goto nfpu_insn; |
| 1966 |
#endif |
|
| 1758 | 1967 |
case 0x101: /* V9 fmovscc %icc */ |
| 1759 | 1968 |
cond = GET_FIELD_SP(insn, 14, 17); |
| 1760 | 1969 |
gen_op_load_fpr_FT0(rd); |
| ... | ... | |
| 1774 | 1983 |
gen_op_store_DT0_fpr(rd); |
| 1775 | 1984 |
break; |
| 1776 | 1985 |
case 0x103: /* V9 fmovqcc %icc */ |
| 1986 |
#if defined(CONFIG_USER_ONLY) |
|
| 1987 |
cond = GET_FIELD_SP(insn, 14, 17); |
|
| 1988 |
gen_op_load_fpr_QT0(rd); |
|
| 1989 |
gen_op_load_fpr_QT1(rs2); |
|
| 1990 |
flush_T2(dc); |
|
| 1991 |
gen_cond[0][cond](); |
|
| 1992 |
gen_op_fmovq_cc(); |
|
| 1993 |
gen_op_store_QT0_fpr(rd); |
|
| 1994 |
break; |
|
| 1995 |
#else |
|
| 1777 | 1996 |
goto nfpu_insn; |
| 1997 |
#endif |
|
| 1778 | 1998 |
case 0x181: /* V9 fmovscc %xcc */ |
| 1779 | 1999 |
cond = GET_FIELD_SP(insn, 14, 17); |
| 1780 | 2000 |
gen_op_load_fpr_FT0(rd); |
| ... | ... | |
| 1794 | 2014 |
gen_op_store_DT0_fpr(rd); |
| 1795 | 2015 |
break; |
| 1796 | 2016 |
case 0x183: /* V9 fmovqcc %xcc */ |
| 2017 |
#if defined(CONFIG_USER_ONLY) |
|
| 2018 |
cond = GET_FIELD_SP(insn, 14, 17); |
|
| 2019 |
gen_op_load_fpr_QT0(rd); |
|
| 2020 |
gen_op_load_fpr_QT1(rs2); |
|
| 2021 |
flush_T2(dc); |
|
| 2022 |
gen_cond[1][cond](); |
|
| 2023 |
gen_op_fmovq_cc(); |
|
| 2024 |
gen_op_store_QT0_fpr(rd); |
|
| 2025 |
break; |
|
| 2026 |
#else |
|
| 1797 | 2027 |
goto nfpu_insn; |
| 1798 | 2028 |
#endif |
| 1799 |
case 0x51: /* V9 %fcc */ |
|
| 2029 |
#endif |
|
| 2030 |
case 0x51: /* fcmps, V9 %fcc */ |
|
| 1800 | 2031 |
gen_op_load_fpr_FT0(rs1); |
| 1801 | 2032 |
gen_op_load_fpr_FT1(rs2); |
| 1802 | 2033 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 1805 | 2036 |
gen_op_fcmps(); |
| 1806 | 2037 |
#endif |
| 1807 | 2038 |
break; |
| 1808 |
case 0x52: /* V9 %fcc */ |
|
| 2039 |
case 0x52: /* fcmpd, V9 %fcc */
|
|
| 1809 | 2040 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 1810 | 2041 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 1811 | 2042 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 1814 | 2045 |
gen_op_fcmpd(); |
| 1815 | 2046 |
#endif |
| 1816 | 2047 |
break; |
| 1817 |
case 0x53: /* fcmpq */ |
|
| 2048 |
case 0x53: /* fcmpq, V9 %fcc */ |
|
| 2049 |
#if defined(CONFIG_USER_ONLY) |
|
| 2050 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
|
| 2051 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 2052 |
#ifdef TARGET_SPARC64 |
|
| 2053 |
gen_fcmpq[rd & 3](); |
|
| 2054 |
#else |
|
| 2055 |
gen_op_fcmpq(); |
|
| 2056 |
#endif |
|
| 2057 |
break; |
|
| 2058 |
#else /* !defined(CONFIG_USER_ONLY) */ |
|
| 1818 | 2059 |
goto nfpu_insn; |
| 2060 |
#endif |
|
| 1819 | 2061 |
case 0x55: /* fcmpes, V9 %fcc */ |
| 1820 | 2062 |
gen_op_load_fpr_FT0(rs1); |
| 1821 | 2063 |
gen_op_load_fpr_FT1(rs2); |
| ... | ... | |
| 1834 | 2076 |
gen_op_fcmped(); |
| 1835 | 2077 |
#endif |
| 1836 | 2078 |
break; |
| 1837 |
case 0x57: /* fcmpeq */ |
|
| 2079 |
case 0x57: /* fcmpeq, V9 %fcc */ |
|
| 2080 |
#if defined(CONFIG_USER_ONLY) |
|
| 2081 |
gen_op_load_fpr_QT0(QFPREG(rs1)); |
|
| 2082 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
|
| 2083 |
#ifdef TARGET_SPARC64 |
|
| 2084 |
gen_fcmpeq[rd & 3](); |
|
| 2085 |
#else |
|
| 2086 |
gen_op_fcmpeq(); |
|
| 2087 |
#endif |
|
| 2088 |
break; |
|
| 2089 |
#else/* !defined(CONFIG_USER_ONLY) */ |
|
| 1838 | 2090 |
goto nfpu_insn; |
| 2091 |
#endif |
|
| 1839 | 2092 |
default: |
| 1840 | 2093 |
goto illegal_insn; |
| 1841 | 2094 |
} |
| ... | ... | |
| 3095 | 3348 |
case 0x3d: /* V9 prefetcha, no effect */ |
| 3096 | 3349 |
goto skip_move; |
| 3097 | 3350 |
case 0x32: /* V9 ldqfa */ |
| 3351 |
#if defined(CONFIG_USER_ONLY) |
|
| 3352 |
gen_op_check_align_T0_3(); |
|
| 3353 |
gen_ldf_asi(insn, 16); |
|
| 3354 |
goto skip_move; |
|
| 3355 |
#else |
|
| 3098 | 3356 |
goto nfpu_insn; |
| 3099 | 3357 |
#endif |
| 3358 |
#endif |
|
| 3100 | 3359 |
default: |
| 3101 | 3360 |
goto illegal_insn; |
| 3102 | 3361 |
} |
| ... | ... | |
| 3119 | 3378 |
gen_op_ldfsr(); |
| 3120 | 3379 |
break; |
| 3121 | 3380 |
case 0x22: /* load quad fpreg */ |
| 3381 |
#if defined(CONFIG_USER_ONLY) |
|
| 3382 |
gen_op_check_align_T0_7(); |
|
| 3383 |
gen_op_ldst(ldqf); |
|
| 3384 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 3385 |
break; |
|
| 3386 |
#else |
|
| 3122 | 3387 |
goto nfpu_insn; |
| 3388 |
#endif |
|
| 3123 | 3389 |
case 0x23: /* load double fpreg */ |
| 3124 | 3390 |
gen_op_check_align_T0_7(); |
| 3125 | 3391 |
gen_op_ldst(lddf); |
| ... | ... | |
| 3225 | 3491 |
gen_op_stfsr(); |
| 3226 | 3492 |
gen_op_ldst(stf); |
| 3227 | 3493 |
break; |
| 3228 |
#if !defined(CONFIG_USER_ONLY) |
|
| 3229 |
case 0x26: /* stdfq */ |
|
| 3494 |
case 0x26: |
|
| 3495 |
#ifdef TARGET_SPARC64 |
|
| 3496 |
#if defined(CONFIG_USER_ONLY) |
|
| 3497 |
/* V9 stqf, store quad fpreg */ |
|
| 3498 |
gen_op_check_align_T0_7(); |
|
| 3499 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 3500 |
gen_op_ldst(stqf); |
|
| 3501 |
break; |
|
| 3502 |
#else |
|
| 3503 |
goto nfpu_insn; |
|
| 3504 |
#endif |
|
| 3505 |
#else /* !TARGET_SPARC64 */ |
|
| 3506 |
/* stdfq, store floating point queue */ |
|
| 3507 |
#if defined(CONFIG_USER_ONLY) |
|
| 3508 |
goto illegal_insn; |
|
| 3509 |
#else |
|
| 3230 | 3510 |
if (!supervisor(dc)) |
| 3231 | 3511 |
goto priv_insn; |
| 3232 | 3512 |
if (gen_trap_ifnofpu(dc)) |
| 3233 | 3513 |
goto jmp_insn; |
| 3234 | 3514 |
goto nfq_insn; |
| 3235 | 3515 |
#endif |
| 3516 |
#endif |
|
| 3236 | 3517 |
case 0x27: |
| 3237 | 3518 |
gen_op_check_align_T0_7(); |
| 3238 | 3519 |
gen_op_load_fpr_DT0(DFPREG(rd)); |
| ... | ... | |
| 3249 | 3530 |
gen_op_load_fpr_FT0(rd); |
| 3250 | 3531 |
gen_stf_asi(insn, 4); |
| 3251 | 3532 |
break; |
| 3533 |
case 0x36: /* V9 stqfa */ |
|
| 3534 |
#if defined(CONFIG_USER_ONLY) |
|
| 3535 |
gen_op_check_align_T0_7(); |
|
| 3536 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 3537 |
gen_stf_asi(insn, 16); |
|
| 3538 |
break; |
|
| 3539 |
#else |
|
| 3540 |
goto nfpu_insn; |
|
| 3541 |
#endif |
|
| 3252 | 3542 |
case 0x37: /* V9 stdfa */ |
| 3253 | 3543 |
gen_op_check_align_T0_3(); |
| 3254 | 3544 |
gen_op_load_fpr_DT0(DFPREG(rd)); |
| ... | ... | |
| 3268 | 3558 |
gen_casx_asi(insn); |
| 3269 | 3559 |
gen_movl_T1_reg(rd); |
| 3270 | 3560 |
break; |
| 3271 |
case 0x36: /* V9 stqfa */ |
|
| 3272 |
goto nfpu_insn; |
|
| 3273 | 3561 |
#else |
| 3274 | 3562 |
case 0x34: /* stc */ |
| 3275 | 3563 |
case 0x35: /* stcsr */ |
| ... | ... | |
| 3311 | 3599 |
gen_op_exception(TT_PRIV_INSN); |
| 3312 | 3600 |
dc->is_br = 1; |
| 3313 | 3601 |
return; |
| 3314 |
#endif |
|
| 3315 | 3602 |
nfpu_insn: |
| 3316 | 3603 |
save_state(dc); |
| 3317 | 3604 |
gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
| 3318 | 3605 |
dc->is_br = 1; |
| 3319 | 3606 |
return; |
| 3320 |
#if !defined(CONFIG_USER_ONLY)
|
|
| 3607 |
#ifndef TARGET_SPARC64
|
|
| 3321 | 3608 |
nfq_insn: |
| 3322 | 3609 |
save_state(dc); |
| 3323 | 3610 |
gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
| 3324 | 3611 |
dc->is_br = 1; |
| 3325 | 3612 |
return; |
| 3326 | 3613 |
#endif |
| 3614 |
#endif |
|
| 3327 | 3615 |
#ifndef TARGET_SPARC64 |
| 3328 | 3616 |
ncp_insn: |
| 3329 | 3617 |
save_state(dc); |
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