Revision 1f62d938 hw/pci.c
| b/hw/pci.c | ||
|---|---|---|
| 255 | 255 |
addr = address; |
| 256 | 256 |
for(i = 0; i < len; i++) {
|
| 257 | 257 |
/* default read/write accesses */ |
| 258 |
switch(addr) {
|
|
| 258 |
switch(d->config[0x0e]) {
|
|
| 259 | 259 |
case 0x00: |
| 260 |
case 0x01: |
|
| 261 |
case 0x02: |
|
| 262 |
case 0x03: |
|
| 263 |
case 0x08: |
|
| 264 |
case 0x09: |
|
| 265 |
case 0x0a: |
|
| 266 |
case 0x0b: |
|
| 267 |
case 0x0e: |
|
| 268 |
case 0x3d: |
|
| 269 |
can_write = 0; |
|
| 260 |
case 0x80: |
|
| 261 |
switch(addr) {
|
|
| 262 |
case 0x00: |
|
| 263 |
case 0x01: |
|
| 264 |
case 0x02: |
|
| 265 |
case 0x03: |
|
| 266 |
case 0x08: |
|
| 267 |
case 0x09: |
|
| 268 |
case 0x0a: |
|
| 269 |
case 0x0b: |
|
| 270 |
case 0x0e: |
|
| 271 |
case 0x10 ... 0x27: /* base */ |
|
| 272 |
case 0x30 ... 0x33: /* rom */ |
|
| 273 |
case 0x3d: |
|
| 274 |
can_write = 0; |
|
| 275 |
break; |
|
| 276 |
default: |
|
| 277 |
can_write = 1; |
|
| 278 |
break; |
|
| 279 |
} |
|
| 270 | 280 |
break; |
| 271 | 281 |
default: |
| 272 |
can_write = 1; |
|
| 282 |
case 0x01: |
|
| 283 |
switch(addr) {
|
|
| 284 |
case 0x00: |
|
| 285 |
case 0x01: |
|
| 286 |
case 0x02: |
|
| 287 |
case 0x03: |
|
| 288 |
case 0x08: |
|
| 289 |
case 0x09: |
|
| 290 |
case 0x0a: |
|
| 291 |
case 0x0b: |
|
| 292 |
case 0x0e: |
|
| 293 |
case 0x38 ... 0x3b: /* rom */ |
|
| 294 |
case 0x3d: |
|
| 295 |
can_write = 0; |
|
| 296 |
break; |
|
| 297 |
default: |
|
| 298 |
can_write = 1; |
|
| 299 |
break; |
|
| 300 |
} |
|
| 273 | 301 |
break; |
| 274 | 302 |
} |
| 275 | 303 |
if (can_write) {
|
| ... | ... | |
| 986 | 1014 |
int i, pin, pic_irq, vendor_id, device_id; |
| 987 | 1015 |
|
| 988 | 1016 |
class = pci_config_readw(d, PCI_CLASS_DEVICE); |
| 1017 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
|
| 1018 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
|
| 989 | 1019 |
switch(class) {
|
| 990 | 1020 |
case 0x0101: |
| 991 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
|
| 992 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
|
| 993 | 1021 |
if (vendor_id == 0x8086 && device_id == 0x7010) {
|
| 994 | 1022 |
/* PIIX3 IDE */ |
| 995 | 1023 |
pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO); |
| ... | ... | |
| 1006 | 1034 |
/* VGA: map frame buffer to default Bochs VBE address */ |
| 1007 | 1035 |
pci_set_io_region_addr(d, 0, 0xE0000000); |
| 1008 | 1036 |
break; |
| 1037 |
case 0xff00: |
|
| 1038 |
if (vendor_id == 0x0106b && device_id == 0x0017) {
|
|
| 1039 |
/* macio bridge */ |
|
| 1040 |
pci_set_io_region_addr(d, 0, 0x80800000); |
|
| 1041 |
} |
|
| 1042 |
break; |
|
| 1009 | 1043 |
default: |
| 1010 | 1044 |
/* default memory mappings */ |
| 1011 | 1045 |
for(i = 0; i < PCI_NUM_REGIONS; i++) {
|
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