Revision 1fc7bf6e
| b/target-mips/translate.c | ||
|---|---|---|
| 3484 | 3484 |
default: |
| 3485 | 3485 |
goto die; |
| 3486 | 3486 |
} |
| 3487 |
/* Stop translation as we may have switched the execution mode */ |
|
| 3488 |
ctx->bstate = BS_STOP; |
|
| 3489 | 3487 |
break; |
| 3490 | 3488 |
case 10: |
| 3491 | 3489 |
switch (sel) {
|
| ... | ... | |
| 3507 | 3505 |
default: |
| 3508 | 3506 |
goto die; |
| 3509 | 3507 |
} |
| 3510 |
/* Stop translation as we may have switched the execution mode */ |
|
| 3511 |
ctx->bstate = BS_STOP; |
|
| 3512 | 3508 |
break; |
| 3513 | 3509 |
case 12: |
| 3514 | 3510 |
switch (sel) {
|
| ... | ... | |
| 3553 | 3549 |
default: |
| 3554 | 3550 |
goto die; |
| 3555 | 3551 |
} |
| 3556 |
/* Stop translation as we may have switched the execution mode */ |
|
| 3557 |
ctx->bstate = BS_STOP; |
|
| 3558 | 3552 |
break; |
| 3559 | 3553 |
case 14: |
| 3560 | 3554 |
switch (sel) {
|
| ... | ... | |
| 4756 | 4750 |
ctx->bstate = BS_STOP; |
| 4757 | 4751 |
break; |
| 4758 | 4752 |
case 1: |
| 4759 |
/* ignored */ |
|
| 4753 |
/* ignored, read only */
|
|
| 4760 | 4754 |
rn = "Config1"; |
| 4761 | 4755 |
break; |
| 4762 | 4756 |
case 2: |
| ... | ... | |
| 5350 | 5344 |
/* Treat as NOP. */ |
| 5351 | 5345 |
return; |
| 5352 | 5346 |
} |
| 5353 |
{
|
|
| 5354 |
TCGv t0 = tcg_temp_local_new(); |
|
| 5355 |
|
|
| 5356 |
gen_mfc0(env, ctx, t0, rd, ctx->opcode & 0x7); |
|
| 5357 |
gen_store_gpr(t0, rt); |
|
| 5358 |
tcg_temp_free(t0); |
|
| 5359 |
} |
|
| 5347 |
gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); |
|
| 5360 | 5348 |
opn = "mfc0"; |
| 5361 | 5349 |
break; |
| 5362 | 5350 |
case OPC_MTC0: |
| 5363 | 5351 |
{
|
| 5364 |
TCGv t0 = tcg_temp_local_new();
|
|
| 5352 |
TCGv t0 = tcg_temp_new(); |
|
| 5365 | 5353 |
|
| 5366 | 5354 |
gen_load_gpr(t0, rt); |
| 5367 |
save_cpu_state(ctx, 1); |
|
| 5368 | 5355 |
gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7); |
| 5369 | 5356 |
tcg_temp_free(t0); |
| 5370 | 5357 |
} |
| ... | ... | |
| 5377 | 5364 |
/* Treat as NOP. */ |
| 5378 | 5365 |
return; |
| 5379 | 5366 |
} |
| 5380 |
{
|
|
| 5381 |
TCGv t0 = tcg_temp_local_new(); |
|
| 5382 |
|
|
| 5383 |
gen_dmfc0(env, ctx, t0, rd, ctx->opcode & 0x7); |
|
| 5384 |
gen_store_gpr(t0, rt); |
|
| 5385 |
tcg_temp_free(t0); |
|
| 5386 |
} |
|
| 5367 |
gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); |
|
| 5387 | 5368 |
opn = "dmfc0"; |
| 5388 | 5369 |
break; |
| 5389 | 5370 |
case OPC_DMTC0: |
| 5390 | 5371 |
check_insn(env, ctx, ISA_MIPS3); |
| 5391 | 5372 |
{
|
| 5392 |
TCGv t0 = tcg_temp_local_new();
|
|
| 5373 |
TCGv t0 = tcg_temp_new(); |
|
| 5393 | 5374 |
|
| 5394 | 5375 |
gen_load_gpr(t0, rt); |
| 5395 |
save_cpu_state(ctx, 1); |
|
| 5396 | 5376 |
gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7); |
| 5397 | 5377 |
tcg_temp_free(t0); |
| 5398 | 5378 |
} |
| ... | ... | |
| 5442 | 5422 |
case OPC_ERET: |
| 5443 | 5423 |
opn = "eret"; |
| 5444 | 5424 |
check_insn(env, ctx, ISA_MIPS2); |
| 5445 |
save_cpu_state(ctx, 1); |
|
| 5446 | 5425 |
gen_helper_eret(); |
| 5447 | 5426 |
ctx->bstate = BS_EXCP; |
| 5448 | 5427 |
break; |
| ... | ... | |
| 5453 | 5432 |
MIPS_INVAL(opn); |
| 5454 | 5433 |
generate_exception(ctx, EXCP_RI); |
| 5455 | 5434 |
} else {
|
| 5456 |
save_cpu_state(ctx, 1); |
|
| 5457 | 5435 |
gen_helper_deret(); |
| 5458 | 5436 |
ctx->bstate = BS_EXCP; |
| 5459 | 5437 |
} |
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