Statistics
| Branch: | Revision:

root / hw / pc.c @ 2091ba23

History | View | Annotate | Download (44.5 kB)

1
/*
2
 * QEMU PC System Emulator
3
 *
4
 * Copyright (c) 2003-2004 Fabrice Bellard
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24
#include "hw.h"
25
#include "pc.h"
26
#include "fdc.h"
27
#include "pci.h"
28
#include "block.h"
29
#include "sysemu.h"
30
#include "audio/audio.h"
31
#include "net.h"
32
#include "smbus.h"
33
#include "boards.h"
34
#include "monitor.h"
35
#include "fw_cfg.h"
36
#include "hpet_emul.h"
37
#include "watchdog.h"
38
#include "smbios.h"
39

    
40
/* output Bochs bios info messages */
41
//#define DEBUG_BIOS
42

    
43
/* Show multiboot debug output */
44
//#define DEBUG_MULTIBOOT
45

    
46
#define BIOS_FILENAME "bios.bin"
47
#define VGABIOS_FILENAME "vgabios.bin"
48
#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
49

    
50
#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
51

    
52
/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
53
#define ACPI_DATA_SIZE       0x10000
54
#define BIOS_CFG_IOPORT 0x510
55
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
56
#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
57
#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
58

    
59
#define MAX_IDE_BUS 2
60

    
61
static fdctrl_t *floppy_controller;
62
static RTCState *rtc_state;
63
static PITState *pit;
64
static PCIDevice *i440fx_state;
65

    
66
typedef struct rom_reset_data {
67
    uint8_t *data;
68
    target_phys_addr_t addr;
69
    unsigned size;
70
} RomResetData;
71

    
72
static void option_rom_reset(void *_rrd)
73
{
74
    RomResetData *rrd = _rrd;
75

    
76
    cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
77
}
78

    
79
static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
80
{
81
    RomResetData *rrd = qemu_malloc(sizeof *rrd);
82

    
83
    rrd->data = qemu_malloc(size);
84
    cpu_physical_memory_read(addr, rrd->data, size);
85
    rrd->addr = addr;
86
    rrd->size = size;
87
    qemu_register_reset(option_rom_reset, rrd);
88
}
89

    
90
typedef struct isa_irq_state {
91
    qemu_irq *i8259;
92
    qemu_irq *ioapic;
93
} IsaIrqState;
94

    
95
static void isa_irq_handler(void *opaque, int n, int level)
96
{
97
    IsaIrqState *isa = (IsaIrqState *)opaque;
98

    
99
    if (n < 16) {
100
        qemu_set_irq(isa->i8259[n], level);
101
    }
102
    qemu_set_irq(isa->ioapic[n], level);
103
};
104

    
105
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
106
{
107
}
108

    
109
/* MSDOS compatibility mode FPU exception support */
110
static qemu_irq ferr_irq;
111
/* XXX: add IGNNE support */
112
void cpu_set_ferr(CPUX86State *s)
113
{
114
    qemu_irq_raise(ferr_irq);
115
}
116

    
117
static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
118
{
119
    qemu_irq_lower(ferr_irq);
120
}
121

    
122
/* TSC handling */
123
uint64_t cpu_get_tsc(CPUX86State *env)
124
{
125
    return cpu_get_ticks();
126
}
127

    
128
/* SMM support */
129
void cpu_smm_update(CPUState *env)
130
{
131
    if (i440fx_state && env == first_cpu)
132
        i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
133
}
134

    
135

    
136
/* IRQ handling */
137
int cpu_get_pic_interrupt(CPUState *env)
138
{
139
    int intno;
140

    
141
    intno = apic_get_interrupt(env);
142
    if (intno >= 0) {
143
        /* set irq request if a PIC irq is still pending */
144
        /* XXX: improve that */
145
        pic_update_irq(isa_pic);
146
        return intno;
147
    }
148
    /* read the irq from the PIC */
149
    if (!apic_accept_pic_intr(env))
150
        return -1;
151

    
152
    intno = pic_read_irq(isa_pic);
153
    return intno;
154
}
155

    
156
static void pic_irq_request(void *opaque, int irq, int level)
157
{
158
    CPUState *env = first_cpu;
159

    
160
    if (env->apic_state) {
161
        while (env) {
162
            if (apic_accept_pic_intr(env))
163
                apic_deliver_pic_intr(env, level);
164
            env = env->next_cpu;
165
        }
166
    } else {
167
        if (level)
168
            cpu_interrupt(env, CPU_INTERRUPT_HARD);
169
        else
170
            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
171
    }
172
}
173

    
174
/* PC cmos mappings */
175

    
176
#define REG_EQUIPMENT_BYTE          0x14
177

    
178
static int cmos_get_fd_drive_type(int fd0)
179
{
180
    int val;
181

    
182
    switch (fd0) {
183
    case 0:
184
        /* 1.44 Mb 3"5 drive */
185
        val = 4;
186
        break;
187
    case 1:
188
        /* 2.88 Mb 3"5 drive */
189
        val = 5;
190
        break;
191
    case 2:
192
        /* 1.2 Mb 5"5 drive */
193
        val = 2;
194
        break;
195
    default:
196
        val = 0;
197
        break;
198
    }
199
    return val;
200
}
201

    
202
static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
203
{
204
    RTCState *s = rtc_state;
205
    int cylinders, heads, sectors;
206
    bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
207
    rtc_set_memory(s, type_ofs, 47);
208
    rtc_set_memory(s, info_ofs, cylinders);
209
    rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
210
    rtc_set_memory(s, info_ofs + 2, heads);
211
    rtc_set_memory(s, info_ofs + 3, 0xff);
212
    rtc_set_memory(s, info_ofs + 4, 0xff);
213
    rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
214
    rtc_set_memory(s, info_ofs + 6, cylinders);
215
    rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
216
    rtc_set_memory(s, info_ofs + 8, sectors);
217
}
218

    
219
/* convert boot_device letter to something recognizable by the bios */
220
static int boot_device2nibble(char boot_device)
221
{
222
    switch(boot_device) {
223
    case 'a':
224
    case 'b':
225
        return 0x01; /* floppy boot */
226
    case 'c':
227
        return 0x02; /* hard drive boot */
228
    case 'd':
229
        return 0x03; /* CD-ROM boot */
230
    case 'n':
231
        return 0x04; /* Network boot */
232
    }
233
    return 0;
234
}
235

    
236
/* copy/pasted from cmos_init, should be made a general function
237
 and used there as well */
238
static int pc_boot_set(void *opaque, const char *boot_device)
239
{
240
    Monitor *mon = cur_mon;
241
#define PC_MAX_BOOT_DEVICES 3
242
    RTCState *s = (RTCState *)opaque;
243
    int nbds, bds[3] = { 0, };
244
    int i;
245

    
246
    nbds = strlen(boot_device);
247
    if (nbds > PC_MAX_BOOT_DEVICES) {
248
        monitor_printf(mon, "Too many boot devices for PC\n");
249
        return(1);
250
    }
251
    for (i = 0; i < nbds; i++) {
252
        bds[i] = boot_device2nibble(boot_device[i]);
253
        if (bds[i] == 0) {
254
            monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
255
                           boot_device[i]);
256
            return(1);
257
        }
258
    }
259
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
260
    rtc_set_memory(s, 0x38, (bds[2] << 4));
261
    return(0);
262
}
263

    
264
/* hd_table must contain 4 block drivers */
265
static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
266
                      const char *boot_device, BlockDriverState **hd_table)
267
{
268
    RTCState *s = rtc_state;
269
    int nbds, bds[3] = { 0, };
270
    int val;
271
    int fd0, fd1, nb;
272
    int i;
273

    
274
    /* various important CMOS locations needed by PC/Bochs bios */
275

    
276
    /* memory size */
277
    val = 640; /* base memory in K */
278
    rtc_set_memory(s, 0x15, val);
279
    rtc_set_memory(s, 0x16, val >> 8);
280

    
281
    val = (ram_size / 1024) - 1024;
282
    if (val > 65535)
283
        val = 65535;
284
    rtc_set_memory(s, 0x17, val);
285
    rtc_set_memory(s, 0x18, val >> 8);
286
    rtc_set_memory(s, 0x30, val);
287
    rtc_set_memory(s, 0x31, val >> 8);
288

    
289
    if (above_4g_mem_size) {
290
        rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
291
        rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
292
        rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
293
    }
294

    
295
    if (ram_size > (16 * 1024 * 1024))
296
        val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
297
    else
298
        val = 0;
299
    if (val > 65535)
300
        val = 65535;
301
    rtc_set_memory(s, 0x34, val);
302
    rtc_set_memory(s, 0x35, val >> 8);
303

    
304
    /* set the number of CPU */
305
    rtc_set_memory(s, 0x5f, smp_cpus - 1);
306

    
307
    /* set boot devices, and disable floppy signature check if requested */
308
#define PC_MAX_BOOT_DEVICES 3
309
    nbds = strlen(boot_device);
310
    if (nbds > PC_MAX_BOOT_DEVICES) {
311
        fprintf(stderr, "Too many boot devices for PC\n");
312
        exit(1);
313
    }
314
    for (i = 0; i < nbds; i++) {
315
        bds[i] = boot_device2nibble(boot_device[i]);
316
        if (bds[i] == 0) {
317
            fprintf(stderr, "Invalid boot device for PC: '%c'\n",
318
                    boot_device[i]);
319
            exit(1);
320
        }
321
    }
322
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
323
    rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
324

    
325
    /* floppy type */
326

    
327
    fd0 = fdctrl_get_drive_type(floppy_controller, 0);
328
    fd1 = fdctrl_get_drive_type(floppy_controller, 1);
329

    
330
    val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
331
    rtc_set_memory(s, 0x10, val);
332

    
333
    val = 0;
334
    nb = 0;
335
    if (fd0 < 3)
336
        nb++;
337
    if (fd1 < 3)
338
        nb++;
339
    switch (nb) {
340
    case 0:
341
        break;
342
    case 1:
343
        val |= 0x01; /* 1 drive, ready for boot */
344
        break;
345
    case 2:
346
        val |= 0x41; /* 2 drives, ready for boot */
347
        break;
348
    }
349
    val |= 0x02; /* FPU is there */
350
    val |= 0x04; /* PS/2 mouse installed */
351
    rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
352

    
353
    /* hard drives */
354

    
355
    rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
356
    if (hd_table[0])
357
        cmos_init_hd(0x19, 0x1b, hd_table[0]);
358
    if (hd_table[1])
359
        cmos_init_hd(0x1a, 0x24, hd_table[1]);
360

    
361
    val = 0;
362
    for (i = 0; i < 4; i++) {
363
        if (hd_table[i]) {
364
            int cylinders, heads, sectors, translation;
365
            /* NOTE: bdrv_get_geometry_hint() returns the physical
366
                geometry.  It is always such that: 1 <= sects <= 63, 1
367
                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
368
                geometry can be different if a translation is done. */
369
            translation = bdrv_get_translation_hint(hd_table[i]);
370
            if (translation == BIOS_ATA_TRANSLATION_AUTO) {
371
                bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
372
                if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
373
                    /* No translation. */
374
                    translation = 0;
375
                } else {
376
                    /* LBA translation. */
377
                    translation = 1;
378
                }
379
            } else {
380
                translation--;
381
            }
382
            val |= translation << (i * 2);
383
        }
384
    }
385
    rtc_set_memory(s, 0x39, val);
386
}
387

    
388
void ioport_set_a20(int enable)
389
{
390
    /* XXX: send to all CPUs ? */
391
    cpu_x86_set_a20(first_cpu, enable);
392
}
393

    
394
int ioport_get_a20(void)
395
{
396
    return ((first_cpu->a20_mask >> 20) & 1);
397
}
398

    
399
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
400
{
401
    ioport_set_a20((val >> 1) & 1);
402
    /* XXX: bit 0 is fast reset */
403
}
404

    
405
static uint32_t ioport92_read(void *opaque, uint32_t addr)
406
{
407
    return ioport_get_a20() << 1;
408
}
409

    
410
/***********************************************************/
411
/* Bochs BIOS debug ports */
412

    
413
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
414
{
415
    static const char shutdown_str[8] = "Shutdown";
416
    static int shutdown_index = 0;
417

    
418
    switch(addr) {
419
        /* Bochs BIOS messages */
420
    case 0x400:
421
    case 0x401:
422
        fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
423
        exit(1);
424
    case 0x402:
425
    case 0x403:
426
#ifdef DEBUG_BIOS
427
        fprintf(stderr, "%c", val);
428
#endif
429
        break;
430
    case 0x8900:
431
        /* same as Bochs power off */
432
        if (val == shutdown_str[shutdown_index]) {
433
            shutdown_index++;
434
            if (shutdown_index == 8) {
435
                shutdown_index = 0;
436
                qemu_system_shutdown_request();
437
            }
438
        } else {
439
            shutdown_index = 0;
440
        }
441
        break;
442

    
443
        /* LGPL'ed VGA BIOS messages */
444
    case 0x501:
445
    case 0x502:
446
        fprintf(stderr, "VGA BIOS panic, line %d\n", val);
447
        exit(1);
448
    case 0x500:
449
    case 0x503:
450
#ifdef DEBUG_BIOS
451
        fprintf(stderr, "%c", val);
452
#endif
453
        break;
454
    }
455
}
456

    
457
extern uint64_t node_cpumask[MAX_NODES];
458

    
459
static void *bochs_bios_init(void)
460
{
461
    void *fw_cfg;
462
    uint8_t *smbios_table;
463
    size_t smbios_len;
464
    uint64_t *numa_fw_cfg;
465
    int i, j;
466

    
467
    register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
468
    register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
469
    register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
470
    register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
471
    register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
472

    
473
    register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
474
    register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
475
    register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
476
    register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
477

    
478
    fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
479

    
480
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
481
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
482
    fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
483
                     acpi_tables_len);
484
    fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
485

    
486
    smbios_table = smbios_get_table(&smbios_len);
487
    if (smbios_table)
488
        fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
489
                         smbios_table, smbios_len);
490

    
491
    /* allocate memory for the NUMA channel: one (64bit) word for the number
492
     * of nodes, one word for each VCPU->node and one word for each node to
493
     * hold the amount of memory.
494
     */
495
    numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
496
    numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
497
    for (i = 0; i < smp_cpus; i++) {
498
        for (j = 0; j < nb_numa_nodes; j++) {
499
            if (node_cpumask[j] & (1 << i)) {
500
                numa_fw_cfg[i + 1] = cpu_to_le64(j);
501
                break;
502
            }
503
        }
504
    }
505
    for (i = 0; i < nb_numa_nodes; i++) {
506
        numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
507
    }
508
    fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
509
                     (1 + smp_cpus + nb_numa_nodes) * 8);
510

    
511
    return fw_cfg;
512
}
513

    
514
/* Generate an initial boot sector which sets state and jump to
515
   a specified vector */
516
static void generate_bootsect(target_phys_addr_t option_rom,
517
                              uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
518
{
519
    uint8_t rom[512], *p, *reloc;
520
    uint8_t sum;
521
    int i;
522

    
523
    memset(rom, 0, sizeof(rom));
524

    
525
    p = rom;
526
    /* Make sure we have an option rom signature */
527
    *p++ = 0x55;
528
    *p++ = 0xaa;
529

    
530
    /* ROM size in sectors*/
531
    *p++ = 1;
532

    
533
    /* Hook int19 */
534

    
535
    *p++ = 0x50;                /* push ax */
536
    *p++ = 0x1e;                /* push ds */
537
    *p++ = 0x31; *p++ = 0xc0;        /* xor ax, ax */
538
    *p++ = 0x8e; *p++ = 0xd8;        /* mov ax, ds */
539

    
540
    *p++ = 0xc7; *p++ = 0x06;   /* movvw _start,0x64 */
541
    *p++ = 0x64; *p++ = 0x00;
542
    reloc = p;
543
    *p++ = 0x00; *p++ = 0x00;
544

    
545
    *p++ = 0x8c; *p++ = 0x0e;   /* mov cs,0x66 */
546
    *p++ = 0x66; *p++ = 0x00;
547

    
548
    *p++ = 0x1f;                /* pop ds */
549
    *p++ = 0x58;                /* pop ax */
550
    *p++ = 0xcb;                /* lret */
551
    
552
    /* Actual code */
553
    *reloc = (p - rom);
554

    
555
    *p++ = 0xfa;                /* CLI */
556
    *p++ = 0xfc;                /* CLD */
557

    
558
    for (i = 0; i < 6; i++) {
559
        if (i == 1)                /* Skip CS */
560
            continue;
561

    
562
        *p++ = 0xb8;                /* MOV AX,imm16 */
563
        *p++ = segs[i];
564
        *p++ = segs[i] >> 8;
565
        *p++ = 0x8e;                /* MOV <seg>,AX */
566
        *p++ = 0xc0 + (i << 3);
567
    }
568

    
569
    for (i = 0; i < 8; i++) {
570
        *p++ = 0x66;                /* 32-bit operand size */
571
        *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
572
        *p++ = gpr[i];
573
        *p++ = gpr[i] >> 8;
574
        *p++ = gpr[i] >> 16;
575
        *p++ = gpr[i] >> 24;
576
    }
577

    
578
    *p++ = 0xea;                /* JMP FAR */
579
    *p++ = ip;                        /* IP */
580
    *p++ = ip >> 8;
581
    *p++ = segs[1];                /* CS */
582
    *p++ = segs[1] >> 8;
583

    
584
    /* sign rom */
585
    sum = 0;
586
    for (i = 0; i < (sizeof(rom) - 1); i++)
587
        sum += rom[i];
588
    rom[sizeof(rom) - 1] = -sum;
589

    
590
    cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
591
    option_rom_setup_reset(option_rom, sizeof (rom));
592
}
593

    
594
static long get_file_size(FILE *f)
595
{
596
    long where, size;
597

    
598
    /* XXX: on Unix systems, using fstat() probably makes more sense */
599

    
600
    where = ftell(f);
601
    fseek(f, 0, SEEK_END);
602
    size = ftell(f);
603
    fseek(f, where, SEEK_SET);
604

    
605
    return size;
606
}
607

    
608
#define MULTIBOOT_STRUCT_ADDR 0x9000
609

    
610
#if MULTIBOOT_STRUCT_ADDR > 0xf0000
611
#error multiboot struct needs to fit in 16 bit real mode
612
#endif
613

    
614
static int load_multiboot(void *fw_cfg,
615
                          FILE *f,
616
                          const char *kernel_filename,
617
                          const char *initrd_filename,
618
                          const char *kernel_cmdline,
619
                          uint8_t *header)
620
{
621
    int i, t, is_multiboot = 0;
622
    uint32_t flags = 0;
623
    uint32_t mh_entry_addr;
624
    uint32_t mh_load_addr;
625
    uint32_t mb_kernel_size;
626
    uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR;
627
    uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
628
    uint32_t mb_cmdline = mb_bootinfo + 0x200;
629
    uint32_t mb_mod_end;
630

    
631
    /* Ok, let's see if it is a multiboot image.
632
       The header is 12x32bit long, so the latest entry may be 8192 - 48. */
633
    for (i = 0; i < (8192 - 48); i += 4) {
634
        if (ldl_p(header+i) == 0x1BADB002) {
635
            uint32_t checksum = ldl_p(header+i+8);
636
            flags = ldl_p(header+i+4);
637
            checksum += flags;
638
            checksum += (uint32_t)0x1BADB002;
639
            if (!checksum) {
640
                is_multiboot = 1;
641
                break;
642
            }
643
        }
644
    }
645

    
646
    if (!is_multiboot)
647
        return 0; /* no multiboot */
648

    
649
#ifdef DEBUG_MULTIBOOT
650
    fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
651
#endif
652

    
653
    if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */
654
        fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
655
    }
656
    if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */
657
        uint64_t elf_entry;
658
        int kernel_size;
659
        fclose(f);
660
        kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
661
        if (kernel_size < 0) {
662
            fprintf(stderr, "Error while loading elf kernel\n");
663
            exit(1);
664
        }
665
        mh_load_addr = mh_entry_addr = elf_entry;
666
        mb_kernel_size = kernel_size;
667

    
668
#ifdef DEBUG_MULTIBOOT
669
        fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
670
                mb_kernel_size, (size_t)mh_entry_addr);
671
#endif
672
    } else {
673
        /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
674
        uint32_t mh_header_addr = ldl_p(header+i+12);
675
        mh_load_addr = ldl_p(header+i+16);
676
#ifdef DEBUG_MULTIBOOT
677
        uint32_t mh_load_end_addr = ldl_p(header+i+20);
678
        uint32_t mh_bss_end_addr = ldl_p(header+i+24);
679
#endif
680
        uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
681

    
682
        mh_entry_addr = ldl_p(header+i+28);
683
        mb_kernel_size = get_file_size(f) - mb_kernel_text_offset;
684

    
685
        /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
686
        uint32_t mh_mode_type = ldl_p(header+i+32);
687
        uint32_t mh_width = ldl_p(header+i+36);
688
        uint32_t mh_height = ldl_p(header+i+40);
689
        uint32_t mh_depth = ldl_p(header+i+44); */
690

    
691
#ifdef DEBUG_MULTIBOOT
692
        fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
693
        fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
694
        fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
695
        fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
696
#endif
697

    
698
        fseek(f, mb_kernel_text_offset, SEEK_SET);
699

    
700
#ifdef DEBUG_MULTIBOOT
701
        fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
702
                mb_kernel_size, mh_load_addr);
703
#endif
704

    
705
        if (!fread_targphys_ok(mh_load_addr, mb_kernel_size, f)) {
706
            fprintf(stderr, "qemu: read error on multiboot kernel '%s' (%#x)\n",
707
                    kernel_filename, mb_kernel_size);
708
            exit(1);
709
        }
710
        fclose(f);
711
    }
712

    
713
    /* blob size is only the kernel for now */
714
    mb_mod_end = mh_load_addr + mb_kernel_size;
715

    
716
    /* load modules */
717
    stl_phys(mb_bootinfo + 20, 0x0); /* mods_count */
718
    if (initrd_filename) {
719
        uint32_t mb_mod_info = mb_bootinfo + 0x100;
720
        uint32_t mb_mod_cmdline = mb_bootinfo + 0x300;
721
        uint32_t mb_mod_start = mh_load_addr;
722
        uint32_t mb_mod_length = mb_kernel_size;
723
        char *next_initrd;
724
        char *next_space;
725
        int mb_mod_count = 0;
726

    
727
        do {
728
            next_initrd = strchr(initrd_filename, ',');
729
            if (next_initrd)
730
                *next_initrd = '\0';
731
            /* if a space comes after the module filename, treat everything
732
               after that as parameters */
733
            cpu_physical_memory_write(mb_mod_cmdline, (uint8_t*)initrd_filename,
734
                                      strlen(initrd_filename) + 1);
735
            stl_phys(mb_mod_info + 8, mb_mod_cmdline); /* string */
736
            mb_mod_cmdline += strlen(initrd_filename) + 1;
737
            if ((next_space = strchr(initrd_filename, ' ')))
738
                *next_space = '\0';
739
#ifdef DEBUG_MULTIBOOT
740
             printf("multiboot loading module: %s\n", initrd_filename);
741
#endif
742
            f = fopen(initrd_filename, "rb");
743
            if (f) {
744
                mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
745
                             & (TARGET_PAGE_MASK);
746
                mb_mod_length = get_file_size(f);
747
                mb_mod_end = mb_mod_start + mb_mod_length;
748

    
749
                if (!fread_targphys_ok(mb_mod_start, mb_mod_length, f)) {
750
                    fprintf(stderr, "qemu: read error on multiboot module '%s' (%#x)\n",
751
                            initrd_filename, mb_mod_length);
752
                    exit(1);
753
                }
754

    
755
                mb_mod_count++;
756
                stl_phys(mb_mod_info + 0, mb_mod_start);
757
                stl_phys(mb_mod_info + 4, mb_mod_start + mb_mod_length);
758
#ifdef DEBUG_MULTIBOOT
759
                printf("mod_start: %#x\nmod_end:   %#x\n", mb_mod_start,
760
                       mb_mod_start + mb_mod_length);
761
#endif
762
                stl_phys(mb_mod_info + 12, 0x0); /* reserved */
763
            }
764
            initrd_filename = next_initrd+1;
765
            mb_mod_info += 16;
766
        } while (next_initrd);
767
        stl_phys(mb_bootinfo + 20, mb_mod_count); /* mods_count */
768
        stl_phys(mb_bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */
769
    }
770

    
771
    /* Make sure we're getting kernel + modules back after reset */
772
    option_rom_setup_reset(mh_load_addr, mb_mod_end - mh_load_addr);
773

    
774
    /* Commandline support */
775
    stl_phys(mb_bootinfo + 16, mb_cmdline);
776
    t = strlen(kernel_filename);
777
    cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_filename, t);
778
    mb_cmdline += t;
779
    stb_phys(mb_cmdline++, ' ');
780
    t = strlen(kernel_cmdline) + 1;
781
    cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_cmdline, t);
782

    
783
    /* the kernel is where we want it to be now */
784

    
785
#define MULTIBOOT_FLAGS_MEMORY (1 << 0)
786
#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1)
787
#define MULTIBOOT_FLAGS_CMDLINE (1 << 2)
788
#define MULTIBOOT_FLAGS_MODULES (1 << 3)
789
#define MULTIBOOT_FLAGS_MMAP (1 << 6)
790
    stl_phys(mb_bootinfo, MULTIBOOT_FLAGS_MEMORY
791
                        | MULTIBOOT_FLAGS_BOOT_DEVICE
792
                        | MULTIBOOT_FLAGS_CMDLINE
793
                        | MULTIBOOT_FLAGS_MODULES
794
                        | MULTIBOOT_FLAGS_MMAP);
795
    stl_phys(mb_bootinfo + 4, 640); /* mem_lower */
796
    stl_phys(mb_bootinfo + 8, ram_size / 1024); /* mem_upper */
797
    stl_phys(mb_bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */
798
    stl_phys(mb_bootinfo + 48, mmap_addr); /* mmap_addr */
799

    
800
#ifdef DEBUG_MULTIBOOT
801
    fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
802
#endif
803

    
804
    /* Pass variables to option rom */
805
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr);
806
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo);
807
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr);
808

    
809
    /* Make sure we're getting the config space back after reset */
810
    option_rom_setup_reset(mb_bootinfo, 0x500);
811

    
812
    option_rom[nb_option_roms] = "multiboot.bin";
813
    nb_option_roms++;
814

    
815
    return 1; /* yes, we are multiboot */
816
}
817

    
818
static void load_linux(void *fw_cfg,
819
                       target_phys_addr_t option_rom,
820
                       const char *kernel_filename,
821
                       const char *initrd_filename,
822
                       const char *kernel_cmdline,
823
               target_phys_addr_t max_ram_size)
824
{
825
    uint16_t protocol;
826
    uint32_t gpr[8];
827
    uint16_t seg[6];
828
    uint16_t real_seg;
829
    int setup_size, kernel_size, initrd_size = 0, cmdline_size;
830
    uint32_t initrd_max;
831
    uint8_t header[8192];
832
    target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
833
    FILE *f, *fi;
834
    char *vmode;
835

    
836
    /* Align to 16 bytes as a paranoia measure */
837
    cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
838

    
839
    /* load the kernel header */
840
    f = fopen(kernel_filename, "rb");
841
    if (!f || !(kernel_size = get_file_size(f)) ||
842
        fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
843
        MIN(ARRAY_SIZE(header), kernel_size)) {
844
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
845
                kernel_filename);
846
        exit(1);
847
    }
848

    
849
    /* kernel protocol version */
850
#if 0
851
    fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
852
#endif
853
    if (ldl_p(header+0x202) == 0x53726448)
854
        protocol = lduw_p(header+0x206);
855
    else {
856
        /* This looks like a multiboot kernel. If it is, let's stop
857
           treating it like a Linux kernel. */
858
        if (load_multiboot(fw_cfg, f, kernel_filename,
859
                           initrd_filename, kernel_cmdline, header))
860
           return;
861
        protocol = 0;
862
    }
863

    
864
    if (protocol < 0x200 || !(header[0x211] & 0x01)) {
865
        /* Low kernel */
866
        real_addr    = 0x90000;
867
        cmdline_addr = 0x9a000 - cmdline_size;
868
        prot_addr    = 0x10000;
869
    } else if (protocol < 0x202) {
870
        /* High but ancient kernel */
871
        real_addr    = 0x90000;
872
        cmdline_addr = 0x9a000 - cmdline_size;
873
        prot_addr    = 0x100000;
874
    } else {
875
        /* High and recent kernel */
876
        real_addr    = 0x10000;
877
        cmdline_addr = 0x20000;
878
        prot_addr    = 0x100000;
879
    }
880

    
881
#if 0
882
    fprintf(stderr,
883
            "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
884
            "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
885
            "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
886
            real_addr,
887
            cmdline_addr,
888
            prot_addr);
889
#endif
890

    
891
    /* highest address for loading the initrd */
892
    if (protocol >= 0x203)
893
        initrd_max = ldl_p(header+0x22c);
894
    else
895
        initrd_max = 0x37ffffff;
896

    
897
    if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
898
            initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
899

    
900
    /* kernel command line */
901
    pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
902

    
903
    if (protocol >= 0x202) {
904
        stl_p(header+0x228, cmdline_addr);
905
    } else {
906
        stw_p(header+0x20, 0xA33F);
907
        stw_p(header+0x22, cmdline_addr-real_addr);
908
    }
909

    
910
    /* handle vga= parameter */
911
    vmode = strstr(kernel_cmdline, "vga=");
912
    if (vmode) {
913
        unsigned int video_mode;
914
        /* skip "vga=" */
915
        vmode += 4;
916
        if (!strncmp(vmode, "normal", 6)) {
917
            video_mode = 0xffff;
918
        } else if (!strncmp(vmode, "ext", 3)) {
919
            video_mode = 0xfffe;
920
        } else if (!strncmp(vmode, "ask", 3)) {
921
            video_mode = 0xfffd;
922
        } else {
923
            video_mode = strtol(vmode, NULL, 0);
924
        }
925
        stw_p(header+0x1fa, video_mode);
926
    }
927

    
928
    /* loader type */
929
    /* High nybble = B reserved for Qemu; low nybble is revision number.
930
       If this code is substantially changed, you may want to consider
931
       incrementing the revision. */
932
    if (protocol >= 0x200)
933
        header[0x210] = 0xB0;
934

    
935
    /* heap */
936
    if (protocol >= 0x201) {
937
        header[0x211] |= 0x80;        /* CAN_USE_HEAP */
938
        stw_p(header+0x224, cmdline_addr-real_addr-0x200);
939
    }
940

    
941
    /* load initrd */
942
    if (initrd_filename) {
943
        if (protocol < 0x200) {
944
            fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
945
            exit(1);
946
        }
947

    
948
        fi = fopen(initrd_filename, "rb");
949
        if (!fi) {
950
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
951
                    initrd_filename);
952
            exit(1);
953
        }
954

    
955
        initrd_size = get_file_size(fi);
956
        initrd_addr = (initrd_max-initrd_size) & ~4095;
957

    
958
        if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
959
            fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
960
                    initrd_filename);
961
            exit(1);
962
        }
963
        fclose(fi);
964

    
965
        stl_p(header+0x218, initrd_addr);
966
        stl_p(header+0x21c, initrd_size);
967
    }
968

    
969
    /* store the finalized header and load the rest of the kernel */
970
    cpu_physical_memory_write(real_addr, header, ARRAY_SIZE(header));
971

    
972
    setup_size = header[0x1f1];
973
    if (setup_size == 0)
974
        setup_size = 4;
975

    
976
    setup_size = (setup_size+1)*512;
977
    /* Size of protected-mode code */
978
    kernel_size -= (setup_size > ARRAY_SIZE(header)) ? setup_size : ARRAY_SIZE(header);
979

    
980
    /* In case we have read too much already, copy that over */
981
    if (setup_size < ARRAY_SIZE(header)) {
982
        cpu_physical_memory_write(prot_addr, header + setup_size, ARRAY_SIZE(header) - setup_size);
983
        prot_addr += (ARRAY_SIZE(header) - setup_size);
984
        setup_size = ARRAY_SIZE(header);
985
    }
986

    
987
    if (!fread_targphys_ok(real_addr + ARRAY_SIZE(header),
988
                           setup_size - ARRAY_SIZE(header), f) ||
989
        !fread_targphys_ok(prot_addr, kernel_size, f)) {
990
        fprintf(stderr, "qemu: read error on kernel '%s'\n",
991
                kernel_filename);
992
        exit(1);
993
    }
994
    fclose(f);
995

    
996
    /* generate bootsector to set up the initial register state */
997
    real_seg = real_addr >> 4;
998
    seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
999
    seg[1] = real_seg+0x20;        /* CS */
1000
    memset(gpr, 0, sizeof gpr);
1001
    gpr[4] = cmdline_addr-real_addr-16;        /* SP (-16 is paranoia) */
1002

    
1003
    option_rom_setup_reset(real_addr, setup_size);
1004
    option_rom_setup_reset(prot_addr, kernel_size);
1005
    option_rom_setup_reset(cmdline_addr, cmdline_size);
1006
    if (initrd_filename)
1007
        option_rom_setup_reset(initrd_addr, initrd_size);
1008

    
1009
    generate_bootsect(option_rom, gpr, seg, 0);
1010
}
1011

    
1012
static const int ide_iobase[2] = { 0x1f0, 0x170 };
1013
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
1014
static const int ide_irq[2] = { 14, 15 };
1015

    
1016
#define NE2000_NB_MAX 6
1017

    
1018
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
1019
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1020

    
1021
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
1022
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
1023

    
1024
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
1025
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
1026

    
1027
#ifdef HAS_AUDIO
1028
static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
1029
{
1030
    struct soundhw *c;
1031

    
1032
    for (c = soundhw; c->name; ++c) {
1033
        if (c->enabled) {
1034
            if (c->isa) {
1035
                c->init.init_isa(pic);
1036
            } else {
1037
                if (pci_bus) {
1038
                    c->init.init_pci(pci_bus);
1039
                }
1040
            }
1041
        }
1042
    }
1043
}
1044
#endif
1045

    
1046
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
1047
{
1048
    static int nb_ne2k = 0;
1049

    
1050
    if (nb_ne2k == NE2000_NB_MAX)
1051
        return;
1052
    isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
1053
    nb_ne2k++;
1054
}
1055

    
1056
static int load_option_rom(const char *oprom, target_phys_addr_t start,
1057
                           target_phys_addr_t end)
1058
{
1059
        int size;
1060
        char *filename;
1061

    
1062
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom);
1063
        if (filename) {
1064
            size = get_image_size(filename);
1065
            if (size > 0 && start + size > end) {
1066
                fprintf(stderr, "Not enough space to load option rom '%s'\n",
1067
                        oprom);
1068
                exit(1);
1069
            }
1070
            size = load_image_targphys(filename, start, end - start);
1071
            qemu_free(filename);
1072
        } else {
1073
            size = -1;
1074
        }
1075
        if (size < 0) {
1076
            fprintf(stderr, "Could not load option rom '%s'\n", oprom);
1077
            exit(1);
1078
        }
1079
        /* Round up optiom rom size to the next 2k boundary */
1080
        size = (size + 2047) & ~2047;
1081
        option_rom_setup_reset(start, size);
1082
        return size;
1083
}
1084

    
1085
int cpu_is_bsp(CPUState *env)
1086
{
1087
        return env->cpuid_apic_id == 0;
1088
}
1089

    
1090
static CPUState *pc_new_cpu(const char *cpu_model)
1091
{
1092
    CPUState *env;
1093

    
1094
    env = cpu_init(cpu_model);
1095
    if (!env) {
1096
        fprintf(stderr, "Unable to find x86 CPU definition\n");
1097
        exit(1);
1098
    }
1099
    if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
1100
        env->cpuid_apic_id = env->cpu_index;
1101
        /* APIC reset callback resets cpu */
1102
        apic_init(env);
1103
    } else {
1104
        qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
1105
    }
1106
    return env;
1107
}
1108

    
1109
/* PC hardware initialisation */
1110
static void pc_init1(ram_addr_t ram_size,
1111
                     const char *boot_device,
1112
                     const char *kernel_filename,
1113
                     const char *kernel_cmdline,
1114
                     const char *initrd_filename,
1115
                     const char *cpu_model,
1116
                     int pci_enabled)
1117
{
1118
    char *filename;
1119
    int ret, linux_boot, i;
1120
    ram_addr_t ram_addr, bios_offset, option_rom_offset;
1121
    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
1122
    int bios_size, isa_bios_size, oprom_area_size;
1123
    PCIBus *pci_bus;
1124
    PCIDevice *pci_dev;
1125
    ISADevice *isa_dev;
1126
    int piix3_devfn = -1;
1127
    CPUState *env;
1128
    qemu_irq *cpu_irq;
1129
    qemu_irq *isa_irq;
1130
    qemu_irq *i8259;
1131
    IsaIrqState *isa_irq_state;
1132
    DriveInfo *dinfo;
1133
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1134
    BlockDriverState *fd[MAX_FD];
1135
    int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
1136
    void *fw_cfg;
1137

    
1138
    if (ram_size >= 0xe0000000 ) {
1139
        above_4g_mem_size = ram_size - 0xe0000000;
1140
        below_4g_mem_size = 0xe0000000;
1141
    } else {
1142
        below_4g_mem_size = ram_size;
1143
    }
1144

    
1145
    linux_boot = (kernel_filename != NULL);
1146

    
1147
    /* init CPUs */
1148
    if (cpu_model == NULL) {
1149
#ifdef TARGET_X86_64
1150
        cpu_model = "qemu64";
1151
#else
1152
        cpu_model = "qemu32";
1153
#endif
1154
    }
1155

    
1156
    for (i = 0; i < smp_cpus; i++) {
1157
        env = pc_new_cpu(cpu_model);
1158
    }
1159

    
1160
    vmport_init();
1161

    
1162
    /* allocate RAM */
1163
    ram_addr = qemu_ram_alloc(0xa0000);
1164
    cpu_register_physical_memory(0, 0xa0000, ram_addr);
1165

    
1166
    /* Allocate, even though we won't register, so we don't break the
1167
     * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
1168
     * and some bios areas, which will be registered later
1169
     */
1170
    ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
1171
    ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
1172
    cpu_register_physical_memory(0x100000,
1173
                 below_4g_mem_size - 0x100000,
1174
                 ram_addr);
1175

    
1176
    /* above 4giga memory allocation */
1177
    if (above_4g_mem_size > 0) {
1178
#if TARGET_PHYS_ADDR_BITS == 32
1179
        hw_error("To much RAM for 32-bit physical address");
1180
#else
1181
        ram_addr = qemu_ram_alloc(above_4g_mem_size);
1182
        cpu_register_physical_memory(0x100000000ULL,
1183
                                     above_4g_mem_size,
1184
                                     ram_addr);
1185
#endif
1186
    }
1187

    
1188

    
1189
    /* BIOS load */
1190
    if (bios_name == NULL)
1191
        bios_name = BIOS_FILENAME;
1192
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1193
    if (filename) {
1194
        bios_size = get_image_size(filename);
1195
    } else {
1196
        bios_size = -1;
1197
    }
1198
    if (bios_size <= 0 ||
1199
        (bios_size % 65536) != 0) {
1200
        goto bios_error;
1201
    }
1202
    bios_offset = qemu_ram_alloc(bios_size);
1203
    ret = load_image(filename, qemu_get_ram_ptr(bios_offset));
1204
    if (ret != bios_size) {
1205
    bios_error:
1206
        fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1207
        exit(1);
1208
    }
1209
    if (filename) {
1210
        qemu_free(filename);
1211
    }
1212
    /* map the last 128KB of the BIOS in ISA space */
1213
    isa_bios_size = bios_size;
1214
    if (isa_bios_size > (128 * 1024))
1215
        isa_bios_size = 128 * 1024;
1216
    cpu_register_physical_memory(0x100000 - isa_bios_size,
1217
                                 isa_bios_size,
1218
                                 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
1219

    
1220

    
1221

    
1222
    option_rom_offset = qemu_ram_alloc(0x20000);
1223
    oprom_area_size = 0;
1224
    cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset);
1225

    
1226
    if (using_vga) {
1227
        const char *vgabios_filename;
1228
        /* VGA BIOS load */
1229
        if (cirrus_vga_enabled) {
1230
            vgabios_filename = VGABIOS_CIRRUS_FILENAME;
1231
        } else {
1232
            vgabios_filename = VGABIOS_FILENAME;
1233
        }
1234
        oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000);
1235
    }
1236
    /* Although video roms can grow larger than 0x8000, the area between
1237
     * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
1238
     * for any other kind of option rom inside this area */
1239
    if (oprom_area_size < 0x8000)
1240
        oprom_area_size = 0x8000;
1241

    
1242
    /* map all the bios at the top of memory */
1243
    cpu_register_physical_memory((uint32_t)(-bios_size),
1244
                                 bios_size, bios_offset | IO_MEM_ROM);
1245

    
1246
    fw_cfg = bochs_bios_init();
1247

    
1248
    if (linux_boot) {
1249
        load_linux(fw_cfg, 0xc0000 + oprom_area_size,
1250
                   kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1251
        oprom_area_size += 2048;
1252
    }
1253

    
1254
    for (i = 0; i < nb_option_roms; i++) {
1255
        oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
1256
                                           0xe0000);
1257
    }
1258

    
1259
    for (i = 0; i < nb_nics; i++) {
1260
        char nic_oprom[1024];
1261
        const char *model = nd_table[i].model;
1262

    
1263
        if (!nd_table[i].bootable)
1264
            continue;
1265

    
1266
        if (model == NULL)
1267
            model = "e1000";
1268
        snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model);
1269

    
1270
        oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
1271
                                           0xe0000);
1272
    }
1273

    
1274
    cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
1275
    i8259 = i8259_init(cpu_irq[0]);
1276
    isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
1277
    isa_irq_state->i8259 = i8259;
1278
    isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
1279
    ferr_irq = isa_irq[13];
1280

    
1281
    if (pci_enabled) {
1282
        pci_bus = i440fx_init(&i440fx_state, isa_irq);
1283
        piix3_devfn = piix3_init(pci_bus, -1);
1284
    } else {
1285
        pci_bus = NULL;
1286
        isa_bus_new(NULL);
1287
    }
1288
    isa_bus_irqs(isa_irq);
1289

    
1290
    /* init basic PC hardware */
1291
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1292

    
1293
    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1294

    
1295
    if (cirrus_vga_enabled) {
1296
        if (pci_enabled) {
1297
            pci_cirrus_vga_init(pci_bus);
1298
        } else {
1299
            isa_cirrus_vga_init();
1300
        }
1301
    } else if (vmsvga_enabled) {
1302
        if (pci_enabled)
1303
            pci_vmsvga_init(pci_bus);
1304
        else
1305
            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1306
    } else if (std_vga_enabled) {
1307
        if (pci_enabled) {
1308
            pci_vga_init(pci_bus, 0, 0);
1309
        } else {
1310
            isa_vga_init();
1311
        }
1312
    }
1313

    
1314
    rtc_state = rtc_init(0x70, isa_irq[8], 2000);
1315

    
1316
    qemu_register_boot_set(pc_boot_set, rtc_state);
1317

    
1318
    register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1319
    register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1320

    
1321
    if (pci_enabled) {
1322
        isa_irq_state->ioapic = ioapic_init();
1323
    }
1324
    pit = pit_init(0x40, isa_irq[0]);
1325
    pcspk_init(pit);
1326
    if (!no_hpet) {
1327
        hpet_init(isa_irq);
1328
    }
1329

    
1330
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1331
        if (serial_hds[i]) {
1332
            serial_init(serial_io[i], isa_irq[serial_irq[i]], 115200,
1333
                        serial_hds[i]);
1334
        }
1335
    }
1336

    
1337
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1338
        if (parallel_hds[i]) {
1339
            parallel_init(parallel_io[i], isa_irq[parallel_irq[i]],
1340
                          parallel_hds[i]);
1341
        }
1342
    }
1343

    
1344
    watchdog_pc_init(pci_bus);
1345

    
1346
    for(i = 0; i < nb_nics; i++) {
1347
        NICInfo *nd = &nd_table[i];
1348

    
1349
        if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1350
            pc_init_ne2k_isa(nd, isa_irq);
1351
        else
1352
            pci_nic_init(nd, "e1000", NULL);
1353
    }
1354

    
1355
    piix4_acpi_system_hot_add_init();
1356

    
1357
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1358
        fprintf(stderr, "qemu: too many IDE bus\n");
1359
        exit(1);
1360
    }
1361

    
1362
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1363
        dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1364
        hd[i] = dinfo ? dinfo->bdrv : NULL;
1365
    }
1366

    
1367
    if (pci_enabled) {
1368
        pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, isa_irq);
1369
    } else {
1370
        for(i = 0; i < MAX_IDE_BUS; i++) {
1371
            isa_ide_init(ide_iobase[i], ide_iobase2[i], isa_irq[ide_irq[i]],
1372
                         hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1373
        }
1374
    }
1375

    
1376
    isa_dev = isa_create_simple("i8042", 0x60, 0x64);
1377
    isa_connect_irq(isa_dev, 0, 1);
1378
    isa_connect_irq(isa_dev, 1, 12);
1379
    DMA_init(0);
1380
#ifdef HAS_AUDIO
1381
    audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
1382
#endif
1383

    
1384
    for(i = 0; i < MAX_FD; i++) {
1385
        dinfo = drive_get(IF_FLOPPY, 0, i);
1386
        fd[i] = dinfo ? dinfo->bdrv : NULL;
1387
    }
1388
    floppy_controller = fdctrl_init_isa(6, 2, 0x3f0, fd);
1389

    
1390
    cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1391

    
1392
    if (pci_enabled && usb_enabled) {
1393
        usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1394
    }
1395

    
1396
    if (pci_enabled && acpi_enabled) {
1397
        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1398
        i2c_bus *smbus;
1399

    
1400
        /* TODO: Populate SPD eeprom data.  */
1401
        smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, isa_irq[9]);
1402
        for (i = 0; i < 8; i++) {
1403
            DeviceState *eeprom;
1404
            eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1405
            qdev_prop_set_uint32(eeprom, "address", 0x50 + i);
1406
            qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1407
            qdev_init(eeprom);
1408
        }
1409
    }
1410

    
1411
    if (i440fx_state) {
1412
        i440fx_init_memory_mappings(i440fx_state);
1413
    }
1414

    
1415
    if (pci_enabled) {
1416
        int max_bus;
1417
        int bus;
1418

    
1419
        max_bus = drive_get_max_bus(IF_SCSI);
1420
        for (bus = 0; bus <= max_bus; bus++) {
1421
            pci_create_simple(pci_bus, -1, "lsi53c895a");
1422
        }
1423
    }
1424

    
1425
    /* Add virtio balloon device */
1426
    if (pci_enabled && virtio_balloon) {
1427
        pci_dev = pci_create("virtio-balloon-pci", virtio_balloon_devaddr);
1428
        qdev_init(&pci_dev->qdev);
1429
    }
1430

    
1431
    /* Add virtio console devices */
1432
    if (pci_enabled) {
1433
        for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1434
            if (virtcon_hds[i]) {
1435
                pci_create_simple(pci_bus, -1, "virtio-console-pci");
1436
            }
1437
        }
1438
    }
1439
}
1440

    
1441
static void pc_init_pci(ram_addr_t ram_size,
1442
                        const char *boot_device,
1443
                        const char *kernel_filename,
1444
                        const char *kernel_cmdline,
1445
                        const char *initrd_filename,
1446
                        const char *cpu_model)
1447
{
1448
    pc_init1(ram_size, boot_device,
1449
             kernel_filename, kernel_cmdline,
1450
             initrd_filename, cpu_model, 1);
1451
}
1452

    
1453
static void pc_init_isa(ram_addr_t ram_size,
1454
                        const char *boot_device,
1455
                        const char *kernel_filename,
1456
                        const char *kernel_cmdline,
1457
                        const char *initrd_filename,
1458
                        const char *cpu_model)
1459
{
1460
    pc_init1(ram_size, boot_device,
1461
             kernel_filename, kernel_cmdline,
1462
             initrd_filename, cpu_model, 0);
1463
}
1464

    
1465
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1466
   BIOS will read it and start S3 resume at POST Entry */
1467
void cmos_set_s3_resume(void)
1468
{
1469
    if (rtc_state)
1470
        rtc_set_memory(rtc_state, 0xF, 0xFE);
1471
}
1472

    
1473
static QEMUMachine pc_machine = {
1474
    .name = "pc-0.11",
1475
    .alias = "pc",
1476
    .desc = "Standard PC",
1477
    .init = pc_init_pci,
1478
    .max_cpus = 255,
1479
    .is_default = 1,
1480
};
1481

    
1482
static QEMUMachine pc_machine_v0_10 = {
1483
    .name = "pc-0.10",
1484
    .desc = "Standard PC, qemu 0.10",
1485
    .init = pc_init_pci,
1486
    .max_cpus = 255,
1487
    .compat_props = (CompatProperty[]) {
1488
        {
1489
            .driver   = "virtio-blk-pci",
1490
            .property = "class",
1491
            .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1492
        },{
1493
            .driver   = "virtio-console-pci",
1494
            .property = "class",
1495
            .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1496
        },{
1497
            .driver   = "virtio-net-pci",
1498
            .property = "vectors",
1499
            .value    = stringify(0),
1500
        },{
1501
            .driver   = "virtio-blk-pci",
1502
            .property = "vectors",
1503
            .value    = stringify(0),
1504
        },
1505
        { /* end of list */ }
1506
    },
1507
};
1508

    
1509
static QEMUMachine isapc_machine = {
1510
    .name = "isapc",
1511
    .desc = "ISA-only PC",
1512
    .init = pc_init_isa,
1513
    .max_cpus = 1,
1514
};
1515

    
1516
static void pc_machine_init(void)
1517
{
1518
    qemu_register_machine(&pc_machine);
1519
    qemu_register_machine(&pc_machine_v0_10);
1520
    qemu_register_machine(&isapc_machine);
1521
}
1522

    
1523
machine_init(pc_machine_init);