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#include "exec.h"
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//#define DEBUG_PCALL
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//#define DEBUG_MMU
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//#define DEBUG_MXCC
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//#define DEBUG_UNALIGNED
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//#define DEBUG_UNASSIGNED
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, args...) \
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do { printf("MMU: " fmt , ##args); } while (0)
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#else
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#define DPRINTF_MMU(fmt, args...)
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#endif
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#ifdef DEBUG_MXCC
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#define DPRINTF_MXCC(fmt, args...) \
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do { printf("MXCC: " fmt , ##args); } while (0)
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#else
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#define DPRINTF_MXCC(fmt, args...)
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#endif
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void raise_exception(int tt)
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{
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    env->exception_index = tt;
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    cpu_loop_exit();
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}
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void check_ieee_exceptions()
30
{
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     T0 = get_float_exception_flags(&env->fp_status);
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     if (T0)
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     {
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        /* Copy IEEE 754 flags into FSR */
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        if (T0 & float_flag_invalid)
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            env->fsr |= FSR_NVC;
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        if (T0 & float_flag_overflow)
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            env->fsr |= FSR_OFC;
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        if (T0 & float_flag_underflow)
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            env->fsr |= FSR_UFC;
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        if (T0 & float_flag_divbyzero)
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            env->fsr |= FSR_DZC;
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        if (T0 & float_flag_inexact)
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            env->fsr |= FSR_NXC;
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        if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
47
        {
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            /* Unmasked exception, generate a trap */
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            env->fsr |= FSR_FTT_IEEE_EXCP;
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            raise_exception(TT_FP_EXCP);
51
        }
52
        else
53
        {
54
            /* Accumulate exceptions */
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            env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
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        }
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     }
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}
59

    
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#ifdef USE_INT_TO_FLOAT_HELPERS
61
void do_fitos(void)
62
{
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    set_float_exception_flags(0, &env->fp_status);
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    FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
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    check_ieee_exceptions();
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}
67

    
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void do_fitod(void)
69
{
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    DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
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}
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#ifdef TARGET_SPARC64
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void do_fxtos(void)
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{
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    set_float_exception_flags(0, &env->fp_status);
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    FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
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    check_ieee_exceptions();
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}
79

    
80
void do_fxtod(void)
81
{
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    set_float_exception_flags(0, &env->fp_status);
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    DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
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    check_ieee_exceptions();
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}
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#endif
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#endif
88

    
89
void do_fabss(void)
90
{
91
    FT0 = float32_abs(FT1);
92
}
93

    
94
#ifdef TARGET_SPARC64
95
void do_fabsd(void)
96
{
97
    DT0 = float64_abs(DT1);
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}
99
#endif
100

    
101
void do_fsqrts(void)
102
{
103
    set_float_exception_flags(0, &env->fp_status);
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    FT0 = float32_sqrt(FT1, &env->fp_status);
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    check_ieee_exceptions();
106
}
107

    
108
void do_fsqrtd(void)
109
{
110
    set_float_exception_flags(0, &env->fp_status);
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    DT0 = float64_sqrt(DT1, &env->fp_status);
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    check_ieee_exceptions();
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}
114

    
115
#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP)                      \
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    void glue(do_, name) (void)                                         \
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    {                                                                   \
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        env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \
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        switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
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        case float_relation_unordered:                                  \
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            T0 = (FSR_FCC1 | FSR_FCC0) << FS;                           \
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            if ((env->fsr & FSR_NVM) || TRAP) {                         \
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                env->fsr |= T0;                                         \
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                env->fsr |= FSR_NVC;                                    \
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                env->fsr |= FSR_FTT_IEEE_EXCP;                          \
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                raise_exception(TT_FP_EXCP);                            \
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            } else {                                                    \
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                env->fsr |= FSR_NVA;                                    \
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            }                                                           \
130
            break;                                                      \
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        case float_relation_less:                                       \
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            T0 = FSR_FCC0 << FS;                                        \
133
            break;                                                      \
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        case float_relation_greater:                                    \
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            T0 = FSR_FCC1 << FS;                                        \
136
            break;                                                      \
137
        default:                                                        \
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            T0 = 0;                                                     \
139
            break;                                                      \
140
        }                                                               \
141
        env->fsr |= T0;                                                 \
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    }
143

    
144
GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
145
GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
146

    
147
GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
148
GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
149

    
150
#ifdef TARGET_SPARC64
151
GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
152
GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
153

    
154
GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
156

    
157
GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
158
GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
159

    
160
GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
161
GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
162

    
163
GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
164
GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
165

    
166
GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
167
GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
168
#endif
169

    
170
#ifndef TARGET_SPARC64
171
#ifndef CONFIG_USER_ONLY
172

    
173
#ifdef DEBUG_MXCC
174
static void dump_mxcc(CPUState *env)
175
{
176
    printf("mxccdata: %016llx %016llx %016llx %016llx\n",
177
        env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
178
    printf("mxccregs: %016llx %016llx %016llx %016llx\n"
179
           "          %016llx %016llx %016llx %016llx\n",
180
        env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
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        env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
182
}
183
#endif
184

    
185
void helper_ld_asi(int asi, int size, int sign)
186
{
187
    uint32_t ret = 0;
188
    uint64_t tmp;
189
#ifdef DEBUG_MXCC
190
    uint32_t last_T0 = T0;
191
#endif
192

    
193
    switch (asi) {
194
    case 2: /* SuperSparc MXCC registers */
195
        switch (T0) {
196
        case 0x01c00a00: /* MXCC control register */
197
            if (size == 8) {
198
                ret = env->mxccregs[3];
199
                T0 = env->mxccregs[3] >> 32;
200
            } else
201
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
202
            break;
203
        case 0x01c00a04: /* MXCC control register */
204
            if (size == 4)
205
                ret = env->mxccregs[3];
206
            else
207
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
208
            break;
209
        case 0x01c00f00: /* MBus port address register */
210
            if (size == 8) {
211
                ret = env->mxccregs[7];
212
                T0 = env->mxccregs[7] >> 32;
213
            } else
214
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
215
            break;
216
        default:
217
            DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
218
            break;
219
        }
220
        DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
221
                     "T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
222
#ifdef DEBUG_MXCC
223
        dump_mxcc(env);
224
#endif
225
        break;
226
    case 3: /* MMU probe */
227
        {
228
            int mmulev;
229

    
230
            mmulev = (T0 >> 8) & 15;
231
            if (mmulev > 4)
232
                ret = 0;
233
            else {
234
                ret = mmu_probe(env, T0, mmulev);
235
                //bswap32s(&ret);
236
            }
237
            DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
238
        }
239
        break;
240
    case 4: /* read MMU regs */
241
        {
242
            int reg = (T0 >> 8) & 0xf;
243

    
244
            ret = env->mmuregs[reg];
245
            if (reg == 3) /* Fault status cleared on read */
246
                env->mmuregs[reg] = 0;
247
            DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
248
        }
249
        break;
250
    case 9: /* Supervisor code access */
251
        switch(size) {
252
        case 1:
253
            ret = ldub_code(T0);
254
            break;
255
        case 2:
256
            ret = lduw_code(T0 & ~1);
257
            break;
258
        default:
259
        case 4:
260
            ret = ldl_code(T0 & ~3);
261
            break;
262
        case 8:
263
            tmp = ldq_code(T0 & ~7);
264
            ret = tmp >> 32;
265
            T0 = tmp & 0xffffffff;
266
            break;
267
        }
268
        break;
269
    case 0xa: /* User data access */
270
        switch(size) {
271
        case 1:
272
            ret = ldub_user(T0);
273
            break;
274
        case 2:
275
            ret = lduw_user(T0 & ~1);
276
            break;
277
        default:
278
        case 4:
279
            ret = ldl_user(T0 & ~3);
280
            break;
281
        case 8:
282
            tmp = ldq_user(T0 & ~7);
283
            ret = tmp >> 32;
284
            T0 = tmp & 0xffffffff;
285
            break;
286
        }
287
        break;
288
    case 0xb: /* Supervisor data access */
289
        switch(size) {
290
        case 1:
291
            ret = ldub_kernel(T0);
292
            break;
293
        case 2:
294
            ret = lduw_kernel(T0 & ~1);
295
            break;
296
        default:
297
        case 4:
298
            ret = ldl_kernel(T0 & ~3);
299
            break;
300
        case 8:
301
            tmp = ldq_kernel(T0 & ~7);
302
            ret = tmp >> 32;
303
            T0 = tmp & 0xffffffff;
304
            break;
305
        }
306
        break;
307
    case 0xc: /* I-cache tag */
308
    case 0xd: /* I-cache data */
309
    case 0xe: /* D-cache tag */
310
    case 0xf: /* D-cache data */
311
        break;
312
    case 0x20: /* MMU passthrough */
313
        switch(size) {
314
        case 1:
315
            ret = ldub_phys(T0);
316
            break;
317
        case 2:
318
            ret = lduw_phys(T0 & ~1);
319
            break;
320
        default:
321
        case 4:
322
            ret = ldl_phys(T0 & ~3);
323
            break;
324
        case 8:
325
            tmp = ldq_phys(T0 & ~7);
326
            ret = tmp >> 32;
327
            T0 = tmp & 0xffffffff;
328
            break;
329
        }
330
        break;
331
    case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
332
    case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
333
        switch(size) {
334
        case 1:
335
            ret = ldub_phys((target_phys_addr_t)T0
336
                            | ((target_phys_addr_t)(asi & 0xf) << 32));
337
            break;
338
        case 2:
339
            ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
340
                            | ((target_phys_addr_t)(asi & 0xf) << 32));
341
            break;
342
        default:
343
        case 4:
344
            ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
345
                           | ((target_phys_addr_t)(asi & 0xf) << 32));
346
            break;
347
        case 8:
348
            tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
349
                           | ((target_phys_addr_t)(asi & 0xf) << 32));
350
            ret = tmp >> 32;
351
            T0 = tmp & 0xffffffff;
352
            break;
353
        }
354
        break;
355
    case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
356
    default:
357
        do_unassigned_access(T0, 0, 0, 1);
358
        ret = 0;
359
        break;
360
    }
361
    if (sign) {
362
        switch(size) {
363
        case 1:
364
            T1 = (int8_t) ret;
365
            break;
366
        case 2:
367
            T1 = (int16_t) ret;
368
            break;
369
        default:
370
            T1 = ret;
371
            break;
372
        }
373
    }
374
    else
375
        T1 = ret;
376
}
377

    
378
void helper_st_asi(int asi, int size)
379
{
380
    switch(asi) {
381
    case 2: /* SuperSparc MXCC registers */
382
        switch (T0) {
383
        case 0x01c00000: /* MXCC stream data register 0 */
384
            if (size == 8)
385
                env->mxccdata[0] = ((uint64_t)T1 << 32) | T2;
386
            else
387
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
388
            break;
389
        case 0x01c00008: /* MXCC stream data register 1 */
390
            if (size == 8)
391
                env->mxccdata[1] = ((uint64_t)T1 << 32) | T2;
392
            else
393
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
394
            break;
395
        case 0x01c00010: /* MXCC stream data register 2 */
396
            if (size == 8)
397
                env->mxccdata[2] = ((uint64_t)T1 << 32) | T2;
398
            else
399
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
400
            break;
401
        case 0x01c00018: /* MXCC stream data register 3 */
402
            if (size == 8)
403
                env->mxccdata[3] = ((uint64_t)T1 << 32) | T2;
404
            else
405
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
406
            break;
407
        case 0x01c00100: /* MXCC stream source */
408
            if (size == 8)
409
                env->mxccregs[0] = ((uint64_t)T1 << 32) | T2;
410
            else
411
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
412
            env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +  0);
413
            env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +  8);
414
            env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
415
            env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
416
            break;
417
        case 0x01c00200: /* MXCC stream destination */
418
            if (size == 8)
419
                env->mxccregs[1] = ((uint64_t)T1 << 32) | T2;
420
            else
421
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
422
            stq_phys((env->mxccregs[1] & 0xffffffffULL) +  0, env->mxccdata[0]);
423
            stq_phys((env->mxccregs[1] & 0xffffffffULL) +  8, env->mxccdata[1]);
424
            stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
425
            stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
426
            break;
427
        case 0x01c00a00: /* MXCC control register */
428
            if (size == 8)
429
                env->mxccregs[3] = ((uint64_t)T1 << 32) | T2;
430
            else
431
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
432
            break;
433
        case 0x01c00a04: /* MXCC control register */
434
            if (size == 4)
435
                env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000) | T1;
436
            else
437
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
438
            break;
439
        case 0x01c00e00: /* MXCC error register  */
440
            if (size == 8)
441
                env->mxccregs[6] = ((uint64_t)T1 << 32) | T2;
442
            else
443
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
444
            if (env->mxccregs[6] == 0xffffffffffffffffULL) {
445
                // this is probably a reset
446
            }
447
            break;
448
        case 0x01c00f00: /* MBus port address register */
449
            if (size == 8)
450
                env->mxccregs[7] = ((uint64_t)T1 << 32) | T2;
451
            else
452
                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
453
            break;
454
        default:
455
            DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
456
            break;
457
        }
458
        DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
459
#ifdef DEBUG_MXCC
460
        dump_mxcc(env);
461
#endif
462
        break;
463
    case 3: /* MMU flush */
464
        {
465
            int mmulev;
466

    
467
            mmulev = (T0 >> 8) & 15;
468
            DPRINTF_MMU("mmu flush level %d\n", mmulev);
469
            switch (mmulev) {
470
            case 0: // flush page
471
                tlb_flush_page(env, T0 & 0xfffff000);
472
                break;
473
            case 1: // flush segment (256k)
474
            case 2: // flush region (16M)
475
            case 3: // flush context (4G)
476
            case 4: // flush entire
477
                tlb_flush(env, 1);
478
                break;
479
            default:
480
                break;
481
            }
482
#ifdef DEBUG_MMU
483
            dump_mmu(env);
484
#endif
485
            return;
486
        }
487
    case 4: /* write MMU regs */
488
        {
489
            int reg = (T0 >> 8) & 0xf;
490
            uint32_t oldreg;
491

    
492
            oldreg = env->mmuregs[reg];
493
            switch(reg) {
494
            case 0:
495
                env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM);
496
                env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM);
497
                // Mappings generated during no-fault mode or MMU
498
                // disabled mode are invalid in normal mode
499
                if (oldreg != env->mmuregs[reg])
500
                    tlb_flush(env, 1);
501
                break;
502
            case 2:
503
                env->mmuregs[reg] = T1;
504
                if (oldreg != env->mmuregs[reg]) {
505
                    /* we flush when the MMU context changes because
506
                       QEMU has no MMU context support */
507
                    tlb_flush(env, 1);
508
                }
509
                break;
510
            case 3:
511
            case 4:
512
                break;
513
            default:
514
                env->mmuregs[reg] = T1;
515
                break;
516
            }
517
            if (oldreg != env->mmuregs[reg]) {
518
                DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
519
            }
520
#ifdef DEBUG_MMU
521
            dump_mmu(env);
522
#endif
523
            return;
524
        }
525
    case 0xa: /* User data access */
526
        switch(size) {
527
        case 1:
528
            stb_user(T0, T1);
529
            break;
530
        case 2:
531
            stw_user(T0 & ~1, T1);
532
            break;
533
        default:
534
        case 4:
535
            stl_user(T0 & ~3, T1);
536
            break;
537
        case 8:
538
            stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2);
539
            break;
540
        }
541
        break;
542
    case 0xb: /* Supervisor data access */
543
        switch(size) {
544
        case 1:
545
            stb_kernel(T0, T1);
546
            break;
547
        case 2:
548
            stw_kernel(T0 & ~1, T1);
549
            break;
550
        default:
551
        case 4:
552
            stl_kernel(T0 & ~3, T1);
553
            break;
554
        case 8:
555
            stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2);
556
            break;
557
        }
558
        break;
559
    case 0xc: /* I-cache tag */
560
    case 0xd: /* I-cache data */
561
    case 0xe: /* D-cache tag */
562
    case 0xf: /* D-cache data */
563
    case 0x10: /* I/D-cache flush page */
564
    case 0x11: /* I/D-cache flush segment */
565
    case 0x12: /* I/D-cache flush region */
566
    case 0x13: /* I/D-cache flush context */
567
    case 0x14: /* I/D-cache flush user */
568
        break;
569
    case 0x17: /* Block copy, sta access */
570
        {
571
            // value (T1) = src
572
            // address (T0) = dst
573
            // copy 32 bytes
574
            unsigned int i;
575
            uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
576

    
577
            for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
578
                temp = ldl_kernel(src);
579
                stl_kernel(dst, temp);
580
            }
581
        }
582
        return;
583
    case 0x1f: /* Block fill, stda access */
584
        {
585
            // value (T1, T2)
586
            // address (T0) = dst
587
            // fill 32 bytes
588
            unsigned int i;
589
            uint32_t dst = T0 & 7;
590
            uint64_t val;
591

    
592
            val = (((uint64_t)T1) << 32) | T2;
593

    
594
            for (i = 0; i < 32; i += 8, dst += 8)
595
                stq_kernel(dst, val);
596
        }
597
        return;
598
    case 0x20: /* MMU passthrough */
599
        {
600
            switch(size) {
601
            case 1:
602
                stb_phys(T0, T1);
603
                break;
604
            case 2:
605
                stw_phys(T0 & ~1, T1);
606
                break;
607
            case 4:
608
            default:
609
                stl_phys(T0 & ~3, T1);
610
                break;
611
            case 8:
612
                stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2);
613
                break;
614
            }
615
        }
616
        return;
617
    case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
618
    case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
619
        {
620
            switch(size) {
621
            case 1:
622
                stb_phys((target_phys_addr_t)T0
623
                         | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
624
                break;
625
            case 2:
626
                stw_phys((target_phys_addr_t)(T0 & ~1)
627
                            | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
628
                break;
629
            case 4:
630
            default:
631
                stl_phys((target_phys_addr_t)(T0 & ~3)
632
                           | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
633
                break;
634
            case 8:
635
                stq_phys((target_phys_addr_t)(T0 & ~7)
636
                           | ((target_phys_addr_t)(asi & 0xf) << 32),
637
                         ((uint64_t)T1 << 32) | T2);
638
                break;
639
            }
640
        }
641
        return;
642
    case 0x31: /* Ross RT620 I-cache flush */
643
    case 0x36: /* I-cache flash clear */
644
    case 0x37: /* D-cache flash clear */
645
        break;
646
    case 9: /* Supervisor code access, XXX */
647
    case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
648
    default:
649
        do_unassigned_access(T0, 1, 0, 1);
650
        return;
651
    }
652
}
653

    
654
#endif /* CONFIG_USER_ONLY */
655
#else /* TARGET_SPARC64 */
656

    
657
#ifdef CONFIG_USER_ONLY
658
void helper_ld_asi(int asi, int size, int sign)
659
{
660
    uint64_t ret = 0;
661

    
662
    if (asi < 0x80)
663
        raise_exception(TT_PRIV_ACT);
664

    
665
    switch (asi) {
666
    case 0x80: // Primary
667
    case 0x82: // Primary no-fault
668
    case 0x88: // Primary LE
669
    case 0x8a: // Primary no-fault LE
670
        {
671
            switch(size) {
672
            case 1:
673
                ret = ldub_raw(T0);
674
                break;
675
            case 2:
676
                ret = lduw_raw(T0 & ~1);
677
                break;
678
            case 4:
679
                ret = ldl_raw(T0 & ~3);
680
                break;
681
            default:
682
            case 8:
683
                ret = ldq_raw(T0 & ~7);
684
                break;
685
            }
686
        }
687
        break;
688
    case 0x81: // Secondary
689
    case 0x83: // Secondary no-fault
690
    case 0x89: // Secondary LE
691
    case 0x8b: // Secondary no-fault LE
692
        // XXX
693
        break;
694
    default:
695
        break;
696
    }
697

    
698
    /* Convert from little endian */
699
    switch (asi) {
700
    case 0x88: // Primary LE
701
    case 0x89: // Secondary LE
702
    case 0x8a: // Primary no-fault LE
703
    case 0x8b: // Secondary no-fault LE
704
        switch(size) {
705
        case 2:
706
            ret = bswap16(ret);
707
            break;
708
        case 4:
709
            ret = bswap32(ret);
710
            break;
711
        case 8:
712
            ret = bswap64(ret);
713
            break;
714
        default:
715
            break;
716
        }
717
    default:
718
        break;
719
    }
720

    
721
    /* Convert to signed number */
722
    if (sign) {
723
        switch(size) {
724
        case 1:
725
            ret = (int8_t) ret;
726
            break;
727
        case 2:
728
            ret = (int16_t) ret;
729
            break;
730
        case 4:
731
            ret = (int32_t) ret;
732
            break;
733
        default:
734
            break;
735
        }
736
    }
737
    T1 = ret;
738
}
739

    
740
void helper_st_asi(int asi, int size)
741
{
742
    if (asi < 0x80)
743
        raise_exception(TT_PRIV_ACT);
744

    
745
    /* Convert to little endian */
746
    switch (asi) {
747
    case 0x88: // Primary LE
748
    case 0x89: // Secondary LE
749
        switch(size) {
750
        case 2:
751
            T0 = bswap16(T0);
752
            break;
753
        case 4:
754
            T0 = bswap32(T0);
755
            break;
756
        case 8:
757
            T0 = bswap64(T0);
758
            break;
759
        default:
760
            break;
761
        }
762
    default:
763
        break;
764
    }
765

    
766
    switch(asi) {
767
    case 0x80: // Primary
768
    case 0x88: // Primary LE
769
        {
770
            switch(size) {
771
            case 1:
772
                stb_raw(T0, T1);
773
                break;
774
            case 2:
775
                stw_raw(T0 & ~1, T1);
776
                break;
777
            case 4:
778
                stl_raw(T0 & ~3, T1);
779
                break;
780
            case 8:
781
            default:
782
                stq_raw(T0 & ~7, T1);
783
                break;
784
            }
785
        }
786
        break;
787
    case 0x81: // Secondary
788
    case 0x89: // Secondary LE
789
        // XXX
790
        return;
791

    
792
    case 0x82: // Primary no-fault, RO
793
    case 0x83: // Secondary no-fault, RO
794
    case 0x8a: // Primary no-fault LE, RO
795
    case 0x8b: // Secondary no-fault LE, RO
796
    default:
797
        do_unassigned_access(T0, 1, 0, 1);
798
        return;
799
    }
800
}
801

    
802
#else /* CONFIG_USER_ONLY */
803

    
804
void helper_ld_asi(int asi, int size, int sign)
805
{
806
    uint64_t ret = 0;
807

    
808
    if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
809
        || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
810
        raise_exception(TT_PRIV_ACT);
811

    
812
    switch (asi) {
813
    case 0x10: // As if user primary
814
    case 0x18: // As if user primary LE
815
    case 0x80: // Primary
816
    case 0x82: // Primary no-fault
817
    case 0x88: // Primary LE
818
    case 0x8a: // Primary no-fault LE
819
        if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
820
            if (env->hpstate & HS_PRIV) {
821
                switch(size) {
822
                case 1:
823
                    ret = ldub_hypv(T0);
824
                    break;
825
                case 2:
826
                    ret = lduw_hypv(T0 & ~1);
827
                    break;
828
                case 4:
829
                    ret = ldl_hypv(T0 & ~3);
830
                    break;
831
                default:
832
                case 8:
833
                    ret = ldq_hypv(T0 & ~7);
834
                    break;
835
                }
836
            } else {
837
                switch(size) {
838
                case 1:
839
                    ret = ldub_kernel(T0);
840
                    break;
841
                case 2:
842
                    ret = lduw_kernel(T0 & ~1);
843
                    break;
844
                case 4:
845
                    ret = ldl_kernel(T0 & ~3);
846
                    break;
847
                default:
848
                case 8:
849
                    ret = ldq_kernel(T0 & ~7);
850
                    break;
851
                }
852
            }
853
        } else {
854
            switch(size) {
855
            case 1:
856
                ret = ldub_user(T0);
857
                break;
858
            case 2:
859
                ret = lduw_user(T0 & ~1);
860
                break;
861
            case 4:
862
                ret = ldl_user(T0 & ~3);
863
                break;
864
            default:
865
            case 8:
866
                ret = ldq_user(T0 & ~7);
867
                break;
868
            }
869
        }
870
        break;
871
    case 0x14: // Bypass
872
    case 0x15: // Bypass, non-cacheable
873
    case 0x1c: // Bypass LE
874
    case 0x1d: // Bypass, non-cacheable LE
875
        {
876
            switch(size) {
877
            case 1:
878
                ret = ldub_phys(T0);
879
                break;
880
            case 2:
881
                ret = lduw_phys(T0 & ~1);
882
                break;
883
            case 4:
884
                ret = ldl_phys(T0 & ~3);
885
                break;
886
            default:
887
            case 8:
888
                ret = ldq_phys(T0 & ~7);
889
                break;
890
            }
891
            break;
892
        }
893
    case 0x04: // Nucleus
894
    case 0x0c: // Nucleus Little Endian (LE)
895
    case 0x11: // As if user secondary
896
    case 0x19: // As if user secondary LE
897
    case 0x24: // Nucleus quad LDD 128 bit atomic
898
    case 0x2c: // Nucleus quad LDD 128 bit atomic
899
    case 0x4a: // UPA config
900
    case 0x81: // Secondary
901
    case 0x83: // Secondary no-fault
902
    case 0x89: // Secondary LE
903
    case 0x8b: // Secondary no-fault LE
904
        // XXX
905
        break;
906
    case 0x45: // LSU
907
        ret = env->lsu;
908
        break;
909
    case 0x50: // I-MMU regs
910
        {
911
            int reg = (T0 >> 3) & 0xf;
912

    
913
            ret = env->immuregs[reg];
914
            break;
915
        }
916
    case 0x51: // I-MMU 8k TSB pointer
917
    case 0x52: // I-MMU 64k TSB pointer
918
    case 0x55: // I-MMU data access
919
        // XXX
920
        break;
921
    case 0x56: // I-MMU tag read
922
        {
923
            unsigned int i;
924

    
925
            for (i = 0; i < 64; i++) {
926
                // Valid, ctx match, vaddr match
927
                if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
928
                    env->itlb_tag[i] == T0) {
929
                    ret = env->itlb_tag[i];
930
                    break;
931
                }
932
            }
933
            break;
934
        }
935
    case 0x58: // D-MMU regs
936
        {
937
            int reg = (T0 >> 3) & 0xf;
938

    
939
            ret = env->dmmuregs[reg];
940
            break;
941
        }
942
    case 0x5e: // D-MMU tag read
943
        {
944
            unsigned int i;
945

    
946
            for (i = 0; i < 64; i++) {
947
                // Valid, ctx match, vaddr match
948
                if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
949
                    env->dtlb_tag[i] == T0) {
950
                    ret = env->dtlb_tag[i];
951
                    break;
952
                }
953
            }
954
            break;
955
        }
956
    case 0x59: // D-MMU 8k TSB pointer
957
    case 0x5a: // D-MMU 64k TSB pointer
958
    case 0x5b: // D-MMU data pointer
959
    case 0x5d: // D-MMU data access
960
    case 0x48: // Interrupt dispatch, RO
961
    case 0x49: // Interrupt data receive
962
    case 0x7f: // Incoming interrupt vector, RO
963
        // XXX
964
        break;
965
    case 0x54: // I-MMU data in, WO
966
    case 0x57: // I-MMU demap, WO
967
    case 0x5c: // D-MMU data in, WO
968
    case 0x5f: // D-MMU demap, WO
969
    case 0x77: // Interrupt vector, WO
970
    default:
971
        do_unassigned_access(T0, 0, 0, 1);
972
        ret = 0;
973
        break;
974
    }
975

    
976
    /* Convert from little endian */
977
    switch (asi) {
978
    case 0x0c: // Nucleus Little Endian (LE)
979
    case 0x18: // As if user primary LE
980
    case 0x19: // As if user secondary LE
981
    case 0x1c: // Bypass LE
982
    case 0x1d: // Bypass, non-cacheable LE
983
    case 0x88: // Primary LE
984
    case 0x89: // Secondary LE
985
    case 0x8a: // Primary no-fault LE
986
    case 0x8b: // Secondary no-fault LE
987
        switch(size) {
988
        case 2:
989
            ret = bswap16(ret);
990
            break;
991
        case 4:
992
            ret = bswap32(ret);
993
            break;
994
        case 8:
995
            ret = bswap64(ret);
996
            break;
997
        default:
998
            break;
999
        }
1000
    default:
1001
        break;
1002
    }
1003

    
1004
    /* Convert to signed number */
1005
    if (sign) {
1006
        switch(size) {
1007
        case 1:
1008
            ret = (int8_t) ret;
1009
            break;
1010
        case 2:
1011
            ret = (int16_t) ret;
1012
            break;
1013
        case 4:
1014
            ret = (int32_t) ret;
1015
            break;
1016
        default:
1017
            break;
1018
        }
1019
    }
1020
    T1 = ret;
1021
}
1022

    
1023
void helper_st_asi(int asi, int size)
1024
{
1025
    if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1026
        || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
1027
        raise_exception(TT_PRIV_ACT);
1028

    
1029
    /* Convert to little endian */
1030
    switch (asi) {
1031
    case 0x0c: // Nucleus Little Endian (LE)
1032
    case 0x18: // As if user primary LE
1033
    case 0x19: // As if user secondary LE
1034
    case 0x1c: // Bypass LE
1035
    case 0x1d: // Bypass, non-cacheable LE
1036
    case 0x88: // Primary LE
1037
    case 0x89: // Secondary LE
1038
        switch(size) {
1039
        case 2:
1040
            T0 = bswap16(T0);
1041
            break;
1042
        case 4:
1043
            T0 = bswap32(T0);
1044
            break;
1045
        case 8:
1046
            T0 = bswap64(T0);
1047
            break;
1048
        default:
1049
            break;
1050
        }
1051
    default:
1052
        break;
1053
    }
1054

    
1055
    switch(asi) {
1056
    case 0x10: // As if user primary
1057
    case 0x18: // As if user primary LE
1058
    case 0x80: // Primary
1059
    case 0x88: // Primary LE
1060
        if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1061
            if (env->hpstate & HS_PRIV) {
1062
                switch(size) {
1063
                case 1:
1064
                    stb_hypv(T0, T1);
1065
                    break;
1066
                case 2:
1067
                    stw_hypv(T0 & ~1, T1);
1068
                    break;
1069
                case 4:
1070
                    stl_hypv(T0 & ~3, T1);
1071
                    break;
1072
                case 8:
1073
                default:
1074
                    stq_hypv(T0 & ~7, T1);
1075
                    break;
1076
                }
1077
            } else {
1078
                switch(size) {
1079
                case 1:
1080
                    stb_kernel(T0, T1);
1081
                    break;
1082
                case 2:
1083
                    stw_kernel(T0 & ~1, T1);
1084
                    break;
1085
                case 4:
1086
                    stl_kernel(T0 & ~3, T1);
1087
                    break;
1088
                case 8:
1089
                default:
1090
                    stq_kernel(T0 & ~7, T1);
1091
                    break;
1092
                }
1093
            }
1094
        } else {
1095
            switch(size) {
1096
            case 1:
1097
                stb_user(T0, T1);
1098
                break;
1099
            case 2:
1100
                stw_user(T0 & ~1, T1);
1101
                break;
1102
            case 4:
1103
                stl_user(T0 & ~3, T1);
1104
                break;
1105
            case 8:
1106
            default:
1107
                stq_user(T0 & ~7, T1);
1108
                break;
1109
            }
1110
        }
1111
        break;
1112
    case 0x14: // Bypass
1113
    case 0x15: // Bypass, non-cacheable
1114
    case 0x1c: // Bypass LE
1115
    case 0x1d: // Bypass, non-cacheable LE
1116
        {
1117
            switch(size) {
1118
            case 1:
1119
                stb_phys(T0, T1);
1120
                break;
1121
            case 2:
1122
                stw_phys(T0 & ~1, T1);
1123
                break;
1124
            case 4:
1125
                stl_phys(T0 & ~3, T1);
1126
                break;
1127
            case 8:
1128
            default:
1129
                stq_phys(T0 & ~7, T1);
1130
                break;
1131
            }
1132
        }
1133
        return;
1134
    case 0x04: // Nucleus
1135
    case 0x0c: // Nucleus Little Endian (LE)
1136
    case 0x11: // As if user secondary
1137
    case 0x19: // As if user secondary LE
1138
    case 0x24: // Nucleus quad LDD 128 bit atomic
1139
    case 0x2c: // Nucleus quad LDD 128 bit atomic
1140
    case 0x4a: // UPA config
1141
    case 0x81: // Secondary
1142
    case 0x89: // Secondary LE
1143
        // XXX
1144
        return;
1145
    case 0x45: // LSU
1146
        {
1147
            uint64_t oldreg;
1148

    
1149
            oldreg = env->lsu;
1150
            env->lsu = T1 & (DMMU_E | IMMU_E);
1151
            // Mappings generated during D/I MMU disabled mode are
1152
            // invalid in normal mode
1153
            if (oldreg != env->lsu) {
1154
                DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
1155
#ifdef DEBUG_MMU
1156
                dump_mmu(env);
1157
#endif
1158
                tlb_flush(env, 1);
1159
            }
1160
            return;
1161
        }
1162
    case 0x50: // I-MMU regs
1163
        {
1164
            int reg = (T0 >> 3) & 0xf;
1165
            uint64_t oldreg;
1166

    
1167
            oldreg = env->immuregs[reg];
1168
            switch(reg) {
1169
            case 0: // RO
1170
            case 4:
1171
                return;
1172
            case 1: // Not in I-MMU
1173
            case 2:
1174
            case 7:
1175
            case 8:
1176
                return;
1177
            case 3: // SFSR
1178
                if ((T1 & 1) == 0)
1179
                    T1 = 0; // Clear SFSR
1180
                break;
1181
            case 5: // TSB access
1182
            case 6: // Tag access
1183
            default:
1184
                break;
1185
            }
1186
            env->immuregs[reg] = T1;
1187
            if (oldreg != env->immuregs[reg]) {
1188
                DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1189
            }
1190
#ifdef DEBUG_MMU
1191
            dump_mmu(env);
1192
#endif
1193
            return;
1194
        }
1195
    case 0x54: // I-MMU data in
1196
        {
1197
            unsigned int i;
1198

    
1199
            // Try finding an invalid entry
1200
            for (i = 0; i < 64; i++) {
1201
                if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1202
                    env->itlb_tag[i] = env->immuregs[6];
1203
                    env->itlb_tte[i] = T1;
1204
                    return;
1205
                }
1206
            }
1207
            // Try finding an unlocked entry
1208
            for (i = 0; i < 64; i++) {
1209
                if ((env->itlb_tte[i] & 0x40) == 0) {
1210
                    env->itlb_tag[i] = env->immuregs[6];
1211
                    env->itlb_tte[i] = T1;
1212
                    return;
1213
                }
1214
            }
1215
            // error state?
1216
            return;
1217
        }
1218
    case 0x55: // I-MMU data access
1219
        {
1220
            unsigned int i = (T0 >> 3) & 0x3f;
1221

    
1222
            env->itlb_tag[i] = env->immuregs[6];
1223
            env->itlb_tte[i] = T1;
1224
            return;
1225
        }
1226
    case 0x57: // I-MMU demap
1227
        // XXX
1228
        return;
1229
    case 0x58: // D-MMU regs
1230
        {
1231
            int reg = (T0 >> 3) & 0xf;
1232
            uint64_t oldreg;
1233

    
1234
            oldreg = env->dmmuregs[reg];
1235
            switch(reg) {
1236
            case 0: // RO
1237
            case 4:
1238
                return;
1239
            case 3: // SFSR
1240
                if ((T1 & 1) == 0) {
1241
                    T1 = 0; // Clear SFSR, Fault address
1242
                    env->dmmuregs[4] = 0;
1243
                }
1244
                env->dmmuregs[reg] = T1;
1245
                break;
1246
            case 1: // Primary context
1247
            case 2: // Secondary context
1248
            case 5: // TSB access
1249
            case 6: // Tag access
1250
            case 7: // Virtual Watchpoint
1251
            case 8: // Physical Watchpoint
1252
            default:
1253
                break;
1254
            }
1255
            env->dmmuregs[reg] = T1;
1256
            if (oldreg != env->dmmuregs[reg]) {
1257
                DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1258
            }
1259
#ifdef DEBUG_MMU
1260
            dump_mmu(env);
1261
#endif
1262
            return;
1263
        }
1264
    case 0x5c: // D-MMU data in
1265
        {
1266
            unsigned int i;
1267

    
1268
            // Try finding an invalid entry
1269
            for (i = 0; i < 64; i++) {
1270
                if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1271
                    env->dtlb_tag[i] = env->dmmuregs[6];
1272
                    env->dtlb_tte[i] = T1;
1273
                    return;
1274
                }
1275
            }
1276
            // Try finding an unlocked entry
1277
            for (i = 0; i < 64; i++) {
1278
                if ((env->dtlb_tte[i] & 0x40) == 0) {
1279
                    env->dtlb_tag[i] = env->dmmuregs[6];
1280
                    env->dtlb_tte[i] = T1;
1281
                    return;
1282
                }
1283
            }
1284
            // error state?
1285
            return;
1286
        }
1287
    case 0x5d: // D-MMU data access
1288
        {
1289
            unsigned int i = (T0 >> 3) & 0x3f;
1290

    
1291
            env->dtlb_tag[i] = env->dmmuregs[6];
1292
            env->dtlb_tte[i] = T1;
1293
            return;
1294
        }
1295
    case 0x5f: // D-MMU demap
1296
    case 0x49: // Interrupt data receive
1297
        // XXX
1298
        return;
1299
    case 0x51: // I-MMU 8k TSB pointer, RO
1300
    case 0x52: // I-MMU 64k TSB pointer, RO
1301
    case 0x56: // I-MMU tag read, RO
1302
    case 0x59: // D-MMU 8k TSB pointer, RO
1303
    case 0x5a: // D-MMU 64k TSB pointer, RO
1304
    case 0x5b: // D-MMU data pointer, RO
1305
    case 0x5e: // D-MMU tag read, RO
1306
    case 0x48: // Interrupt dispatch, RO
1307
    case 0x7f: // Incoming interrupt vector, RO
1308
    case 0x82: // Primary no-fault, RO
1309
    case 0x83: // Secondary no-fault, RO
1310
    case 0x8a: // Primary no-fault LE, RO
1311
    case 0x8b: // Secondary no-fault LE, RO
1312
    default:
1313
        do_unassigned_access(T0, 1, 0, 1);
1314
        return;
1315
    }
1316
}
1317
#endif /* CONFIG_USER_ONLY */
1318

    
1319
void helper_ldf_asi(int asi, int size, int rd)
1320
{
1321
    target_ulong tmp_T0 = T0, tmp_T1 = T1;
1322
    unsigned int i;
1323

    
1324
    switch (asi) {
1325
    case 0xf0: // Block load primary
1326
    case 0xf1: // Block load secondary
1327
    case 0xf8: // Block load primary LE
1328
    case 0xf9: // Block load secondary LE
1329
        if (rd & 7) {
1330
            raise_exception(TT_ILL_INSN);
1331
            return;
1332
        }
1333
        if (T0 & 0x3f) {
1334
            raise_exception(TT_UNALIGNED);
1335
            return;
1336
        }
1337
        for (i = 0; i < 16; i++) {
1338
            helper_ld_asi(asi & 0x8f, 4, 0);
1339
            *(uint32_t *)&env->fpr[rd++] = T1;
1340
            T0 += 4;
1341
        }
1342
        T0 = tmp_T0;
1343
        T1 = tmp_T1;
1344

    
1345
        return;
1346
    default:
1347
        break;
1348
    }
1349

    
1350
    helper_ld_asi(asi, size, 0);
1351
    switch(size) {
1352
    default:
1353
    case 4:
1354
        *((uint32_t *)&FT0) = T1;
1355
        break;
1356
    case 8:
1357
        *((int64_t *)&DT0) = T1;
1358
        break;
1359
    }
1360
    T1 = tmp_T1;
1361
}
1362

    
1363
void helper_stf_asi(int asi, int size, int rd)
1364
{
1365
    target_ulong tmp_T0 = T0, tmp_T1 = T1;
1366
    unsigned int i;
1367

    
1368
    switch (asi) {
1369
    case 0xf0: // Block store primary
1370
    case 0xf1: // Block store secondary
1371
    case 0xf8: // Block store primary LE
1372
    case 0xf9: // Block store secondary LE
1373
        if (rd & 7) {
1374
            raise_exception(TT_ILL_INSN);
1375
            return;
1376
        }
1377
        if (T0 & 0x3f) {
1378
            raise_exception(TT_UNALIGNED);
1379
            return;
1380
        }
1381
        for (i = 0; i < 16; i++) {
1382
            T1 = *(uint32_t *)&env->fpr[rd++];
1383
            helper_st_asi(asi & 0x8f, 4);
1384
            T0 += 4;
1385
        }
1386
        T0 = tmp_T0;
1387
        T1 = tmp_T1;
1388

    
1389
        return;
1390
    default:
1391
        break;
1392
    }
1393

    
1394
    switch(size) {
1395
    default:
1396
    case 4:
1397
        T1 = *((uint32_t *)&FT0);
1398
        break;
1399
    case 8:
1400
        T1 = *((int64_t *)&DT0);
1401
        break;
1402
    }
1403
    helper_st_asi(asi, size);
1404
    T1 = tmp_T1;
1405
}
1406

    
1407
#endif /* TARGET_SPARC64 */
1408

    
1409
#ifndef TARGET_SPARC64
1410
void helper_rett()
1411
{
1412
    unsigned int cwp;
1413

    
1414
    if (env->psret == 1)
1415
        raise_exception(TT_ILL_INSN);
1416

    
1417
    env->psret = 1;
1418
    cwp = (env->cwp + 1) & (NWINDOWS - 1);
1419
    if (env->wim & (1 << cwp)) {
1420
        raise_exception(TT_WIN_UNF);
1421
    }
1422
    set_cwp(cwp);
1423
    env->psrs = env->psrps;
1424
}
1425
#endif
1426

    
1427
void helper_ldfsr(void)
1428
{
1429
    int rnd_mode;
1430
    switch (env->fsr & FSR_RD_MASK) {
1431
    case FSR_RD_NEAREST:
1432
        rnd_mode = float_round_nearest_even;
1433
        break;
1434
    default:
1435
    case FSR_RD_ZERO:
1436
        rnd_mode = float_round_to_zero;
1437
        break;
1438
    case FSR_RD_POS:
1439
        rnd_mode = float_round_up;
1440
        break;
1441
    case FSR_RD_NEG:
1442
        rnd_mode = float_round_down;
1443
        break;
1444
    }
1445
    set_float_rounding_mode(rnd_mode, &env->fp_status);
1446
}
1447

    
1448
void helper_debug()
1449
{
1450
    env->exception_index = EXCP_DEBUG;
1451
    cpu_loop_exit();
1452
}
1453

    
1454
#ifndef TARGET_SPARC64
1455
void do_wrpsr()
1456
{
1457
    if ((T0 & PSR_CWP) >= NWINDOWS)
1458
        raise_exception(TT_ILL_INSN);
1459
    else
1460
        PUT_PSR(env, T0);
1461
}
1462

    
1463
void do_rdpsr()
1464
{
1465
    T0 = GET_PSR(env);
1466
}
1467

    
1468
#else
1469

    
1470
void do_popc()
1471
{
1472
    T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL);
1473
    T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL);
1474
    T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL);
1475
    T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL);
1476
    T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL);
1477
    T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL);
1478
}
1479

    
1480
static inline uint64_t *get_gregset(uint64_t pstate)
1481
{
1482
    switch (pstate) {
1483
    default:
1484
    case 0:
1485
        return env->bgregs;
1486
    case PS_AG:
1487
        return env->agregs;
1488
    case PS_MG:
1489
        return env->mgregs;
1490
    case PS_IG:
1491
        return env->igregs;
1492
    }
1493
}
1494

    
1495
static inline void change_pstate(uint64_t new_pstate)
1496
{
1497
    uint64_t pstate_regs, new_pstate_regs;
1498
    uint64_t *src, *dst;
1499

    
1500
    pstate_regs = env->pstate & 0xc01;
1501
    new_pstate_regs = new_pstate & 0xc01;
1502
    if (new_pstate_regs != pstate_regs) {
1503
        // Switch global register bank
1504
        src = get_gregset(new_pstate_regs);
1505
        dst = get_gregset(pstate_regs);
1506
        memcpy32(dst, env->gregs);
1507
        memcpy32(env->gregs, src);
1508
    }
1509
    env->pstate = new_pstate;
1510
}
1511

    
1512
void do_wrpstate(void)
1513
{
1514
    change_pstate(T0 & 0xf3f);
1515
}
1516

    
1517
void do_done(void)
1518
{
1519
    env->tl--;
1520
    env->pc = env->tnpc[env->tl];
1521
    env->npc = env->tnpc[env->tl] + 4;
1522
    PUT_CCR(env, env->tstate[env->tl] >> 32);
1523
    env->asi = (env->tstate[env->tl] >> 24) & 0xff;
1524
    change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
1525
    PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1526
}
1527

    
1528
void do_retry(void)
1529
{
1530
    env->tl--;
1531
    env->pc = env->tpc[env->tl];
1532
    env->npc = env->tnpc[env->tl];
1533
    PUT_CCR(env, env->tstate[env->tl] >> 32);
1534
    env->asi = (env->tstate[env->tl] >> 24) & 0xff;
1535
    change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
1536
    PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1537
}
1538
#endif
1539

    
1540
void set_cwp(int new_cwp)
1541
{
1542
    /* put the modified wrap registers at their proper location */
1543
    if (env->cwp == (NWINDOWS - 1))
1544
        memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
1545
    env->cwp = new_cwp;
1546
    /* put the wrap registers at their temporary location */
1547
    if (new_cwp == (NWINDOWS - 1))
1548
        memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
1549
    env->regwptr = env->regbase + (new_cwp * 16);
1550
    REGWPTR = env->regwptr;
1551
}
1552

    
1553
void cpu_set_cwp(CPUState *env1, int new_cwp)
1554
{
1555
    CPUState *saved_env;
1556
#ifdef reg_REGWPTR
1557
    target_ulong *saved_regwptr;
1558
#endif
1559

    
1560
    saved_env = env;
1561
#ifdef reg_REGWPTR
1562
    saved_regwptr = REGWPTR;
1563
#endif
1564
    env = env1;
1565
    set_cwp(new_cwp);
1566
    env = saved_env;
1567
#ifdef reg_REGWPTR
1568
    REGWPTR = saved_regwptr;
1569
#endif
1570
}
1571

    
1572
#ifdef TARGET_SPARC64
1573
void do_interrupt(int intno)
1574
{
1575
#ifdef DEBUG_PCALL
1576
    if (loglevel & CPU_LOG_INT) {
1577
        static int count;
1578
        fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
1579
                count, intno,
1580
                env->pc,
1581
                env->npc, env->regwptr[6]);
1582
        cpu_dump_state(env, logfile, fprintf, 0);
1583
#if 0
1584
        {
1585
            int i;
1586
            uint8_t *ptr;
1587

1588
            fprintf(logfile, "       code=");
1589
            ptr = (uint8_t *)env->pc;
1590
            for(i = 0; i < 16; i++) {
1591
                fprintf(logfile, " %02x", ldub(ptr + i));
1592
            }
1593
            fprintf(logfile, "\n");
1594
        }
1595
#endif
1596
        count++;
1597
    }
1598
#endif
1599
#if !defined(CONFIG_USER_ONLY)
1600
    if (env->tl == MAXTL) {
1601
        cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
1602
        return;
1603
    }
1604
#endif
1605
    env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
1606
        ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
1607
    env->tpc[env->tl] = env->pc;
1608
    env->tnpc[env->tl] = env->npc;
1609
    env->tt[env->tl] = intno;
1610
    change_pstate(PS_PEF | PS_PRIV | PS_AG);
1611

    
1612
    if (intno == TT_CLRWIN)
1613
        set_cwp((env->cwp - 1) & (NWINDOWS - 1));
1614
    else if ((intno & 0x1c0) == TT_SPILL)
1615
        set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
1616
    else if ((intno & 0x1c0) == TT_FILL)
1617
        set_cwp((env->cwp + 1) & (NWINDOWS - 1));
1618
    env->tbr &= ~0x7fffULL;
1619
    env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
1620
    if (env->tl < MAXTL - 1) {
1621
        env->tl++;
1622
    } else {
1623
        env->pstate |= PS_RED;
1624
        if (env->tl != MAXTL)
1625
            env->tl++;
1626
    }
1627
    env->pc = env->tbr;
1628
    env->npc = env->pc + 4;
1629
    env->exception_index = 0;
1630
}
1631
#else
1632
void do_interrupt(int intno)
1633
{
1634
    int cwp;
1635

    
1636
#ifdef DEBUG_PCALL
1637
    if (loglevel & CPU_LOG_INT) {
1638
        static int count;
1639
        fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
1640
                count, intno,
1641
                env->pc,
1642
                env->npc, env->regwptr[6]);
1643
        cpu_dump_state(env, logfile, fprintf, 0);
1644
#if 0
1645
        {
1646
            int i;
1647
            uint8_t *ptr;
1648

1649
            fprintf(logfile, "       code=");
1650
            ptr = (uint8_t *)env->pc;
1651
            for(i = 0; i < 16; i++) {
1652
                fprintf(logfile, " %02x", ldub(ptr + i));
1653
            }
1654
            fprintf(logfile, "\n");
1655
        }
1656
#endif
1657
        count++;
1658
    }
1659
#endif
1660
#if !defined(CONFIG_USER_ONLY)
1661
    if (env->psret == 0) {
1662
        cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
1663
        return;
1664
    }
1665
#endif
1666
    env->psret = 0;
1667
    cwp = (env->cwp - 1) & (NWINDOWS - 1);
1668
    set_cwp(cwp);
1669
    env->regwptr[9] = env->pc;
1670
    env->regwptr[10] = env->npc;
1671
    env->psrps = env->psrs;
1672
    env->psrs = 1;
1673
    env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
1674
    env->pc = env->tbr;
1675
    env->npc = env->pc + 4;
1676
    env->exception_index = 0;
1677
}
1678
#endif
1679

    
1680
#if !defined(CONFIG_USER_ONLY)
1681

    
1682
static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1683
                                void *retaddr);
1684

    
1685
#define MMUSUFFIX _mmu
1686
#define ALIGNED_ONLY
1687
#define GETPC() (__builtin_return_address(0))
1688

    
1689
#define SHIFT 0
1690
#include "softmmu_template.h"
1691

    
1692
#define SHIFT 1
1693
#include "softmmu_template.h"
1694

    
1695
#define SHIFT 2
1696
#include "softmmu_template.h"
1697

    
1698
#define SHIFT 3
1699
#include "softmmu_template.h"
1700

    
1701
static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1702
                                void *retaddr)
1703
{
1704
#ifdef DEBUG_UNALIGNED
1705
    printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
1706
#endif
1707
    raise_exception(TT_UNALIGNED);
1708
}
1709

    
1710
/* try to fill the TLB and return an exception if error. If retaddr is
1711
   NULL, it means that the function was called in C code (i.e. not
1712
   from generated code or from helper.c) */
1713
/* XXX: fix it to restore all registers */
1714
void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1715
{
1716
    TranslationBlock *tb;
1717
    int ret;
1718
    unsigned long pc;
1719
    CPUState *saved_env;
1720

    
1721
    /* XXX: hack to restore env in all cases, even if not called from
1722
       generated code */
1723
    saved_env = env;
1724
    env = cpu_single_env;
1725

    
1726
    ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1727
    if (ret) {
1728
        if (retaddr) {
1729
            /* now we have a real cpu fault */
1730
            pc = (unsigned long)retaddr;
1731
            tb = tb_find_pc(pc);
1732
            if (tb) {
1733
                /* the PC is inside the translated code. It means that we have
1734
                   a virtual CPU fault */
1735
                cpu_restore_state(tb, env, pc, (void *)T2);
1736
            }
1737
        }
1738
        cpu_loop_exit();
1739
    }
1740
    env = saved_env;
1741
}
1742

    
1743
#endif
1744

    
1745
#ifndef TARGET_SPARC64
1746
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1747
                          int is_asi)
1748
{
1749
    CPUState *saved_env;
1750

    
1751
    /* XXX: hack to restore env in all cases, even if not called from
1752
       generated code */
1753
    saved_env = env;
1754
    env = cpu_single_env;
1755
    if (env->mmuregs[3]) /* Fault status register */
1756
        env->mmuregs[3] = 1; /* overflow (not read before another fault) */
1757
    if (is_asi)
1758
        env->mmuregs[3] |= 1 << 16;
1759
    if (env->psrs)
1760
        env->mmuregs[3] |= 1 << 5;
1761
    if (is_exec)
1762
        env->mmuregs[3] |= 1 << 6;
1763
    if (is_write)
1764
        env->mmuregs[3] |= 1 << 7;
1765
    env->mmuregs[3] |= (5 << 2) | 2;
1766
    env->mmuregs[4] = addr; /* Fault address register */
1767
    if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1768
#ifdef DEBUG_UNASSIGNED
1769
        printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
1770
               "\n", addr, env->pc);
1771
#endif
1772
        if (is_exec)
1773
            raise_exception(TT_CODE_ACCESS);
1774
        else
1775
            raise_exception(TT_DATA_ACCESS);
1776
    }
1777
    env = saved_env;
1778
}
1779
#else
1780
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1781
                          int is_asi)
1782
{
1783
#ifdef DEBUG_UNASSIGNED
1784
    CPUState *saved_env;
1785

    
1786
    /* XXX: hack to restore env in all cases, even if not called from
1787
       generated code */
1788
    saved_env = env;
1789
    env = cpu_single_env;
1790
    printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
1791
           addr, env->pc);
1792
    env = saved_env;
1793
#endif
1794
    if (is_exec)
1795
        raise_exception(TT_CODE_ACCESS);
1796
    else
1797
        raise_exception(TT_DATA_ACCESS);
1798
}
1799
#endif
1800

    
1801
#ifdef TARGET_SPARC64
1802
void do_tick_set_count(void *opaque, uint64_t count)
1803
{
1804
#if !defined(CONFIG_USER_ONLY)
1805
    ptimer_set_count(opaque, -count);
1806
#endif
1807
}
1808

    
1809
uint64_t do_tick_get_count(void *opaque)
1810
{
1811
#if !defined(CONFIG_USER_ONLY)
1812
    return -ptimer_get_count(opaque);
1813
#else
1814
    return 0;
1815
#endif
1816
}
1817

    
1818
void do_tick_set_limit(void *opaque, uint64_t limit)
1819
{
1820
#if !defined(CONFIG_USER_ONLY)
1821
    ptimer_set_limit(opaque, -limit, 0);
1822
#endif
1823
}
1824
#endif