Revision 20c9f095 hw/sun4u.c
| b/hw/sun4u.c | ||
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| 282 | 282 |
static void main_cpu_reset(void *opaque) |
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{
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CPUState *env = opaque; |
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cpu_reset(env); |
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ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); |
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ptimer_run(env->tick, 0); |
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ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); |
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ptimer_run(env->stick, 0); |
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ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); |
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ptimer_run(env->hstick, 0); |
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} |
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void tick_irq(void *opaque) |
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{
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CPUState *env = opaque; |
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cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
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} |
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void stick_irq(void *opaque) |
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{
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CPUState *env = opaque; |
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cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
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} |
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void hstick_irq(void *opaque) |
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{
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CPUState *env = opaque; |
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cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
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} |
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
|
| ... | ... | |
| 311 | 339 |
long prom_offset, initrd_size, kernel_size; |
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PCIBus *pci_bus; |
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const sparc_def_t *def; |
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QEMUBH *bh; |
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linux_boot = (kernel_filename != NULL); |
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|
| ... | ... | |
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} |
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env = cpu_init(); |
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cpu_sparc_register(env, def); |
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bh = qemu_bh_new(tick_irq, env); |
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env->tick = ptimer_init(bh); |
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ptimer_set_period(env->tick, 1ULL); |
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bh = qemu_bh_new(stick_irq, env); |
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env->stick = ptimer_init(bh); |
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ptimer_set_period(env->stick, 1ULL); |
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bh = qemu_bh_new(hstick_irq, env); |
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env->hstick = ptimer_init(bh); |
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ptimer_set_period(env->hstick, 1ULL); |
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env); |
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main_cpu_reset(env); |
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| 329 | 370 |
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/* allocate RAM */ |
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cpu_register_physical_memory(0, ram_size, 0); |
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