Revision 20dcee94 target-m68k/translate.c
| b/target-m68k/translate.c | ||
|---|---|---|
| 1345 | 1345 |
gen_op_logic_cc(gen_im32(val & 0xf)); |
| 1346 | 1346 |
gen_op_update_xflag_tst(gen_im32((val & 0x10) >> 4)); |
| 1347 | 1347 |
if (!ccr_only) {
|
| 1348 |
gen_op_mov32(QREG_SR, gen_im32(val & 0xff00));
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|
| 1348 |
gen_op_set_sr(gen_im32(val & 0xff00));
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|
| 1349 | 1349 |
} |
| 1350 | 1350 |
} |
| 1351 | 1351 |
|
| ... | ... | |
| 1365 | 1365 |
gen_op_and32(src1, src1, gen_im32(1)); |
| 1366 | 1366 |
gen_op_update_xflag_tst(src1); |
| 1367 | 1367 |
if (!ccr_only) {
|
| 1368 |
gen_op_and32(QREG_SR, reg, gen_im32(0xff00));
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|
| 1368 |
gen_op_set_sr(reg);
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|
| 1369 | 1369 |
} |
| 1370 | 1370 |
} |
| 1371 | 1371 |
else if ((insn & 0x3f) == 0x3c) |
| ... | ... | |
| 2797 | 2797 |
INSN(trap, 4e40, fff0, CF_ISA_A); |
| 2798 | 2798 |
INSN(link, 4e50, fff8, CF_ISA_A); |
| 2799 | 2799 |
INSN(unlk, 4e58, fff8, CF_ISA_A); |
| 2800 |
INSN(move_to_usp, 4e60, fff8, CF_ISA_B);
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|
| 2801 |
INSN(move_from_usp, 4e68, fff8, CF_ISA_B);
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|
| 2800 |
INSN(move_to_usp, 4e60, fff8, USP);
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|
| 2801 |
INSN(move_from_usp, 4e68, fff8, USP);
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|
| 2802 | 2802 |
INSN(nop, 4e71, ffff, CF_ISA_A); |
| 2803 | 2803 |
INSN(stop, 4e72, ffff, CF_ISA_A); |
| 2804 | 2804 |
INSN(rte, 4e73, ffff, CF_ISA_A); |
| ... | ... | |
| 3261 | 3261 |
#if !defined (CONFIG_USER_ONLY) |
| 3262 | 3262 |
env->sr = 0x2700; |
| 3263 | 3263 |
#endif |
| 3264 |
m68k_switch_sp(env); |
|
| 3264 | 3265 |
/* ??? FP regs should be initialized to NaN. */ |
| 3265 | 3266 |
env->cc_op = CC_OP_FLAGS; |
| 3266 | 3267 |
/* TODO: We should set PC from the interrupt vector. */ |
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