root / hw / ppc / spapr_hcall.c @ 210b580b
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#include "sysemu/sysemu.h" |
---|---|
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#include "cpu.h" |
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#include "helper_regs.h" |
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#include "hw/ppc/spapr.h" |
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#include "mmu-hash64.h" |
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|
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static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
|
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target_ulong pte_index) |
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{ |
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target_ulong rb, va_low; |
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|
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rb = (v & ~0x7fULL) << 16; /* AVA field */ |
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va_low = pte_index >> 3;
|
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if (v & HPTE64_V_SECONDARY) {
|
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va_low = ~va_low; |
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} |
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/* xor vsid from AVA */
|
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if (!(v & HPTE64_V_1TB_SEG)) {
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va_low ^= v >> 12;
|
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} else {
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va_low ^= v >> 24;
|
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} |
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va_low &= 0x7ff;
|
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if (v & HPTE64_V_LARGE) {
|
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rb |= 1; /* L field */ |
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#if 0 /* Disable that P7 specific bit for now */
|
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if (r & 0xff000) {
|
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/* non-16MB large page, must be 64k */
|
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/* (masks depend on page size) */
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rb |= 0x1000; /* page encoding in LP field */
|
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rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
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rb |= (va_low & 0xfe); /* AVAL field */
|
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}
|
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#endif
|
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} else {
|
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/* 4kB page */
|
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rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ |
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} |
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rb |= (v >> 54) & 0x300; /* B field */ |
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return rb;
|
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} |
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|
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static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
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target_ulong opcode, target_ulong *args) |
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{ |
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CPUPPCState *env = &cpu->env; |
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target_ulong flags = args[0];
|
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target_ulong pte_index = args[1];
|
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target_ulong pteh = args[2];
|
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target_ulong ptel = args[3];
|
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target_ulong page_shift = 12;
|
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target_ulong raddr; |
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target_ulong i; |
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hwaddr hpte; |
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|
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/* only handle 4k and 16M pages for now */
|
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if (pteh & HPTE64_V_LARGE) {
|
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#if 0 /* We don't support 64k pages yet */
|
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if ((ptel & 0xf000) == 0x1000) {
|
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/* 64k page */
|
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} else
|
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#endif
|
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if ((ptel & 0xff000) == 0) { |
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/* 16M page */
|
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page_shift = 24;
|
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/* lowest AVA bit must be 0 for 16M pages */
|
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if (pteh & 0x80) { |
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return H_PARAMETER;
|
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} |
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} else {
|
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return H_PARAMETER;
|
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} |
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} |
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|
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raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1); |
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|
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if (raddr < spapr->ram_limit) {
|
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/* Regular RAM - should have WIMG=0010 */
|
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if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
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return H_PARAMETER;
|
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} |
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} else {
|
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/* Looks like an IO address */
|
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/* FIXME: What WIMG combinations could be sensible for IO?
|
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* For now we allow WIMG=010x, but are there others? */
|
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/* FIXME: Should we check against registered IO addresses? */
|
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if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) {
|
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return H_PARAMETER;
|
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} |
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} |
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|
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pteh &= ~0x60ULL;
|
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|
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
|
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return H_PARAMETER;
|
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} |
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if (likely((flags & H_EXACT) == 0)) { |
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pte_index &= ~7ULL;
|
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hpte = pte_index * HASH_PTE_SIZE_64; |
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for (i = 0; ; ++i) { |
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if (i == 8) { |
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return H_PTEG_FULL;
|
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} |
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if ((ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) == 0) { |
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break;
|
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} |
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hpte += HASH_PTE_SIZE_64; |
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} |
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} else {
|
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i = 0;
|
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hpte = pte_index * HASH_PTE_SIZE_64; |
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if (ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) {
|
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return H_PTEG_FULL;
|
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} |
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} |
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ppc_hash64_store_hpte1(env, hpte, ptel); |
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/* eieio(); FIXME: need some sort of barrier for smp? */
|
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ppc_hash64_store_hpte0(env, hpte, pteh); |
119 |
|
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args[0] = pte_index + i;
|
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return H_SUCCESS;
|
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} |
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|
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enum {
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REMOVE_SUCCESS = 0,
|
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REMOVE_NOT_FOUND = 1,
|
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REMOVE_PARM = 2,
|
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REMOVE_HW = 3,
|
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}; |
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|
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static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex,
|
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target_ulong avpn, |
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target_ulong flags, |
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target_ulong *vp, target_ulong *rp) |
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{ |
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hwaddr hpte; |
137 |
target_ulong v, r, rb; |
138 |
|
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if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
|
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return REMOVE_PARM;
|
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} |
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|
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hpte = ptex * HASH_PTE_SIZE_64; |
144 |
|
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v = ppc_hash64_load_hpte0(env, hpte); |
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r = ppc_hash64_load_hpte1(env, hpte); |
147 |
|
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if ((v & HPTE64_V_VALID) == 0 || |
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((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
|
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((flags & H_ANDCOND) && (v & avpn) != 0)) {
|
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return REMOVE_NOT_FOUND;
|
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} |
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*vp = v; |
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*rp = r; |
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ppc_hash64_store_hpte0(env, hpte, 0);
|
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rb = compute_tlbie_rb(v, r, ptex); |
157 |
ppc_tlb_invalidate_one(env, rb); |
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return REMOVE_SUCCESS;
|
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} |
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|
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static target_ulong h_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
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target_ulong opcode, target_ulong *args) |
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{ |
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CPUPPCState *env = &cpu->env; |
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target_ulong flags = args[0];
|
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target_ulong pte_index = args[1];
|
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target_ulong avpn = args[2];
|
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int ret;
|
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|
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ret = remove_hpte(env, pte_index, avpn, flags, |
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&args[0], &args[1]); |
172 |
|
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switch (ret) {
|
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case REMOVE_SUCCESS:
|
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return H_SUCCESS;
|
176 |
|
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case REMOVE_NOT_FOUND:
|
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return H_NOT_FOUND;
|
179 |
|
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case REMOVE_PARM:
|
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return H_PARAMETER;
|
182 |
|
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case REMOVE_HW:
|
184 |
return H_HARDWARE;
|
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} |
186 |
|
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assert(0);
|
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} |
189 |
|
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#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL |
191 |
#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL |
192 |
#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL |
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#define H_BULK_REMOVE_END 0xc000000000000000ULL |
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#define H_BULK_REMOVE_CODE 0x3000000000000000ULL |
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#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL |
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#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL |
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#define H_BULK_REMOVE_PARM 0x2000000000000000ULL |
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#define H_BULK_REMOVE_HW 0x3000000000000000ULL |
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#define H_BULK_REMOVE_RC 0x0c00000000000000ULL |
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#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL |
201 |
#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL |
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#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL |
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#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL |
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#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL |
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|
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#define H_BULK_REMOVE_MAX_BATCH 4 |
207 |
|
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static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
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target_ulong opcode, target_ulong *args) |
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{ |
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CPUPPCState *env = &cpu->env; |
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int i;
|
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|
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for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { |
215 |
target_ulong *tsh = &args[i*2];
|
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target_ulong tsl = args[i*2 + 1]; |
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target_ulong v, r, ret; |
218 |
|
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if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
|
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break;
|
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} else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { |
222 |
return H_PARAMETER;
|
223 |
} |
224 |
|
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*tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; |
226 |
*tsh |= H_BULK_REMOVE_RESPONSE; |
227 |
|
228 |
if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
|
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*tsh |= H_BULK_REMOVE_PARM; |
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return H_PARAMETER;
|
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} |
232 |
|
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ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl, |
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(*tsh & H_BULK_REMOVE_FLAGS) >> 26,
|
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&v, &r); |
236 |
|
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*tsh |= ret << 60;
|
238 |
|
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switch (ret) {
|
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case REMOVE_SUCCESS:
|
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*tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
|
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break;
|
243 |
|
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case REMOVE_PARM:
|
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return H_PARAMETER;
|
246 |
|
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case REMOVE_HW:
|
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return H_HARDWARE;
|
249 |
} |
250 |
} |
251 |
|
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return H_SUCCESS;
|
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} |
254 |
|
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static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
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target_ulong opcode, target_ulong *args) |
257 |
{ |
258 |
CPUPPCState *env = &cpu->env; |
259 |
target_ulong flags = args[0];
|
260 |
target_ulong pte_index = args[1];
|
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target_ulong avpn = args[2];
|
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hwaddr hpte; |
263 |
target_ulong v, r, rb; |
264 |
|
265 |
if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
|
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return H_PARAMETER;
|
267 |
} |
268 |
|
269 |
hpte = pte_index * HASH_PTE_SIZE_64; |
270 |
|
271 |
v = ppc_hash64_load_hpte0(env, hpte); |
272 |
r = ppc_hash64_load_hpte1(env, hpte); |
273 |
|
274 |
if ((v & HPTE64_V_VALID) == 0 || |
275 |
((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
|
276 |
return H_NOT_FOUND;
|
277 |
} |
278 |
|
279 |
r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | |
280 |
HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); |
281 |
r |= (flags << 55) & HPTE64_R_PP0;
|
282 |
r |= (flags << 48) & HPTE64_R_KEY_HI;
|
283 |
r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); |
284 |
rb = compute_tlbie_rb(v, r, pte_index); |
285 |
ppc_hash64_store_hpte0(env, hpte, v & ~HPTE64_V_VALID); |
286 |
ppc_tlb_invalidate_one(env, rb); |
287 |
ppc_hash64_store_hpte1(env, hpte, r); |
288 |
/* Don't need a memory barrier, due to qemu's global lock */
|
289 |
ppc_hash64_store_hpte0(env, hpte, v); |
290 |
return H_SUCCESS;
|
291 |
} |
292 |
|
293 |
static target_ulong h_read(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
294 |
target_ulong opcode, target_ulong *args) |
295 |
{ |
296 |
CPUPPCState *env = &cpu->env; |
297 |
target_ulong flags = args[0];
|
298 |
target_ulong pte_index = args[1];
|
299 |
uint8_t *hpte; |
300 |
int i, ridx, n_entries = 1; |
301 |
|
302 |
if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
|
303 |
return H_PARAMETER;
|
304 |
} |
305 |
|
306 |
if (flags & H_READ_4) {
|
307 |
/* Clear the two low order bits */
|
308 |
pte_index &= ~(3ULL);
|
309 |
n_entries = 4;
|
310 |
} |
311 |
|
312 |
hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); |
313 |
|
314 |
for (i = 0, ridx = 0; i < n_entries; i++) { |
315 |
args[ridx++] = ldq_p(hpte); |
316 |
args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
|
317 |
hpte += HASH_PTE_SIZE_64; |
318 |
} |
319 |
|
320 |
return H_SUCCESS;
|
321 |
} |
322 |
|
323 |
static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
324 |
target_ulong opcode, target_ulong *args) |
325 |
{ |
326 |
/* FIXME: actually implement this */
|
327 |
return H_HARDWARE;
|
328 |
} |
329 |
|
330 |
#define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
331 |
#define FLAGS_REGISTER_DTL 0x0000400000000000ULL |
332 |
#define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL |
333 |
#define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL |
334 |
#define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL |
335 |
#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL |
336 |
|
337 |
#define VPA_MIN_SIZE 640 |
338 |
#define VPA_SIZE_OFFSET 0x4 |
339 |
#define VPA_SHARED_PROC_OFFSET 0x9 |
340 |
#define VPA_SHARED_PROC_VAL 0x2 |
341 |
|
342 |
static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
|
343 |
{ |
344 |
uint16_t size; |
345 |
uint8_t tmp; |
346 |
|
347 |
if (vpa == 0) { |
348 |
hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
|
349 |
return H_HARDWARE;
|
350 |
} |
351 |
|
352 |
if (vpa % env->dcache_line_size) {
|
353 |
return H_PARAMETER;
|
354 |
} |
355 |
/* FIXME: bounds check the address */
|
356 |
|
357 |
size = lduw_be_phys(vpa + 0x4);
|
358 |
|
359 |
if (size < VPA_MIN_SIZE) {
|
360 |
return H_PARAMETER;
|
361 |
} |
362 |
|
363 |
/* VPA is not allowed to cross a page boundary */
|
364 |
if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { |
365 |
return H_PARAMETER;
|
366 |
} |
367 |
|
368 |
env->vpa_addr = vpa; |
369 |
|
370 |
tmp = ldub_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET); |
371 |
tmp |= VPA_SHARED_PROC_VAL; |
372 |
stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
373 |
|
374 |
return H_SUCCESS;
|
375 |
} |
376 |
|
377 |
static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
|
378 |
{ |
379 |
if (env->slb_shadow_addr) {
|
380 |
return H_RESOURCE;
|
381 |
} |
382 |
|
383 |
if (env->dtl_addr) {
|
384 |
return H_RESOURCE;
|
385 |
} |
386 |
|
387 |
env->vpa_addr = 0;
|
388 |
return H_SUCCESS;
|
389 |
} |
390 |
|
391 |
static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
|
392 |
{ |
393 |
uint32_t size; |
394 |
|
395 |
if (addr == 0) { |
396 |
hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
|
397 |
return H_HARDWARE;
|
398 |
} |
399 |
|
400 |
size = ldl_be_phys(addr + 0x4);
|
401 |
if (size < 0x8) { |
402 |
return H_PARAMETER;
|
403 |
} |
404 |
|
405 |
if ((addr / 4096) != ((addr + size - 1) / 4096)) { |
406 |
return H_PARAMETER;
|
407 |
} |
408 |
|
409 |
if (!env->vpa_addr) {
|
410 |
return H_RESOURCE;
|
411 |
} |
412 |
|
413 |
env->slb_shadow_addr = addr; |
414 |
env->slb_shadow_size = size; |
415 |
|
416 |
return H_SUCCESS;
|
417 |
} |
418 |
|
419 |
static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
|
420 |
{ |
421 |
env->slb_shadow_addr = 0;
|
422 |
env->slb_shadow_size = 0;
|
423 |
return H_SUCCESS;
|
424 |
} |
425 |
|
426 |
static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
|
427 |
{ |
428 |
uint32_t size; |
429 |
|
430 |
if (addr == 0) { |
431 |
hcall_dprintf("Can't cope with DTL at logical 0\n");
|
432 |
return H_HARDWARE;
|
433 |
} |
434 |
|
435 |
size = ldl_be_phys(addr + 0x4);
|
436 |
|
437 |
if (size < 48) { |
438 |
return H_PARAMETER;
|
439 |
} |
440 |
|
441 |
if (!env->vpa_addr) {
|
442 |
return H_RESOURCE;
|
443 |
} |
444 |
|
445 |
env->dtl_addr = addr; |
446 |
env->dtl_size = size; |
447 |
|
448 |
return H_SUCCESS;
|
449 |
} |
450 |
|
451 |
static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
|
452 |
{ |
453 |
env->dtl_addr = 0;
|
454 |
env->dtl_size = 0;
|
455 |
|
456 |
return H_SUCCESS;
|
457 |
} |
458 |
|
459 |
static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
460 |
target_ulong opcode, target_ulong *args) |
461 |
{ |
462 |
target_ulong flags = args[0];
|
463 |
target_ulong procno = args[1];
|
464 |
target_ulong vpa = args[2];
|
465 |
target_ulong ret = H_PARAMETER; |
466 |
CPUPPCState *tenv; |
467 |
CPUState *tcpu; |
468 |
|
469 |
tcpu = qemu_get_cpu(procno); |
470 |
if (!tcpu) {
|
471 |
return H_PARAMETER;
|
472 |
} |
473 |
tenv = tcpu->env_ptr; |
474 |
|
475 |
switch (flags) {
|
476 |
case FLAGS_REGISTER_VPA:
|
477 |
ret = register_vpa(tenv, vpa); |
478 |
break;
|
479 |
|
480 |
case FLAGS_DEREGISTER_VPA:
|
481 |
ret = deregister_vpa(tenv, vpa); |
482 |
break;
|
483 |
|
484 |
case FLAGS_REGISTER_SLBSHADOW:
|
485 |
ret = register_slb_shadow(tenv, vpa); |
486 |
break;
|
487 |
|
488 |
case FLAGS_DEREGISTER_SLBSHADOW:
|
489 |
ret = deregister_slb_shadow(tenv, vpa); |
490 |
break;
|
491 |
|
492 |
case FLAGS_REGISTER_DTL:
|
493 |
ret = register_dtl(tenv, vpa); |
494 |
break;
|
495 |
|
496 |
case FLAGS_DEREGISTER_DTL:
|
497 |
ret = deregister_dtl(tenv, vpa); |
498 |
break;
|
499 |
} |
500 |
|
501 |
return ret;
|
502 |
} |
503 |
|
504 |
static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
505 |
target_ulong opcode, target_ulong *args) |
506 |
{ |
507 |
CPUPPCState *env = &cpu->env; |
508 |
CPUState *cs = CPU(cpu); |
509 |
|
510 |
env->msr |= (1ULL << MSR_EE);
|
511 |
hreg_compute_hflags(env); |
512 |
if (!cpu_has_work(cs)) {
|
513 |
cs->halted = 1;
|
514 |
env->exception_index = EXCP_HLT; |
515 |
cs->exit_request = 1;
|
516 |
} |
517 |
return H_SUCCESS;
|
518 |
} |
519 |
|
520 |
static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
521 |
target_ulong opcode, target_ulong *args) |
522 |
{ |
523 |
target_ulong rtas_r3 = args[0];
|
524 |
uint32_t token = ldl_be_phys(rtas_r3); |
525 |
uint32_t nargs = ldl_be_phys(rtas_r3 + 4);
|
526 |
uint32_t nret = ldl_be_phys(rtas_r3 + 8);
|
527 |
|
528 |
return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, |
529 |
nret, rtas_r3 + 12 + 4*nargs); |
530 |
} |
531 |
|
532 |
static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
533 |
target_ulong opcode, target_ulong *args) |
534 |
{ |
535 |
target_ulong size = args[0];
|
536 |
target_ulong addr = args[1];
|
537 |
|
538 |
switch (size) {
|
539 |
case 1: |
540 |
args[0] = ldub_phys(addr);
|
541 |
return H_SUCCESS;
|
542 |
case 2: |
543 |
args[0] = lduw_phys(addr);
|
544 |
return H_SUCCESS;
|
545 |
case 4: |
546 |
args[0] = ldl_phys(addr);
|
547 |
return H_SUCCESS;
|
548 |
case 8: |
549 |
args[0] = ldq_phys(addr);
|
550 |
return H_SUCCESS;
|
551 |
} |
552 |
return H_PARAMETER;
|
553 |
} |
554 |
|
555 |
static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
556 |
target_ulong opcode, target_ulong *args) |
557 |
{ |
558 |
target_ulong size = args[0];
|
559 |
target_ulong addr = args[1];
|
560 |
target_ulong val = args[2];
|
561 |
|
562 |
switch (size) {
|
563 |
case 1: |
564 |
stb_phys(addr, val); |
565 |
return H_SUCCESS;
|
566 |
case 2: |
567 |
stw_phys(addr, val); |
568 |
return H_SUCCESS;
|
569 |
case 4: |
570 |
stl_phys(addr, val); |
571 |
return H_SUCCESS;
|
572 |
case 8: |
573 |
stq_phys(addr, val); |
574 |
return H_SUCCESS;
|
575 |
} |
576 |
return H_PARAMETER;
|
577 |
} |
578 |
|
579 |
static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
580 |
target_ulong opcode, target_ulong *args) |
581 |
{ |
582 |
target_ulong dst = args[0]; /* Destination address */ |
583 |
target_ulong src = args[1]; /* Source address */ |
584 |
target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ |
585 |
target_ulong count = args[3]; /* Element count */ |
586 |
target_ulong op = args[4]; /* 0 = copy, 1 = invert */ |
587 |
uint64_t tmp; |
588 |
unsigned int mask = (1 << esize) - 1; |
589 |
int step = 1 << esize; |
590 |
|
591 |
if (count > 0x80000000) { |
592 |
return H_PARAMETER;
|
593 |
} |
594 |
|
595 |
if ((dst & mask) || (src & mask) || (op > 1)) { |
596 |
return H_PARAMETER;
|
597 |
} |
598 |
|
599 |
if (dst >= src && dst < (src + (count << esize))) {
|
600 |
dst = dst + ((count - 1) << esize);
|
601 |
src = src + ((count - 1) << esize);
|
602 |
step = -step; |
603 |
} |
604 |
|
605 |
while (count--) {
|
606 |
switch (esize) {
|
607 |
case 0: |
608 |
tmp = ldub_phys(src); |
609 |
break;
|
610 |
case 1: |
611 |
tmp = lduw_phys(src); |
612 |
break;
|
613 |
case 2: |
614 |
tmp = ldl_phys(src); |
615 |
break;
|
616 |
case 3: |
617 |
tmp = ldq_phys(src); |
618 |
break;
|
619 |
default:
|
620 |
return H_PARAMETER;
|
621 |
} |
622 |
if (op == 1) { |
623 |
tmp = ~tmp; |
624 |
} |
625 |
switch (esize) {
|
626 |
case 0: |
627 |
stb_phys(dst, tmp); |
628 |
break;
|
629 |
case 1: |
630 |
stw_phys(dst, tmp); |
631 |
break;
|
632 |
case 2: |
633 |
stl_phys(dst, tmp); |
634 |
break;
|
635 |
case 3: |
636 |
stq_phys(dst, tmp); |
637 |
break;
|
638 |
} |
639 |
dst = dst + step; |
640 |
src = src + step; |
641 |
} |
642 |
|
643 |
return H_SUCCESS;
|
644 |
} |
645 |
|
646 |
static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
647 |
target_ulong opcode, target_ulong *args) |
648 |
{ |
649 |
/* Nothing to do on emulation, KVM will trap this in the kernel */
|
650 |
return H_SUCCESS;
|
651 |
} |
652 |
|
653 |
static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
654 |
target_ulong opcode, target_ulong *args) |
655 |
{ |
656 |
/* Nothing to do on emulation, KVM will trap this in the kernel */
|
657 |
return H_SUCCESS;
|
658 |
} |
659 |
|
660 |
static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
661 |
static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; |
662 |
|
663 |
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
|
664 |
{ |
665 |
spapr_hcall_fn *slot; |
666 |
|
667 |
if (opcode <= MAX_HCALL_OPCODE) {
|
668 |
assert((opcode & 0x3) == 0); |
669 |
|
670 |
slot = &papr_hypercall_table[opcode / 4];
|
671 |
} else {
|
672 |
assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); |
673 |
|
674 |
slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
675 |
} |
676 |
|
677 |
assert(!(*slot)); |
678 |
*slot = fn; |
679 |
} |
680 |
|
681 |
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
682 |
target_ulong *args) |
683 |
{ |
684 |
if ((opcode <= MAX_HCALL_OPCODE)
|
685 |
&& ((opcode & 0x3) == 0)) { |
686 |
spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
|
687 |
|
688 |
if (fn) {
|
689 |
return fn(cpu, spapr, opcode, args);
|
690 |
} |
691 |
} else if ((opcode >= KVMPPC_HCALL_BASE) && |
692 |
(opcode <= KVMPPC_HCALL_MAX)) { |
693 |
spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
694 |
|
695 |
if (fn) {
|
696 |
return fn(cpu, spapr, opcode, args);
|
697 |
} |
698 |
} |
699 |
|
700 |
hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode); |
701 |
return H_FUNCTION;
|
702 |
} |
703 |
|
704 |
static void hypercall_register_types(void) |
705 |
{ |
706 |
/* hcall-pft */
|
707 |
spapr_register_hypercall(H_ENTER, h_enter); |
708 |
spapr_register_hypercall(H_REMOVE, h_remove); |
709 |
spapr_register_hypercall(H_PROTECT, h_protect); |
710 |
spapr_register_hypercall(H_READ, h_read); |
711 |
|
712 |
/* hcall-bulk */
|
713 |
spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); |
714 |
|
715 |
/* hcall-dabr */
|
716 |
spapr_register_hypercall(H_SET_DABR, h_set_dabr); |
717 |
|
718 |
/* hcall-splpar */
|
719 |
spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); |
720 |
spapr_register_hypercall(H_CEDE, h_cede); |
721 |
|
722 |
/* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
|
723 |
* here between the "CI" and the "CACHE" variants, they will use whatever
|
724 |
* mapping attributes qemu is using. When using KVM, the kernel will
|
725 |
* enforce the attributes more strongly
|
726 |
*/
|
727 |
spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); |
728 |
spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); |
729 |
spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); |
730 |
spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); |
731 |
spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); |
732 |
spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); |
733 |
spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
734 |
|
735 |
/* qemu/KVM-PPC specific hcalls */
|
736 |
spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); |
737 |
} |
738 |
|
739 |
type_init(hypercall_register_types) |