Revision 2115c019
| b/hw/pxa.h | ||
|---|---|---|
| 71 | 71 |
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); |
| 72 | 72 |
|
| 73 | 73 |
/* pxa2xx_dma.c */ |
| 74 |
typedef struct PXA2xxDMAState PXA2xxDMAState; |
|
| 75 |
PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, |
|
| 76 |
qemu_irq irq); |
|
| 77 |
PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, |
|
| 78 |
qemu_irq irq); |
|
| 79 |
void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on); |
|
| 74 |
DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq); |
|
| 75 |
DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq); |
|
| 80 | 76 |
|
| 81 | 77 |
/* pxa2xx_lcd.c */ |
| 82 | 78 |
typedef struct PXA2xxLCDState PXA2xxLCDState; |
| ... | ... | |
| 88 | 84 |
/* pxa2xx_mmci.c */ |
| 89 | 85 |
typedef struct PXA2xxMMCIState PXA2xxMMCIState; |
| 90 | 86 |
PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, |
| 91 |
BlockDriverState *bd, qemu_irq irq, void *dma); |
|
| 87 |
BlockDriverState *bd, qemu_irq irq, |
|
| 88 |
qemu_irq rx_dma, qemu_irq tx_dma); |
|
| 92 | 89 |
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, |
| 93 | 90 |
qemu_irq coverswitch); |
| 94 | 91 |
|
| ... | ... | |
| 123 | 120 |
CPUState *env; |
| 124 | 121 |
DeviceState *pic; |
| 125 | 122 |
qemu_irq reset; |
| 126 |
PXA2xxDMAState *dma;
|
|
| 123 |
DeviceState *dma;
|
|
| 127 | 124 |
DeviceState *gpio; |
| 128 | 125 |
PXA2xxLCDState *lcd; |
| 129 | 126 |
SSIBus **ssp; |
| ... | ... | |
| 181 | 178 |
|
| 182 | 179 |
struct PXA2xxI2SState {
|
| 183 | 180 |
qemu_irq irq; |
| 184 |
PXA2xxDMAState *dma; |
|
| 181 |
qemu_irq rx_dma; |
|
| 182 |
qemu_irq tx_dma; |
|
| 185 | 183 |
void (*data_req)(void *, int, int); |
| 186 | 184 |
|
| 187 | 185 |
uint32_t control[2]; |
| b/hw/pxa2xx.c | ||
|---|---|---|
| 1585 | 1585 |
tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && |
| 1586 | 1586 |
i2s->enable && !SACR_DPRL(i2s->control[1]); |
| 1587 | 1587 |
|
| 1588 |
pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
|
|
| 1589 |
pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
|
|
| 1588 |
qemu_set_irq(i2s->rx_dma, rfs);
|
|
| 1589 |
qemu_set_irq(i2s->tx_dma, tfs);
|
|
| 1590 | 1590 |
|
| 1591 | 1591 |
i2s->status &= 0xe0; |
| 1592 | 1592 |
if (i2s->fifo_len < 16 || !i2s->enable) |
| ... | ... | |
| 1769 | 1769 |
} |
| 1770 | 1770 |
|
| 1771 | 1771 |
static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, |
| 1772 |
qemu_irq irq, PXA2xxDMAState *dma)
|
|
| 1772 |
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
|
|
| 1773 | 1773 |
{
|
| 1774 | 1774 |
int iomemtype; |
| 1775 | 1775 |
PXA2xxI2SState *s = (PXA2xxI2SState *) |
| 1776 | 1776 |
qemu_mallocz(sizeof(PXA2xxI2SState)); |
| 1777 | 1777 |
|
| 1778 | 1778 |
s->irq = irq; |
| 1779 |
s->dma = dma; |
|
| 1779 |
s->rx_dma = rx_dma; |
|
| 1780 |
s->tx_dma = tx_dma; |
|
| 1780 | 1781 |
s->data_req = pxa2xx_i2s_data_req; |
| 1781 | 1782 |
|
| 1782 | 1783 |
pxa2xx_i2s_reset(s); |
| ... | ... | |
| 1794 | 1795 |
/* PXA Fast Infra-red Communications Port */ |
| 1795 | 1796 |
struct PXA2xxFIrState {
|
| 1796 | 1797 |
qemu_irq irq; |
| 1797 |
PXA2xxDMAState *dma; |
|
| 1798 |
qemu_irq rx_dma; |
|
| 1799 |
qemu_irq tx_dma; |
|
| 1798 | 1800 |
int enable; |
| 1799 | 1801 |
CharDriverState *chr; |
| 1800 | 1802 |
|
| ... | ... | |
| 1848 | 1850 |
(s->status[0] & (1 << 1)); /* TUR */ |
| 1849 | 1851 |
intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ |
| 1850 | 1852 |
|
| 1851 |
pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
|
|
| 1852 |
pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
|
|
| 1853 |
qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
|
|
| 1854 |
qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
|
|
| 1853 | 1855 |
|
| 1854 | 1856 |
qemu_set_irq(s->irq, intr && s->enable); |
| 1855 | 1857 |
} |
| ... | ... | |
| 2028 | 2030 |
} |
| 2029 | 2031 |
|
| 2030 | 2032 |
static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base, |
| 2031 |
qemu_irq irq, PXA2xxDMAState *dma,
|
|
| 2033 |
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
|
|
| 2032 | 2034 |
CharDriverState *chr) |
| 2033 | 2035 |
{
|
| 2034 | 2036 |
int iomemtype; |
| ... | ... | |
| 2036 | 2038 |
qemu_mallocz(sizeof(PXA2xxFIrState)); |
| 2037 | 2039 |
|
| 2038 | 2040 |
s->irq = irq; |
| 2039 |
s->dma = dma; |
|
| 2041 |
s->rx_dma = rx_dma; |
|
| 2042 |
s->tx_dma = tx_dma; |
|
| 2040 | 2043 |
s->chr = chr; |
| 2041 | 2044 |
|
| 2042 | 2045 |
pxa2xx_fir_reset(s); |
| ... | ... | |
| 2116 | 2119 |
exit(1); |
| 2117 | 2120 |
} |
| 2118 | 2121 |
s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv, |
| 2119 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma); |
|
| 2122 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
|
| 2123 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), |
|
| 2124 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); |
|
| 2120 | 2125 |
|
| 2121 | 2126 |
for (i = 0; pxa270_serial[i].io_base; i ++) |
| 2122 | 2127 |
if (serial_hds[i]) |
| ... | ... | |
| 2134 | 2139 |
if (serial_hds[i]) |
| 2135 | 2140 |
s->fir = pxa2xx_fir_init(0x40800000, |
| 2136 | 2141 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
| 2137 |
s->dma, serial_hds[i]); |
|
| 2142 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
|
| 2143 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), |
|
| 2144 |
serial_hds[i]); |
|
| 2138 | 2145 |
|
| 2139 | 2146 |
s->lcd = pxa2xx_lcdc_init(0x44000000, |
| 2140 | 2147 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
| ... | ... | |
| 2195 | 2202 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); |
| 2196 | 2203 |
|
| 2197 | 2204 |
s->i2s = pxa2xx_i2s_init(0x40400000, |
| 2198 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma); |
|
| 2205 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
|
| 2206 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), |
|
| 2207 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); |
|
| 2199 | 2208 |
|
| 2200 | 2209 |
s->kp = pxa27x_keypad_init(0x41500000, |
| 2201 | 2210 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); |
| ... | ... | |
| 2250 | 2259 |
exit(1); |
| 2251 | 2260 |
} |
| 2252 | 2261 |
s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv, |
| 2253 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma); |
|
| 2262 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
|
| 2263 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), |
|
| 2264 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); |
|
| 2254 | 2265 |
|
| 2255 | 2266 |
for (i = 0; pxa255_serial[i].io_base; i ++) |
| 2256 | 2267 |
if (serial_hds[i]) {
|
| ... | ... | |
| 2269 | 2280 |
if (serial_hds[i]) |
| 2270 | 2281 |
s->fir = pxa2xx_fir_init(0x40800000, |
| 2271 | 2282 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
| 2272 |
s->dma, serial_hds[i]); |
|
| 2283 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
|
| 2284 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), |
|
| 2285 |
serial_hds[i]); |
|
| 2273 | 2286 |
|
| 2274 | 2287 |
s->lcd = pxa2xx_lcdc_init(0x44000000, |
| 2275 | 2288 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
| ... | ... | |
| 2330 | 2343 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); |
| 2331 | 2344 |
|
| 2332 | 2345 |
s->i2s = pxa2xx_i2s_init(0x40400000, |
| 2333 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma); |
|
| 2346 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
|
| 2347 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), |
|
| 2348 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); |
|
| 2334 | 2349 |
|
| 2335 | 2350 |
/* GPIO1 resets the processor */ |
| 2336 | 2351 |
/* The handler can be overridden by board-specific code */ |
| b/hw/pxa2xx_dma.c | ||
|---|---|---|
| 10 | 10 |
|
| 11 | 11 |
#include "hw.h" |
| 12 | 12 |
#include "pxa.h" |
| 13 |
#include "sysbus.h" |
|
| 14 |
|
|
| 15 |
#define PXA255_DMA_NUM_CHANNELS 16 |
|
| 16 |
#define PXA27X_DMA_NUM_CHANNELS 32 |
|
| 17 |
|
|
| 18 |
#define PXA2XX_DMA_NUM_REQUESTS 75 |
|
| 13 | 19 |
|
| 14 | 20 |
typedef struct {
|
| 15 | 21 |
target_phys_addr_t descr; |
| ... | ... | |
| 20 | 26 |
int request; |
| 21 | 27 |
} PXA2xxDMAChannel; |
| 22 | 28 |
|
| 23 |
struct PXA2xxDMAState {
|
|
| 29 |
typedef struct PXA2xxDMAState {
|
|
| 30 |
SysBusDevice busdev; |
|
| 24 | 31 |
qemu_irq irq; |
| 25 | 32 |
|
| 26 | 33 |
uint32_t stopintr; |
| ... | ... | |
| 35 | 42 |
int channels; |
| 36 | 43 |
PXA2xxDMAChannel *chan; |
| 37 | 44 |
|
| 38 |
uint8_t *req;
|
|
| 45 |
uint8_t req[PXA2XX_DMA_NUM_REQUESTS];
|
|
| 39 | 46 |
|
| 40 | 47 |
/* Flag to avoid recursive DMA invocations. */ |
| 41 | 48 |
int running; |
| 42 |
}; |
|
| 43 |
|
|
| 44 |
#define PXA255_DMA_NUM_CHANNELS 16 |
|
| 45 |
#define PXA27X_DMA_NUM_CHANNELS 32 |
|
| 46 |
|
|
| 47 |
#define PXA2XX_DMA_NUM_REQUESTS 75 |
|
| 49 |
} PXA2xxDMAState; |
|
| 48 | 50 |
|
| 49 | 51 |
#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */ |
| 50 | 52 |
#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ |
| ... | ... | |
| 424 | 426 |
pxa2xx_dma_write |
| 425 | 427 |
}; |
| 426 | 428 |
|
| 427 |
static void pxa2xx_dma_save(QEMUFile *f, void *opaque) |
|
| 428 |
{
|
|
| 429 |
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
|
| 430 |
int i; |
|
| 431 |
|
|
| 432 |
qemu_put_be32(f, s->channels); |
|
| 433 |
|
|
| 434 |
qemu_put_be32s(f, &s->stopintr); |
|
| 435 |
qemu_put_be32s(f, &s->eorintr); |
|
| 436 |
qemu_put_be32s(f, &s->rasintr); |
|
| 437 |
qemu_put_be32s(f, &s->startintr); |
|
| 438 |
qemu_put_be32s(f, &s->endintr); |
|
| 439 |
qemu_put_be32s(f, &s->align); |
|
| 440 |
qemu_put_be32s(f, &s->pio); |
|
| 441 |
|
|
| 442 |
qemu_put_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); |
|
| 443 |
for (i = 0; i < s->channels; i ++) {
|
|
| 444 |
qemu_put_betl(f, s->chan[i].descr); |
|
| 445 |
qemu_put_betl(f, s->chan[i].src); |
|
| 446 |
qemu_put_betl(f, s->chan[i].dest); |
|
| 447 |
qemu_put_be32s(f, &s->chan[i].cmd); |
|
| 448 |
qemu_put_be32s(f, &s->chan[i].state); |
|
| 449 |
qemu_put_be32(f, s->chan[i].request); |
|
| 450 |
}; |
|
| 451 |
} |
|
| 429 |
static void pxa2xx_dma_request(void *opaque, int req_num, int on); |
|
| 452 | 430 |
|
| 453 |
static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) |
|
| 454 |
{
|
|
| 455 |
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
|
| 456 |
int i; |
|
| 457 |
|
|
| 458 |
if (qemu_get_be32(f) != s->channels) |
|
| 459 |
return -EINVAL; |
|
| 460 |
|
|
| 461 |
qemu_get_be32s(f, &s->stopintr); |
|
| 462 |
qemu_get_be32s(f, &s->eorintr); |
|
| 463 |
qemu_get_be32s(f, &s->rasintr); |
|
| 464 |
qemu_get_be32s(f, &s->startintr); |
|
| 465 |
qemu_get_be32s(f, &s->endintr); |
|
| 466 |
qemu_get_be32s(f, &s->align); |
|
| 467 |
qemu_get_be32s(f, &s->pio); |
|
| 468 |
|
|
| 469 |
qemu_get_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); |
|
| 470 |
for (i = 0; i < s->channels; i ++) {
|
|
| 471 |
s->chan[i].descr = qemu_get_betl(f); |
|
| 472 |
s->chan[i].src = qemu_get_betl(f); |
|
| 473 |
s->chan[i].dest = qemu_get_betl(f); |
|
| 474 |
qemu_get_be32s(f, &s->chan[i].cmd); |
|
| 475 |
qemu_get_be32s(f, &s->chan[i].state); |
|
| 476 |
s->chan[i].request = qemu_get_be32(f); |
|
| 477 |
}; |
|
| 478 |
|
|
| 479 |
return 0; |
|
| 480 |
} |
|
| 481 |
|
|
| 482 |
static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base, |
|
| 483 |
qemu_irq irq, int channels) |
|
| 431 |
static int pxa2xx_dma_init(SysBusDevice *dev) |
|
| 484 | 432 |
{
|
| 485 | 433 |
int i, iomemtype; |
| 486 | 434 |
PXA2xxDMAState *s; |
| 487 |
s = (PXA2xxDMAState *) |
|
| 488 |
qemu_mallocz(sizeof(PXA2xxDMAState)); |
|
| 435 |
s = FROM_SYSBUS(PXA2xxDMAState, dev); |
|
| 436 |
|
|
| 437 |
if (s->channels <= 0) {
|
|
| 438 |
return -1; |
|
| 439 |
} |
|
| 489 | 440 |
|
| 490 |
s->channels = channels; |
|
| 491 | 441 |
s->chan = qemu_mallocz(sizeof(PXA2xxDMAChannel) * s->channels); |
| 492 |
s->irq = irq; |
|
| 493 |
s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); |
|
| 494 | 442 |
|
| 495 | 443 |
memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels); |
| 496 | 444 |
for (i = 0; i < s->channels; i ++) |
| ... | ... | |
| 498 | 446 |
|
| 499 | 447 |
memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); |
| 500 | 448 |
|
| 449 |
qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS); |
|
| 450 |
|
|
| 501 | 451 |
iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn, |
| 502 | 452 |
pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN); |
| 503 |
cpu_register_physical_memory(base, 0x00010000, iomemtype); |
|
| 453 |
sysbus_init_mmio(dev, 0x00010000, iomemtype); |
|
| 454 |
sysbus_init_irq(dev, &s->irq); |
|
| 504 | 455 |
|
| 505 |
register_savevm(NULL, "pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s); |
|
| 506 |
|
|
| 507 |
return s; |
|
| 456 |
return 0; |
|
| 508 | 457 |
} |
| 509 | 458 |
|
| 510 |
PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, |
|
| 511 |
qemu_irq irq) |
|
| 459 |
DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq) |
|
| 512 | 460 |
{
|
| 513 |
return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS); |
|
| 461 |
DeviceState *dev; |
|
| 462 |
|
|
| 463 |
dev = qdev_create(NULL, "pxa2xx-dma"); |
|
| 464 |
qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); |
|
| 465 |
qdev_init_nofail(dev); |
|
| 466 |
|
|
| 467 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); |
|
| 468 |
sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); |
|
| 469 |
|
|
| 470 |
return dev; |
|
| 514 | 471 |
} |
| 515 | 472 |
|
| 516 |
PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, |
|
| 517 |
qemu_irq irq) |
|
| 473 |
DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq) |
|
| 518 | 474 |
{
|
| 519 |
return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS); |
|
| 475 |
DeviceState *dev; |
|
| 476 |
|
|
| 477 |
dev = qdev_create(NULL, "pxa2xx-dma"); |
|
| 478 |
qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); |
|
| 479 |
qdev_init_nofail(dev); |
|
| 480 |
|
|
| 481 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); |
|
| 482 |
sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); |
|
| 483 |
|
|
| 484 |
return dev; |
|
| 520 | 485 |
} |
| 521 | 486 |
|
| 522 |
void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on)
|
|
| 487 |
static void pxa2xx_dma_request(void *opaque, int req_num, int on)
|
|
| 523 | 488 |
{
|
| 489 |
PXA2xxDMAState *s = opaque; |
|
| 524 | 490 |
int ch; |
| 525 | 491 |
if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) |
| 526 | 492 |
hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
|
| ... | ... | |
| 542 | 508 |
pxa2xx_dma_update(s, ch); |
| 543 | 509 |
} |
| 544 | 510 |
} |
| 511 |
|
|
| 512 |
static bool is_version_0(void *opaque, int version_id) |
|
| 513 |
{
|
|
| 514 |
return version_id == 0; |
|
| 515 |
} |
|
| 516 |
|
|
| 517 |
static VMStateDescription vmstate_pxa2xx_dma_chan = {
|
|
| 518 |
.name = "pxa2xx_dma_chan", |
|
| 519 |
.version_id = 1, |
|
| 520 |
.minimum_version_id = 1, |
|
| 521 |
.minimum_version_id_old = 1, |
|
| 522 |
.fields = (VMStateField[]) {
|
|
| 523 |
VMSTATE_UINTTL(descr, PXA2xxDMAChannel), |
|
| 524 |
VMSTATE_UINTTL(src, PXA2xxDMAChannel), |
|
| 525 |
VMSTATE_UINTTL(dest, PXA2xxDMAChannel), |
|
| 526 |
VMSTATE_UINT32(cmd, PXA2xxDMAChannel), |
|
| 527 |
VMSTATE_UINT32(state, PXA2xxDMAChannel), |
|
| 528 |
VMSTATE_INT32(request, PXA2xxDMAChannel), |
|
| 529 |
VMSTATE_END_OF_LIST(), |
|
| 530 |
}, |
|
| 531 |
}; |
|
| 532 |
|
|
| 533 |
static VMStateDescription vmstate_pxa2xx_dma = {
|
|
| 534 |
.name = "pxa2xx_dma", |
|
| 535 |
.version_id = 1, |
|
| 536 |
.minimum_version_id = 0, |
|
| 537 |
.minimum_version_id_old = 0, |
|
| 538 |
.fields = (VMStateField[]) {
|
|
| 539 |
VMSTATE_UNUSED_TEST(is_version_0, 4), |
|
| 540 |
VMSTATE_UINT32(stopintr, PXA2xxDMAState), |
|
| 541 |
VMSTATE_UINT32(eorintr, PXA2xxDMAState), |
|
| 542 |
VMSTATE_UINT32(rasintr, PXA2xxDMAState), |
|
| 543 |
VMSTATE_UINT32(startintr, PXA2xxDMAState), |
|
| 544 |
VMSTATE_UINT32(endintr, PXA2xxDMAState), |
|
| 545 |
VMSTATE_UINT32(align, PXA2xxDMAState), |
|
| 546 |
VMSTATE_UINT32(pio, PXA2xxDMAState), |
|
| 547 |
VMSTATE_BUFFER(req, PXA2xxDMAState), |
|
| 548 |
VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels, |
|
| 549 |
vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel), |
|
| 550 |
VMSTATE_END_OF_LIST(), |
|
| 551 |
}, |
|
| 552 |
}; |
|
| 553 |
|
|
| 554 |
static SysBusDeviceInfo pxa2xx_dma_info = {
|
|
| 555 |
.init = pxa2xx_dma_init, |
|
| 556 |
.qdev.name = "pxa2xx-dma", |
|
| 557 |
.qdev.desc = "PXA2xx DMA controller", |
|
| 558 |
.qdev.size = sizeof(PXA2xxDMAState), |
|
| 559 |
.qdev.vmsd = &vmstate_pxa2xx_dma, |
|
| 560 |
.qdev.props = (Property[]) {
|
|
| 561 |
DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
|
|
| 562 |
DEFINE_PROP_END_OF_LIST(), |
|
| 563 |
}, |
|
| 564 |
}; |
|
| 565 |
|
|
| 566 |
static void pxa2xx_dma_register(void) |
|
| 567 |
{
|
|
| 568 |
sysbus_register_withprop(&pxa2xx_dma_info); |
|
| 569 |
} |
|
| 570 |
device_init(pxa2xx_dma_register); |
|
| b/hw/pxa2xx_mmci.c | ||
|---|---|---|
| 10 | 10 |
#include "hw.h" |
| 11 | 11 |
#include "pxa.h" |
| 12 | 12 |
#include "sd.h" |
| 13 |
#include "qdev.h" |
|
| 13 | 14 |
|
| 14 | 15 |
struct PXA2xxMMCIState {
|
| 15 | 16 |
qemu_irq irq; |
| 16 |
void *dma; |
|
| 17 |
qemu_irq rx_dma; |
|
| 18 |
qemu_irq tx_dma; |
|
| 17 | 19 |
|
| 18 | 20 |
SDState *card; |
| 19 | 21 |
|
| ... | ... | |
| 102 | 104 |
if (s->cmdat & CMDAT_DMA_EN) {
|
| 103 | 105 |
mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ; |
| 104 | 106 |
|
| 105 |
pxa2xx_dma_request(s->dma, |
|
| 106 |
PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ)); |
|
| 107 |
pxa2xx_dma_request(s->dma, |
|
| 108 |
PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ)); |
|
| 107 |
qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ)); |
|
| 108 |
qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ)); |
|
| 109 | 109 |
} |
| 110 | 110 |
|
| 111 | 111 |
qemu_set_irq(s->irq, !!(s->intreq & ~mask)); |
| ... | ... | |
| 518 | 518 |
} |
| 519 | 519 |
|
| 520 | 520 |
PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, |
| 521 |
BlockDriverState *bd, qemu_irq irq, void *dma) |
|
| 521 |
BlockDriverState *bd, qemu_irq irq, |
|
| 522 |
qemu_irq rx_dma, qemu_irq tx_dma) |
|
| 522 | 523 |
{
|
| 523 | 524 |
int iomemtype; |
| 524 | 525 |
PXA2xxMMCIState *s; |
| 525 | 526 |
|
| 526 | 527 |
s = (PXA2xxMMCIState *) qemu_mallocz(sizeof(PXA2xxMMCIState)); |
| 527 | 528 |
s->irq = irq; |
| 528 |
s->dma = dma; |
|
| 529 |
s->rx_dma = rx_dma; |
|
| 530 |
s->tx_dma = tx_dma; |
|
| 529 | 531 |
|
| 530 | 532 |
iomemtype = cpu_register_io_memory(pxa2xx_mmci_readfn, |
| 531 | 533 |
pxa2xx_mmci_writefn, s, DEVICE_NATIVE_ENDIAN); |
Also available in: Unified diff