Revision 2115c019 hw/pxa.h
| b/hw/pxa.h | ||
|---|---|---|
| 71 | 71 |
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); |
| 72 | 72 |
|
| 73 | 73 |
/* pxa2xx_dma.c */ |
| 74 |
typedef struct PXA2xxDMAState PXA2xxDMAState; |
|
| 75 |
PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, |
|
| 76 |
qemu_irq irq); |
|
| 77 |
PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, |
|
| 78 |
qemu_irq irq); |
|
| 79 |
void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on); |
|
| 74 |
DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq); |
|
| 75 |
DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq); |
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| 80 | 76 |
|
| 81 | 77 |
/* pxa2xx_lcd.c */ |
| 82 | 78 |
typedef struct PXA2xxLCDState PXA2xxLCDState; |
| ... | ... | |
| 88 | 84 |
/* pxa2xx_mmci.c */ |
| 89 | 85 |
typedef struct PXA2xxMMCIState PXA2xxMMCIState; |
| 90 | 86 |
PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, |
| 91 |
BlockDriverState *bd, qemu_irq irq, void *dma); |
|
| 87 |
BlockDriverState *bd, qemu_irq irq, |
|
| 88 |
qemu_irq rx_dma, qemu_irq tx_dma); |
|
| 92 | 89 |
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, |
| 93 | 90 |
qemu_irq coverswitch); |
| 94 | 91 |
|
| ... | ... | |
| 123 | 120 |
CPUState *env; |
| 124 | 121 |
DeviceState *pic; |
| 125 | 122 |
qemu_irq reset; |
| 126 |
PXA2xxDMAState *dma;
|
|
| 123 |
DeviceState *dma;
|
|
| 127 | 124 |
DeviceState *gpio; |
| 128 | 125 |
PXA2xxLCDState *lcd; |
| 129 | 126 |
SSIBus **ssp; |
| ... | ... | |
| 181 | 178 |
|
| 182 | 179 |
struct PXA2xxI2SState {
|
| 183 | 180 |
qemu_irq irq; |
| 184 |
PXA2xxDMAState *dma; |
|
| 181 |
qemu_irq rx_dma; |
|
| 182 |
qemu_irq tx_dma; |
|
| 185 | 183 |
void (*data_req)(void *, int, int); |
| 186 | 184 |
|
| 187 | 185 |
uint32_t control[2]; |
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