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/*
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* Intel XScale PXA255/270 processor support.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licenced under the GPL.
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*/
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#include "sysbus.h" |
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#include "pxa.h" |
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#include "sysemu.h" |
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#include "pc.h" |
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#include "i2c.h" |
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#include "ssi.h" |
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#include "qemu-timer.h" |
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#include "qemu-char.h" |
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#include "blockdev.h" |
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|
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static struct { |
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target_phys_addr_t io_base; |
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int irqn;
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} pxa255_serial[] = { |
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{ 0x40100000, PXA2XX_PIC_FFUART },
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{ 0x40200000, PXA2XX_PIC_BTUART },
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{ 0x40700000, PXA2XX_PIC_STUART },
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{ 0x41600000, PXA25X_PIC_HWUART },
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{ 0, 0 } |
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}, pxa270_serial[] = { |
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{ 0x40100000, PXA2XX_PIC_FFUART },
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{ 0x40200000, PXA2XX_PIC_BTUART },
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{ 0x40700000, PXA2XX_PIC_STUART },
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{ 0, 0 } |
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}; |
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typedef struct PXASSPDef { |
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target_phys_addr_t io_base; |
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int irqn;
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} PXASSPDef; |
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#if 0
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static PXASSPDef pxa250_ssp[] = {
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0, 0 }
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};
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#endif
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static PXASSPDef pxa255_ssp[] = {
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41400000, PXA25X_PIC_NSSP },
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{ 0, 0 } |
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}; |
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#if 0
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static PXASSPDef pxa26x_ssp[] = {
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41400000, PXA25X_PIC_NSSP },
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{ 0x41500000, PXA26X_PIC_ASSP },
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{ 0, 0 }
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};
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#endif
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static PXASSPDef pxa27x_ssp[] = {
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41700000, PXA27X_PIC_SSP2 },
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{ 0x41900000, PXA2XX_PIC_SSP3 },
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{ 0, 0 } |
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}; |
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|
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#define PMCR 0x00 /* Power Manager Control register */ |
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#define PSSR 0x04 /* Power Manager Sleep Status register */ |
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#define PSPR 0x08 /* Power Manager Scratch-Pad register */ |
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#define PWER 0x0c /* Power Manager Wake-Up Enable register */ |
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#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ |
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#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ |
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#define PEDR 0x18 /* Power Manager Edge-Detect Status register */ |
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#define PCFR 0x1c /* Power Manager General Configuration register */ |
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#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ |
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#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ |
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#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ |
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#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ |
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#define RCSR 0x30 /* Reset Controller Status register */ |
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#define PSLR 0x34 /* Power Manager Sleep Configuration register */ |
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#define PTSR 0x38 /* Power Manager Standby Configuration register */ |
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#define PVCR 0x40 /* Power Manager Voltage Change Control register */ |
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#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ |
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#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ |
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#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ |
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#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ |
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#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ |
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|
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static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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|
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switch (addr) {
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case PMCR ... PCMD31:
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if (addr & 3) |
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goto fail;
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|
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return s->pm_regs[addr >> 2]; |
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default:
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fail:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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return 0; |
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} |
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|
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static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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|
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switch (addr) {
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case PMCR:
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s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a); |
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s->pm_regs[addr >> 2] |= value & 0x15; |
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break;
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|
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case PSSR: /* Read-clean registers */ |
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case RCSR:
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case PKSR:
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s->pm_regs[addr >> 2] &= ~value;
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break;
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default: /* Read-write registers */ |
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if (!(addr & 3)) { |
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s->pm_regs[addr >> 2] = value;
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break;
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} |
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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} |
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|
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static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = { |
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pxa2xx_pm_read, |
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pxa2xx_pm_read, |
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pxa2xx_pm_read, |
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}; |
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|
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static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = { |
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pxa2xx_pm_write, |
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pxa2xx_pm_write, |
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pxa2xx_pm_write, |
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}; |
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|
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static void pxa2xx_pm_save(QEMUFile *f, void *opaque) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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int i;
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for (i = 0; i < 0x40; i ++) |
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qemu_put_be32s(f, &s->pm_regs[i]); |
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} |
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static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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int i;
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for (i = 0; i < 0x40; i ++) |
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qemu_get_be32s(f, &s->pm_regs[i]); |
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return 0; |
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} |
169 |
|
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#define CCCR 0x00 /* Core Clock Configuration register */ |
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#define CKEN 0x04 /* Clock Enable register */ |
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#define OSCC 0x08 /* Oscillator Configuration register */ |
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#define CCSR 0x0c /* Core Clock Status register */ |
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|
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static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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switch (addr) {
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case CCCR:
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case CKEN:
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case OSCC:
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return s->cm_regs[addr >> 2]; |
184 |
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case CCSR:
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return s->cm_regs[CCCR >> 2] | (3 << 28); |
187 |
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default:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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return 0; |
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} |
194 |
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static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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switch (addr) {
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case CCCR:
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case CKEN:
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s->cm_regs[addr >> 2] = value;
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break;
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case OSCC:
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s->cm_regs[addr >> 2] &= ~0x6c; |
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s->cm_regs[addr >> 2] |= value & 0x6e; |
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if ((value >> 1) & 1) /* OON */ |
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s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ |
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break;
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default:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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} |
218 |
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static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = { |
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pxa2xx_cm_read, |
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pxa2xx_cm_read, |
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pxa2xx_cm_read, |
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}; |
224 |
|
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static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = { |
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pxa2xx_cm_write, |
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pxa2xx_cm_write, |
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pxa2xx_cm_write, |
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}; |
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static void pxa2xx_cm_save(QEMUFile *f, void *opaque) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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int i;
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for (i = 0; i < 4; i ++) |
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qemu_put_be32s(f, &s->cm_regs[i]); |
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qemu_put_be32s(f, &s->clkcfg); |
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qemu_put_be32s(f, &s->pmnc); |
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} |
241 |
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static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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int i;
|
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for (i = 0; i < 4; i ++) |
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qemu_get_be32s(f, &s->cm_regs[i]); |
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qemu_get_be32s(f, &s->clkcfg); |
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qemu_get_be32s(f, &s->pmnc); |
251 |
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return 0; |
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} |
254 |
|
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static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) |
256 |
{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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switch (reg) {
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case 6: /* Clock Configuration register */ |
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return s->clkcfg;
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case 7: /* Power Mode register */ |
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return 0; |
265 |
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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} |
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return 0; |
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} |
272 |
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static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, |
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uint32_t value) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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static const char *pwrmode[8] = { |
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"Normal", "Idle", "Deep-idle", "Standby", |
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"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", |
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}; |
281 |
|
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switch (reg) {
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case 6: /* Clock Configuration register */ |
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s->clkcfg = value & 0xf;
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if (value & 2) |
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printf("%s: CPU frequency change attempt\n", __FUNCTION__);
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break;
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case 7: /* Power Mode register */ |
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if (value & 8) |
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printf("%s: CPU voltage change attempt\n", __FUNCTION__);
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switch (value & 7) { |
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case 0: |
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/* Do nothing */
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break;
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|
297 |
case 1: |
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/* Idle */
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if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ |
300 |
cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
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break;
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} |
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/* Fall through. */
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|
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case 2: |
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/* Deep-Idle */
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cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
309 |
goto message;
|
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|
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case 3: |
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s->env->uncached_cpsr = |
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ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
314 |
s->env->cp15.c1_sys = 0;
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s->env->cp15.c1_coproc = 0;
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s->env->cp15.c2_base0 = 0;
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s->env->cp15.c3 = 0;
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s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ |
319 |
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
320 |
|
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/*
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* The scratch-pad register is almost universally used
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* for storing the return address on suspend. For the
|
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* lack of a resuming bootloader, perform a jump
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* directly to that address.
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*/
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memset(s->env->regs, 0, 4 * 15); |
328 |
s->env->regs[15] = s->pm_regs[PSPR >> 2]; |
329 |
|
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#if 0
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buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
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cpu_physical_memory_write(0, &buffer, 4);
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buffer = s->pm_regs[PSPR >> 2];
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cpu_physical_memory_write(8, &buffer, 4);
|
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#endif
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|
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/* Suspend */
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
339 |
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goto message;
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341 |
|
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default:
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343 |
message:
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344 |
printf("%s: machine entered %s mode\n", __FUNCTION__,
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pwrmode[value & 7]);
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346 |
} |
347 |
break;
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348 |
|
349 |
default:
|
350 |
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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} |
353 |
} |
354 |
|
355 |
/* Performace Monitoring Registers */
|
356 |
#define CPPMNC 0 /* Performance Monitor Control register */ |
357 |
#define CPCCNT 1 /* Clock Counter register */ |
358 |
#define CPINTEN 4 /* Interrupt Enable register */ |
359 |
#define CPFLAG 5 /* Overflow Flag register */ |
360 |
#define CPEVTSEL 8 /* Event Selection register */ |
361 |
|
362 |
#define CPPMN0 0 /* Performance Count register 0 */ |
363 |
#define CPPMN1 1 /* Performance Count register 1 */ |
364 |
#define CPPMN2 2 /* Performance Count register 2 */ |
365 |
#define CPPMN3 3 /* Performance Count register 3 */ |
366 |
|
367 |
static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm) |
368 |
{ |
369 |
PXA2xxState *s = (PXA2xxState *) opaque; |
370 |
|
371 |
switch (reg) {
|
372 |
case CPPMNC:
|
373 |
return s->pmnc;
|
374 |
case CPCCNT:
|
375 |
if (s->pmnc & 1) |
376 |
return qemu_get_clock(vm_clock);
|
377 |
else
|
378 |
return 0; |
379 |
case CPINTEN:
|
380 |
case CPFLAG:
|
381 |
case CPEVTSEL:
|
382 |
return 0; |
383 |
|
384 |
default:
|
385 |
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
386 |
break;
|
387 |
} |
388 |
return 0; |
389 |
} |
390 |
|
391 |
static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm, |
392 |
uint32_t value) |
393 |
{ |
394 |
PXA2xxState *s = (PXA2xxState *) opaque; |
395 |
|
396 |
switch (reg) {
|
397 |
case CPPMNC:
|
398 |
s->pmnc = value; |
399 |
break;
|
400 |
|
401 |
case CPCCNT:
|
402 |
case CPINTEN:
|
403 |
case CPFLAG:
|
404 |
case CPEVTSEL:
|
405 |
break;
|
406 |
|
407 |
default:
|
408 |
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
409 |
break;
|
410 |
} |
411 |
} |
412 |
|
413 |
static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm) |
414 |
{ |
415 |
switch (crm) {
|
416 |
case 0: |
417 |
return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
|
418 |
case 1: |
419 |
return pxa2xx_perf_read(opaque, op2, reg, crm);
|
420 |
case 2: |
421 |
switch (reg) {
|
422 |
case CPPMN0:
|
423 |
case CPPMN1:
|
424 |
case CPPMN2:
|
425 |
case CPPMN3:
|
426 |
return 0; |
427 |
} |
428 |
/* Fall through */
|
429 |
default:
|
430 |
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
431 |
break;
|
432 |
} |
433 |
return 0; |
434 |
} |
435 |
|
436 |
static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm, |
437 |
uint32_t value) |
438 |
{ |
439 |
switch (crm) {
|
440 |
case 0: |
441 |
pxa2xx_clkpwr_write(opaque, op2, reg, crm, value); |
442 |
break;
|
443 |
case 1: |
444 |
pxa2xx_perf_write(opaque, op2, reg, crm, value); |
445 |
break;
|
446 |
case 2: |
447 |
switch (reg) {
|
448 |
case CPPMN0:
|
449 |
case CPPMN1:
|
450 |
case CPPMN2:
|
451 |
case CPPMN3:
|
452 |
return;
|
453 |
} |
454 |
/* Fall through */
|
455 |
default:
|
456 |
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
457 |
break;
|
458 |
} |
459 |
} |
460 |
|
461 |
#define MDCNFG 0x00 /* SDRAM Configuration register */ |
462 |
#define MDREFR 0x04 /* SDRAM Refresh Control register */ |
463 |
#define MSC0 0x08 /* Static Memory Control register 0 */ |
464 |
#define MSC1 0x0c /* Static Memory Control register 1 */ |
465 |
#define MSC2 0x10 /* Static Memory Control register 2 */ |
466 |
#define MECR 0x14 /* Expansion Memory Bus Config register */ |
467 |
#define SXCNFG 0x1c /* Synchronous Static Memory Config register */ |
468 |
#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ |
469 |
#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ |
470 |
#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ |
471 |
#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ |
472 |
#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ |
473 |
#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ |
474 |
#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ |
475 |
#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ |
476 |
#define ARB_CNTL 0x48 /* Arbiter Control register */ |
477 |
#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ |
478 |
#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ |
479 |
#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ |
480 |
#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ |
481 |
#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ |
482 |
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ |
483 |
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */ |
484 |
|
485 |
static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) |
486 |
{ |
487 |
PXA2xxState *s = (PXA2xxState *) opaque; |
488 |
|
489 |
switch (addr) {
|
490 |
case MDCNFG ... SA1110:
|
491 |
if ((addr & 3) == 0) |
492 |
return s->mm_regs[addr >> 2]; |
493 |
|
494 |
default:
|
495 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
496 |
break;
|
497 |
} |
498 |
return 0; |
499 |
} |
500 |
|
501 |
static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr, |
502 |
uint32_t value) |
503 |
{ |
504 |
PXA2xxState *s = (PXA2xxState *) opaque; |
505 |
|
506 |
switch (addr) {
|
507 |
case MDCNFG ... SA1110:
|
508 |
if ((addr & 3) == 0) { |
509 |
s->mm_regs[addr >> 2] = value;
|
510 |
break;
|
511 |
} |
512 |
|
513 |
default:
|
514 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
515 |
break;
|
516 |
} |
517 |
} |
518 |
|
519 |
static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = { |
520 |
pxa2xx_mm_read, |
521 |
pxa2xx_mm_read, |
522 |
pxa2xx_mm_read, |
523 |
}; |
524 |
|
525 |
static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = { |
526 |
pxa2xx_mm_write, |
527 |
pxa2xx_mm_write, |
528 |
pxa2xx_mm_write, |
529 |
}; |
530 |
|
531 |
static void pxa2xx_mm_save(QEMUFile *f, void *opaque) |
532 |
{ |
533 |
PXA2xxState *s = (PXA2xxState *) opaque; |
534 |
int i;
|
535 |
|
536 |
for (i = 0; i < 0x1a; i ++) |
537 |
qemu_put_be32s(f, &s->mm_regs[i]); |
538 |
} |
539 |
|
540 |
static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id) |
541 |
{ |
542 |
PXA2xxState *s = (PXA2xxState *) opaque; |
543 |
int i;
|
544 |
|
545 |
for (i = 0; i < 0x1a; i ++) |
546 |
qemu_get_be32s(f, &s->mm_regs[i]); |
547 |
|
548 |
return 0; |
549 |
} |
550 |
|
551 |
/* Synchronous Serial Ports */
|
552 |
typedef struct { |
553 |
SysBusDevice busdev; |
554 |
qemu_irq irq; |
555 |
int enable;
|
556 |
SSIBus *bus; |
557 |
|
558 |
uint32_t sscr[2];
|
559 |
uint32_t sspsp; |
560 |
uint32_t ssto; |
561 |
uint32_t ssitr; |
562 |
uint32_t sssr; |
563 |
uint8_t sstsa; |
564 |
uint8_t ssrsa; |
565 |
uint8_t ssacd; |
566 |
|
567 |
uint32_t rx_fifo[16];
|
568 |
int rx_level;
|
569 |
int rx_start;
|
570 |
} PXA2xxSSPState; |
571 |
|
572 |
#define SSCR0 0x00 /* SSP Control register 0 */ |
573 |
#define SSCR1 0x04 /* SSP Control register 1 */ |
574 |
#define SSSR 0x08 /* SSP Status register */ |
575 |
#define SSITR 0x0c /* SSP Interrupt Test register */ |
576 |
#define SSDR 0x10 /* SSP Data register */ |
577 |
#define SSTO 0x28 /* SSP Time-Out register */ |
578 |
#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ |
579 |
#define SSTSA 0x30 /* SSP TX Time Slot Active register */ |
580 |
#define SSRSA 0x34 /* SSP RX Time Slot Active register */ |
581 |
#define SSTSS 0x38 /* SSP Time Slot Status register */ |
582 |
#define SSACD 0x3c /* SSP Audio Clock Divider register */ |
583 |
|
584 |
/* Bitfields for above registers */
|
585 |
#define SSCR0_SPI(x) (((x) & 0x30) == 0x00) |
586 |
#define SSCR0_SSP(x) (((x) & 0x30) == 0x10) |
587 |
#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) |
588 |
#define SSCR0_PSP(x) (((x) & 0x30) == 0x30) |
589 |
#define SSCR0_SSE (1 << 7) |
590 |
#define SSCR0_RIM (1 << 22) |
591 |
#define SSCR0_TIM (1 << 23) |
592 |
#define SSCR0_MOD (1 << 31) |
593 |
#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) |
594 |
#define SSCR1_RIE (1 << 0) |
595 |
#define SSCR1_TIE (1 << 1) |
596 |
#define SSCR1_LBM (1 << 2) |
597 |
#define SSCR1_MWDS (1 << 5) |
598 |
#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) |
599 |
#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) |
600 |
#define SSCR1_EFWR (1 << 14) |
601 |
#define SSCR1_PINTE (1 << 18) |
602 |
#define SSCR1_TINTE (1 << 19) |
603 |
#define SSCR1_RSRE (1 << 20) |
604 |
#define SSCR1_TSRE (1 << 21) |
605 |
#define SSCR1_EBCEI (1 << 29) |
606 |
#define SSITR_INT (7 << 5) |
607 |
#define SSSR_TNF (1 << 2) |
608 |
#define SSSR_RNE (1 << 3) |
609 |
#define SSSR_TFS (1 << 5) |
610 |
#define SSSR_RFS (1 << 6) |
611 |
#define SSSR_ROR (1 << 7) |
612 |
#define SSSR_PINT (1 << 18) |
613 |
#define SSSR_TINT (1 << 19) |
614 |
#define SSSR_EOC (1 << 20) |
615 |
#define SSSR_TUR (1 << 21) |
616 |
#define SSSR_BCE (1 << 23) |
617 |
#define SSSR_RW 0x00bc0080 |
618 |
|
619 |
static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) |
620 |
{ |
621 |
int level = 0; |
622 |
|
623 |
level |= s->ssitr & SSITR_INT; |
624 |
level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
|
625 |
level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
|
626 |
level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); |
627 |
level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
|
628 |
level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
|
629 |
level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
|
630 |
level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
|
631 |
level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
|
632 |
qemu_set_irq(s->irq, !!level); |
633 |
} |
634 |
|
635 |
static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) |
636 |
{ |
637 |
s->sssr &= ~(0xf << 12); /* Clear RFL */ |
638 |
s->sssr &= ~(0xf << 8); /* Clear TFL */ |
639 |
s->sssr &= ~SSSR_TFS; |
640 |
s->sssr &= ~SSSR_TNF; |
641 |
if (s->enable) {
|
642 |
s->sssr |= ((s->rx_level - 1) & 0xf) << 12; |
643 |
if (s->rx_level >= SSCR1_RFT(s->sscr[1])) |
644 |
s->sssr |= SSSR_RFS; |
645 |
else
|
646 |
s->sssr &= ~SSSR_RFS; |
647 |
if (s->rx_level)
|
648 |
s->sssr |= SSSR_RNE; |
649 |
else
|
650 |
s->sssr &= ~SSSR_RNE; |
651 |
/* TX FIFO is never filled, so it is always in underrun
|
652 |
condition if SSP is enabled */
|
653 |
s->sssr |= SSSR_TFS; |
654 |
s->sssr |= SSSR_TNF; |
655 |
} |
656 |
|
657 |
pxa2xx_ssp_int_update(s); |
658 |
} |
659 |
|
660 |
static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) |
661 |
{ |
662 |
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
663 |
uint32_t retval; |
664 |
|
665 |
switch (addr) {
|
666 |
case SSCR0:
|
667 |
return s->sscr[0]; |
668 |
case SSCR1:
|
669 |
return s->sscr[1]; |
670 |
case SSPSP:
|
671 |
return s->sspsp;
|
672 |
case SSTO:
|
673 |
return s->ssto;
|
674 |
case SSITR:
|
675 |
return s->ssitr;
|
676 |
case SSSR:
|
677 |
return s->sssr | s->ssitr;
|
678 |
case SSDR:
|
679 |
if (!s->enable)
|
680 |
return 0xffffffff; |
681 |
if (s->rx_level < 1) { |
682 |
printf("%s: SSP Rx Underrun\n", __FUNCTION__);
|
683 |
return 0xffffffff; |
684 |
} |
685 |
s->rx_level --; |
686 |
retval = s->rx_fifo[s->rx_start ++]; |
687 |
s->rx_start &= 0xf;
|
688 |
pxa2xx_ssp_fifo_update(s); |
689 |
return retval;
|
690 |
case SSTSA:
|
691 |
return s->sstsa;
|
692 |
case SSRSA:
|
693 |
return s->ssrsa;
|
694 |
case SSTSS:
|
695 |
return 0; |
696 |
case SSACD:
|
697 |
return s->ssacd;
|
698 |
default:
|
699 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
700 |
break;
|
701 |
} |
702 |
return 0; |
703 |
} |
704 |
|
705 |
static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr, |
706 |
uint32_t value) |
707 |
{ |
708 |
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
709 |
|
710 |
switch (addr) {
|
711 |
case SSCR0:
|
712 |
s->sscr[0] = value & 0xc7ffffff; |
713 |
s->enable = value & SSCR0_SSE; |
714 |
if (value & SSCR0_MOD)
|
715 |
printf("%s: Attempt to use network mode\n", __FUNCTION__);
|
716 |
if (s->enable && SSCR0_DSS(value) < 4) |
717 |
printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
|
718 |
SSCR0_DSS(value)); |
719 |
if (!(value & SSCR0_SSE)) {
|
720 |
s->sssr = 0;
|
721 |
s->ssitr = 0;
|
722 |
s->rx_level = 0;
|
723 |
} |
724 |
pxa2xx_ssp_fifo_update(s); |
725 |
break;
|
726 |
|
727 |
case SSCR1:
|
728 |
s->sscr[1] = value;
|
729 |
if (value & (SSCR1_LBM | SSCR1_EFWR))
|
730 |
printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
|
731 |
pxa2xx_ssp_fifo_update(s); |
732 |
break;
|
733 |
|
734 |
case SSPSP:
|
735 |
s->sspsp = value; |
736 |
break;
|
737 |
|
738 |
case SSTO:
|
739 |
s->ssto = value; |
740 |
break;
|
741 |
|
742 |
case SSITR:
|
743 |
s->ssitr = value & SSITR_INT; |
744 |
pxa2xx_ssp_int_update(s); |
745 |
break;
|
746 |
|
747 |
case SSSR:
|
748 |
s->sssr &= ~(value & SSSR_RW); |
749 |
pxa2xx_ssp_int_update(s); |
750 |
break;
|
751 |
|
752 |
case SSDR:
|
753 |
if (SSCR0_UWIRE(s->sscr[0])) { |
754 |
if (s->sscr[1] & SSCR1_MWDS) |
755 |
value &= 0xffff;
|
756 |
else
|
757 |
value &= 0xff;
|
758 |
} else
|
759 |
/* Note how 32bits overflow does no harm here */
|
760 |
value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; |
761 |
|
762 |
/* Data goes from here to the Tx FIFO and is shifted out from
|
763 |
* there directly to the slave, no need to buffer it.
|
764 |
*/
|
765 |
if (s->enable) {
|
766 |
uint32_t readval; |
767 |
readval = ssi_transfer(s->bus, value); |
768 |
if (s->rx_level < 0x10) { |
769 |
s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
|
770 |
} else {
|
771 |
s->sssr |= SSSR_ROR; |
772 |
} |
773 |
} |
774 |
pxa2xx_ssp_fifo_update(s); |
775 |
break;
|
776 |
|
777 |
case SSTSA:
|
778 |
s->sstsa = value; |
779 |
break;
|
780 |
|
781 |
case SSRSA:
|
782 |
s->ssrsa = value; |
783 |
break;
|
784 |
|
785 |
case SSACD:
|
786 |
s->ssacd = value; |
787 |
break;
|
788 |
|
789 |
default:
|
790 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
791 |
break;
|
792 |
} |
793 |
} |
794 |
|
795 |
static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = { |
796 |
pxa2xx_ssp_read, |
797 |
pxa2xx_ssp_read, |
798 |
pxa2xx_ssp_read, |
799 |
}; |
800 |
|
801 |
static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = { |
802 |
pxa2xx_ssp_write, |
803 |
pxa2xx_ssp_write, |
804 |
pxa2xx_ssp_write, |
805 |
}; |
806 |
|
807 |
static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) |
808 |
{ |
809 |
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
810 |
int i;
|
811 |
|
812 |
qemu_put_be32(f, s->enable); |
813 |
|
814 |
qemu_put_be32s(f, &s->sscr[0]);
|
815 |
qemu_put_be32s(f, &s->sscr[1]);
|
816 |
qemu_put_be32s(f, &s->sspsp); |
817 |
qemu_put_be32s(f, &s->ssto); |
818 |
qemu_put_be32s(f, &s->ssitr); |
819 |
qemu_put_be32s(f, &s->sssr); |
820 |
qemu_put_8s(f, &s->sstsa); |
821 |
qemu_put_8s(f, &s->ssrsa); |
822 |
qemu_put_8s(f, &s->ssacd); |
823 |
|
824 |
qemu_put_byte(f, s->rx_level); |
825 |
for (i = 0; i < s->rx_level; i ++) |
826 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
|
827 |
} |
828 |
|
829 |
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) |
830 |
{ |
831 |
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
832 |
int i;
|
833 |
|
834 |
s->enable = qemu_get_be32(f); |
835 |
|
836 |
qemu_get_be32s(f, &s->sscr[0]);
|
837 |
qemu_get_be32s(f, &s->sscr[1]);
|
838 |
qemu_get_be32s(f, &s->sspsp); |
839 |
qemu_get_be32s(f, &s->ssto); |
840 |
qemu_get_be32s(f, &s->ssitr); |
841 |
qemu_get_be32s(f, &s->sssr); |
842 |
qemu_get_8s(f, &s->sstsa); |
843 |
qemu_get_8s(f, &s->ssrsa); |
844 |
qemu_get_8s(f, &s->ssacd); |
845 |
|
846 |
s->rx_level = qemu_get_byte(f); |
847 |
s->rx_start = 0;
|
848 |
for (i = 0; i < s->rx_level; i ++) |
849 |
s->rx_fifo[i] = qemu_get_byte(f); |
850 |
|
851 |
return 0; |
852 |
} |
853 |
|
854 |
static int pxa2xx_ssp_init(SysBusDevice *dev) |
855 |
{ |
856 |
int iomemtype;
|
857 |
PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev); |
858 |
|
859 |
sysbus_init_irq(dev, &s->irq); |
860 |
|
861 |
iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn, |
862 |
pxa2xx_ssp_writefn, s, |
863 |
DEVICE_NATIVE_ENDIAN); |
864 |
sysbus_init_mmio(dev, 0x1000, iomemtype);
|
865 |
register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0, |
866 |
pxa2xx_ssp_save, pxa2xx_ssp_load, s); |
867 |
|
868 |
s->bus = ssi_create_bus(&dev->qdev, "ssi");
|
869 |
return 0; |
870 |
} |
871 |
|
872 |
/* Real-Time Clock */
|
873 |
#define RCNR 0x00 /* RTC Counter register */ |
874 |
#define RTAR 0x04 /* RTC Alarm register */ |
875 |
#define RTSR 0x08 /* RTC Status register */ |
876 |
#define RTTR 0x0c /* RTC Timer Trim register */ |
877 |
#define RDCR 0x10 /* RTC Day Counter register */ |
878 |
#define RYCR 0x14 /* RTC Year Counter register */ |
879 |
#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ |
880 |
#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ |
881 |
#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ |
882 |
#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ |
883 |
#define SWCR 0x28 /* RTC Stopwatch Counter register */ |
884 |
#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ |
885 |
#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ |
886 |
#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ |
887 |
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ |
888 |
|
889 |
static inline void pxa2xx_rtc_int_update(PXA2xxState *s) |
890 |
{ |
891 |
qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
|
892 |
} |
893 |
|
894 |
static void pxa2xx_rtc_hzupdate(PXA2xxState *s) |
895 |
{ |
896 |
int64_t rt = qemu_get_clock(rt_clock); |
897 |
s->last_rcnr += ((rt - s->last_hz) << 15) /
|
898 |
(1000 * ((s->rttr & 0xffff) + 1)); |
899 |
s->last_rdcr += ((rt - s->last_hz) << 15) /
|
900 |
(1000 * ((s->rttr & 0xffff) + 1)); |
901 |
s->last_hz = rt; |
902 |
} |
903 |
|
904 |
static void pxa2xx_rtc_swupdate(PXA2xxState *s) |
905 |
{ |
906 |
int64_t rt = qemu_get_clock(rt_clock); |
907 |
if (s->rtsr & (1 << 12)) |
908 |
s->last_swcr += (rt - s->last_sw) / 10;
|
909 |
s->last_sw = rt; |
910 |
} |
911 |
|
912 |
static void pxa2xx_rtc_piupdate(PXA2xxState *s) |
913 |
{ |
914 |
int64_t rt = qemu_get_clock(rt_clock); |
915 |
if (s->rtsr & (1 << 15)) |
916 |
s->last_swcr += rt - s->last_pi; |
917 |
s->last_pi = rt; |
918 |
} |
919 |
|
920 |
static inline void pxa2xx_rtc_alarm_update(PXA2xxState *s, |
921 |
uint32_t rtsr) |
922 |
{ |
923 |
if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) |
924 |
qemu_mod_timer(s->rtc_hz, s->last_hz + |
925 |
(((s->rtar - s->last_rcnr) * 1000 *
|
926 |
((s->rttr & 0xffff) + 1)) >> 15)); |
927 |
else
|
928 |
qemu_del_timer(s->rtc_hz); |
929 |
|
930 |
if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) |
931 |
qemu_mod_timer(s->rtc_rdal1, s->last_hz + |
932 |
(((s->rdar1 - s->last_rdcr) * 1000 *
|
933 |
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ |
934 |
else
|
935 |
qemu_del_timer(s->rtc_rdal1); |
936 |
|
937 |
if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) |
938 |
qemu_mod_timer(s->rtc_rdal2, s->last_hz + |
939 |
(((s->rdar2 - s->last_rdcr) * 1000 *
|
940 |
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ |
941 |
else
|
942 |
qemu_del_timer(s->rtc_rdal2); |
943 |
|
944 |
if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) |
945 |
qemu_mod_timer(s->rtc_swal1, s->last_sw + |
946 |
(s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ |
947 |
else
|
948 |
qemu_del_timer(s->rtc_swal1); |
949 |
|
950 |
if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) |
951 |
qemu_mod_timer(s->rtc_swal2, s->last_sw + |
952 |
(s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ |
953 |
else
|
954 |
qemu_del_timer(s->rtc_swal2); |
955 |
|
956 |
if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) |
957 |
qemu_mod_timer(s->rtc_pi, s->last_pi + |
958 |
(s->piar & 0xffff) - s->last_rtcpicr);
|
959 |
else
|
960 |
qemu_del_timer(s->rtc_pi); |
961 |
} |
962 |
|
963 |
static inline void pxa2xx_rtc_hz_tick(void *opaque) |
964 |
{ |
965 |
PXA2xxState *s = (PXA2xxState *) opaque; |
966 |
s->rtsr |= (1 << 0); |
967 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
968 |
pxa2xx_rtc_int_update(s); |
969 |
} |
970 |
|
971 |
static inline void pxa2xx_rtc_rdal1_tick(void *opaque) |
972 |
{ |
973 |
PXA2xxState *s = (PXA2xxState *) opaque; |
974 |
s->rtsr |= (1 << 4); |
975 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
976 |
pxa2xx_rtc_int_update(s); |
977 |
} |
978 |
|
979 |
static inline void pxa2xx_rtc_rdal2_tick(void *opaque) |
980 |
{ |
981 |
PXA2xxState *s = (PXA2xxState *) opaque; |
982 |
s->rtsr |= (1 << 6); |
983 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
984 |
pxa2xx_rtc_int_update(s); |
985 |
} |
986 |
|
987 |
static inline void pxa2xx_rtc_swal1_tick(void *opaque) |
988 |
{ |
989 |
PXA2xxState *s = (PXA2xxState *) opaque; |
990 |
s->rtsr |= (1 << 8); |
991 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
992 |
pxa2xx_rtc_int_update(s); |
993 |
} |
994 |
|
995 |
static inline void pxa2xx_rtc_swal2_tick(void *opaque) |
996 |
{ |
997 |
PXA2xxState *s = (PXA2xxState *) opaque; |
998 |
s->rtsr |= (1 << 10); |
999 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1000 |
pxa2xx_rtc_int_update(s); |
1001 |
} |
1002 |
|
1003 |
static inline void pxa2xx_rtc_pi_tick(void *opaque) |
1004 |
{ |
1005 |
PXA2xxState *s = (PXA2xxState *) opaque; |
1006 |
s->rtsr |= (1 << 13); |
1007 |
pxa2xx_rtc_piupdate(s); |
1008 |
s->last_rtcpicr = 0;
|
1009 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1010 |
pxa2xx_rtc_int_update(s); |
1011 |
} |
1012 |
|
1013 |
static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) |
1014 |
{ |
1015 |
PXA2xxState *s = (PXA2xxState *) opaque; |
1016 |
|
1017 |
switch (addr) {
|
1018 |
case RTTR:
|
1019 |
return s->rttr;
|
1020 |
case RTSR:
|
1021 |
return s->rtsr;
|
1022 |
case RTAR:
|
1023 |
return s->rtar;
|
1024 |
case RDAR1:
|
1025 |
return s->rdar1;
|
1026 |
case RDAR2:
|
1027 |
return s->rdar2;
|
1028 |
case RYAR1:
|
1029 |
return s->ryar1;
|
1030 |
case RYAR2:
|
1031 |
return s->ryar2;
|
1032 |
case SWAR1:
|
1033 |
return s->swar1;
|
1034 |
case SWAR2:
|
1035 |
return s->swar2;
|
1036 |
case PIAR:
|
1037 |
return s->piar;
|
1038 |
case RCNR:
|
1039 |
return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / |
1040 |
(1000 * ((s->rttr & 0xffff) + 1)); |
1041 |
case RDCR:
|
1042 |
return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / |
1043 |
(1000 * ((s->rttr & 0xffff) + 1)); |
1044 |
case RYCR:
|
1045 |
return s->last_rycr;
|
1046 |
case SWCR:
|
1047 |
if (s->rtsr & (1 << 12)) |
1048 |
return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10; |
1049 |
else
|
1050 |
return s->last_swcr;
|
1051 |
default:
|
1052 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1053 |
break;
|
1054 |
} |
1055 |
return 0; |
1056 |
} |
1057 |
|
1058 |
static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr, |
1059 |
uint32_t value) |
1060 |
{ |
1061 |
PXA2xxState *s = (PXA2xxState *) opaque; |
1062 |
|
1063 |
switch (addr) {
|
1064 |
case RTTR:
|
1065 |
if (!(s->rttr & (1 << 31))) { |
1066 |
pxa2xx_rtc_hzupdate(s); |
1067 |
s->rttr = value; |
1068 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1069 |
} |
1070 |
break;
|
1071 |
|
1072 |
case RTSR:
|
1073 |
if ((s->rtsr ^ value) & (1 << 15)) |
1074 |
pxa2xx_rtc_piupdate(s); |
1075 |
|
1076 |
if ((s->rtsr ^ value) & (1 << 12)) |
1077 |
pxa2xx_rtc_swupdate(s); |
1078 |
|
1079 |
if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) |
1080 |
pxa2xx_rtc_alarm_update(s, value); |
1081 |
|
1082 |
s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); |
1083 |
pxa2xx_rtc_int_update(s); |
1084 |
break;
|
1085 |
|
1086 |
case RTAR:
|
1087 |
s->rtar = value; |
1088 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1089 |
break;
|
1090 |
|
1091 |
case RDAR1:
|
1092 |
s->rdar1 = value; |
1093 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1094 |
break;
|
1095 |
|
1096 |
case RDAR2:
|
1097 |
s->rdar2 = value; |
1098 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1099 |
break;
|
1100 |
|
1101 |
case RYAR1:
|
1102 |
s->ryar1 = value; |
1103 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1104 |
break;
|
1105 |
|
1106 |
case RYAR2:
|
1107 |
s->ryar2 = value; |
1108 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1109 |
break;
|
1110 |
|
1111 |
case SWAR1:
|
1112 |
pxa2xx_rtc_swupdate(s); |
1113 |
s->swar1 = value; |
1114 |
s->last_swcr = 0;
|
1115 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1116 |
break;
|
1117 |
|
1118 |
case SWAR2:
|
1119 |
s->swar2 = value; |
1120 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1121 |
break;
|
1122 |
|
1123 |
case PIAR:
|
1124 |
s->piar = value; |
1125 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1126 |
break;
|
1127 |
|
1128 |
case RCNR:
|
1129 |
pxa2xx_rtc_hzupdate(s); |
1130 |
s->last_rcnr = value; |
1131 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1132 |
break;
|
1133 |
|
1134 |
case RDCR:
|
1135 |
pxa2xx_rtc_hzupdate(s); |
1136 |
s->last_rdcr = value; |
1137 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1138 |
break;
|
1139 |
|
1140 |
case RYCR:
|
1141 |
s->last_rycr = value; |
1142 |
break;
|
1143 |
|
1144 |
case SWCR:
|
1145 |
pxa2xx_rtc_swupdate(s); |
1146 |
s->last_swcr = value; |
1147 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1148 |
break;
|
1149 |
|
1150 |
case RTCPICR:
|
1151 |
pxa2xx_rtc_piupdate(s); |
1152 |
s->last_rtcpicr = value & 0xffff;
|
1153 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1154 |
break;
|
1155 |
|
1156 |
default:
|
1157 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1158 |
} |
1159 |
} |
1160 |
|
1161 |
static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = { |
1162 |
pxa2xx_rtc_read, |
1163 |
pxa2xx_rtc_read, |
1164 |
pxa2xx_rtc_read, |
1165 |
}; |
1166 |
|
1167 |
static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = { |
1168 |
pxa2xx_rtc_write, |
1169 |
pxa2xx_rtc_write, |
1170 |
pxa2xx_rtc_write, |
1171 |
}; |
1172 |
|
1173 |
static void pxa2xx_rtc_init(PXA2xxState *s) |
1174 |
{ |
1175 |
struct tm tm;
|
1176 |
int wom;
|
1177 |
|
1178 |
s->rttr = 0x7fff;
|
1179 |
s->rtsr = 0;
|
1180 |
|
1181 |
qemu_get_timedate(&tm, 0);
|
1182 |
wom = ((tm.tm_mday - 1) / 7) + 1; |
1183 |
|
1184 |
s->last_rcnr = (uint32_t) mktimegm(&tm); |
1185 |
s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | |
1186 |
(tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; |
1187 |
s->last_rycr = ((tm.tm_year + 1900) << 9) | |
1188 |
((tm.tm_mon + 1) << 5) | tm.tm_mday; |
1189 |
s->last_swcr = (tm.tm_hour << 19) |
|
1190 |
(tm.tm_min << 13) | (tm.tm_sec << 7); |
1191 |
s->last_rtcpicr = 0;
|
1192 |
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock); |
1193 |
|
1194 |
s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s); |
1195 |
s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s); |
1196 |
s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s); |
1197 |
s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s); |
1198 |
s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s); |
1199 |
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); |
1200 |
|
1201 |
s->rtc_irq = qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM); |
1202 |
} |
1203 |
|
1204 |
static void pxa2xx_rtc_save(QEMUFile *f, void *opaque) |
1205 |
{ |
1206 |
PXA2xxState *s = (PXA2xxState *) opaque; |
1207 |
|
1208 |
pxa2xx_rtc_hzupdate(s); |
1209 |
pxa2xx_rtc_piupdate(s); |
1210 |
pxa2xx_rtc_swupdate(s); |
1211 |
|
1212 |
qemu_put_be32s(f, &s->rttr); |
1213 |
qemu_put_be32s(f, &s->rtsr); |
1214 |
qemu_put_be32s(f, &s->rtar); |
1215 |
qemu_put_be32s(f, &s->rdar1); |
1216 |
qemu_put_be32s(f, &s->rdar2); |
1217 |
qemu_put_be32s(f, &s->ryar1); |
1218 |
qemu_put_be32s(f, &s->ryar2); |
1219 |
qemu_put_be32s(f, &s->swar1); |
1220 |
qemu_put_be32s(f, &s->swar2); |
1221 |
qemu_put_be32s(f, &s->piar); |
1222 |
qemu_put_be32s(f, &s->last_rcnr); |
1223 |
qemu_put_be32s(f, &s->last_rdcr); |
1224 |
qemu_put_be32s(f, &s->last_rycr); |
1225 |
qemu_put_be32s(f, &s->last_swcr); |
1226 |
qemu_put_be32s(f, &s->last_rtcpicr); |
1227 |
qemu_put_sbe64s(f, &s->last_hz); |
1228 |
qemu_put_sbe64s(f, &s->last_sw); |
1229 |
qemu_put_sbe64s(f, &s->last_pi); |
1230 |
} |
1231 |
|
1232 |
static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id) |
1233 |
{ |
1234 |
PXA2xxState *s = (PXA2xxState *) opaque; |
1235 |
|
1236 |
qemu_get_be32s(f, &s->rttr); |
1237 |
qemu_get_be32s(f, &s->rtsr); |
1238 |
qemu_get_be32s(f, &s->rtar); |
1239 |
qemu_get_be32s(f, &s->rdar1); |
1240 |
qemu_get_be32s(f, &s->rdar2); |
1241 |
qemu_get_be32s(f, &s->ryar1); |
1242 |
qemu_get_be32s(f, &s->ryar2); |
1243 |
qemu_get_be32s(f, &s->swar1); |
1244 |
qemu_get_be32s(f, &s->swar2); |
1245 |
qemu_get_be32s(f, &s->piar); |
1246 |
qemu_get_be32s(f, &s->last_rcnr); |
1247 |
qemu_get_be32s(f, &s->last_rdcr); |
1248 |
qemu_get_be32s(f, &s->last_rycr); |
1249 |
qemu_get_be32s(f, &s->last_swcr); |
1250 |
qemu_get_be32s(f, &s->last_rtcpicr); |
1251 |
qemu_get_sbe64s(f, &s->last_hz); |
1252 |
qemu_get_sbe64s(f, &s->last_sw); |
1253 |
qemu_get_sbe64s(f, &s->last_pi); |
1254 |
|
1255 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1256 |
|
1257 |
return 0; |
1258 |
} |
1259 |
|
1260 |
/* I2C Interface */
|
1261 |
typedef struct { |
1262 |
i2c_slave i2c; |
1263 |
PXA2xxI2CState *host; |
1264 |
} PXA2xxI2CSlaveState; |
1265 |
|
1266 |
struct PXA2xxI2CState {
|
1267 |
SysBusDevice busdev; |
1268 |
PXA2xxI2CSlaveState *slave; |
1269 |
i2c_bus *bus; |
1270 |
qemu_irq irq; |
1271 |
uint32_t offset; |
1272 |
uint32_t region_size; |
1273 |
|
1274 |
uint16_t control; |
1275 |
uint16_t status; |
1276 |
uint8_t ibmr; |
1277 |
uint8_t data; |
1278 |
}; |
1279 |
|
1280 |
#define IBMR 0x80 /* I2C Bus Monitor register */ |
1281 |
#define IDBR 0x88 /* I2C Data Buffer register */ |
1282 |
#define ICR 0x90 /* I2C Control register */ |
1283 |
#define ISR 0x98 /* I2C Status register */ |
1284 |
#define ISAR 0xa0 /* I2C Slave Address register */ |
1285 |
|
1286 |
static void pxa2xx_i2c_update(PXA2xxI2CState *s) |
1287 |
{ |
1288 |
uint16_t level = 0;
|
1289 |
level |= s->status & s->control & (1 << 10); /* BED */ |
1290 |
level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ |
1291 |
level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ |
1292 |
level |= s->status & (1 << 9); /* SAD */ |
1293 |
qemu_set_irq(s->irq, !!level); |
1294 |
} |
1295 |
|
1296 |
/* These are only stubs now. */
|
1297 |
static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event) |
1298 |
{ |
1299 |
PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); |
1300 |
PXA2xxI2CState *s = slave->host; |
1301 |
|
1302 |
switch (event) {
|
1303 |
case I2C_START_SEND:
|
1304 |
s->status |= (1 << 9); /* set SAD */ |
1305 |
s->status &= ~(1 << 0); /* clear RWM */ |
1306 |
break;
|
1307 |
case I2C_START_RECV:
|
1308 |
s->status |= (1 << 9); /* set SAD */ |
1309 |
s->status |= 1 << 0; /* set RWM */ |
1310 |
break;
|
1311 |
case I2C_FINISH:
|
1312 |
s->status |= (1 << 4); /* set SSD */ |
1313 |
break;
|
1314 |
case I2C_NACK:
|
1315 |
s->status |= 1 << 1; /* set ACKNAK */ |
1316 |
break;
|
1317 |
} |
1318 |
pxa2xx_i2c_update(s); |
1319 |
} |
1320 |
|
1321 |
static int pxa2xx_i2c_rx(i2c_slave *i2c) |
1322 |
{ |
1323 |
PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); |
1324 |
PXA2xxI2CState *s = slave->host; |
1325 |
if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) |
1326 |
return 0; |
1327 |
|
1328 |
if (s->status & (1 << 0)) { /* RWM */ |
1329 |
s->status |= 1 << 6; /* set ITE */ |
1330 |
} |
1331 |
pxa2xx_i2c_update(s); |
1332 |
|
1333 |
return s->data;
|
1334 |
} |
1335 |
|
1336 |
static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data) |
1337 |
{ |
1338 |
PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c); |
1339 |
PXA2xxI2CState *s = slave->host; |
1340 |
if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) |
1341 |
return 1; |
1342 |
|
1343 |
if (!(s->status & (1 << 0))) { /* RWM */ |
1344 |
s->status |= 1 << 7; /* set IRF */ |
1345 |
s->data = data; |
1346 |
} |
1347 |
pxa2xx_i2c_update(s); |
1348 |
|
1349 |
return 1; |
1350 |
} |
1351 |
|
1352 |
static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) |
1353 |
{ |
1354 |
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
1355 |
|
1356 |
addr -= s->offset; |
1357 |
switch (addr) {
|
1358 |
case ICR:
|
1359 |
return s->control;
|
1360 |
case ISR:
|
1361 |
return s->status | (i2c_bus_busy(s->bus) << 2); |
1362 |
case ISAR:
|
1363 |
return s->slave->i2c.address;
|
1364 |
case IDBR:
|
1365 |
return s->data;
|
1366 |
case IBMR:
|
1367 |
if (s->status & (1 << 2)) |
1368 |
s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ |
1369 |
else
|
1370 |
s->ibmr = 0;
|
1371 |
return s->ibmr;
|
1372 |
default:
|
1373 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1374 |
break;
|
1375 |
} |
1376 |
return 0; |
1377 |
} |
1378 |
|
1379 |
static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, |
1380 |
uint32_t value) |
1381 |
{ |
1382 |
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
1383 |
int ack;
|
1384 |
|
1385 |
addr -= s->offset; |
1386 |
switch (addr) {
|
1387 |
case ICR:
|
1388 |
s->control = value & 0xfff7;
|
1389 |
if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ |
1390 |
/* TODO: slave mode */
|
1391 |
if (value & (1 << 0)) { /* START condition */ |
1392 |
if (s->data & 1) |
1393 |
s->status |= 1 << 0; /* set RWM */ |
1394 |
else
|
1395 |
s->status &= ~(1 << 0); /* clear RWM */ |
1396 |
ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); |
1397 |
} else {
|
1398 |
if (s->status & (1 << 0)) { /* RWM */ |
1399 |
s->data = i2c_recv(s->bus); |
1400 |
if (value & (1 << 2)) /* ACKNAK */ |
1401 |
i2c_nack(s->bus); |
1402 |
ack = 1;
|
1403 |
} else
|
1404 |
ack = !i2c_send(s->bus, s->data); |
1405 |
} |
1406 |
|
1407 |
if (value & (1 << 1)) /* STOP condition */ |
1408 |
i2c_end_transfer(s->bus); |
1409 |
|
1410 |
if (ack) {
|
1411 |
if (value & (1 << 0)) /* START condition */ |
1412 |
s->status |= 1 << 6; /* set ITE */ |
1413 |
else
|
1414 |
if (s->status & (1 << 0)) /* RWM */ |
1415 |
s->status |= 1 << 7; /* set IRF */ |
1416 |
else
|
1417 |
s->status |= 1 << 6; /* set ITE */ |
1418 |
s->status &= ~(1 << 1); /* clear ACKNAK */ |
1419 |
} else {
|
1420 |
s->status |= 1 << 6; /* set ITE */ |
1421 |
s->status |= 1 << 10; /* set BED */ |
1422 |
s->status |= 1 << 1; /* set ACKNAK */ |
1423 |
} |
1424 |
} |
1425 |
if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ |
1426 |
if (value & (1 << 4)) /* MA */ |
1427 |
i2c_end_transfer(s->bus); |
1428 |
pxa2xx_i2c_update(s); |
1429 |
break;
|
1430 |
|
1431 |
case ISR:
|
1432 |
s->status &= ~(value & 0x07f0);
|
1433 |
pxa2xx_i2c_update(s); |
1434 |
break;
|
1435 |
|
1436 |
case ISAR:
|
1437 |
i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
|
1438 |
break;
|
1439 |
|
1440 |
case IDBR:
|
1441 |
s->data = value & 0xff;
|
1442 |
break;
|
1443 |
|
1444 |
default:
|
1445 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1446 |
} |
1447 |
} |
1448 |
|
1449 |
static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = { |
1450 |
pxa2xx_i2c_read, |
1451 |
pxa2xx_i2c_read, |
1452 |
pxa2xx_i2c_read, |
1453 |
}; |
1454 |
|
1455 |
static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = { |
1456 |
pxa2xx_i2c_write, |
1457 |
pxa2xx_i2c_write, |
1458 |
pxa2xx_i2c_write, |
1459 |
}; |
1460 |
|
1461 |
static const VMStateDescription vmstate_pxa2xx_i2c_slave = { |
1462 |
.name = "pxa2xx_i2c_slave",
|
1463 |
.version_id = 1,
|
1464 |
.minimum_version_id = 1,
|
1465 |
.minimum_version_id_old = 1,
|
1466 |
.fields = (VMStateField []) { |
1467 |
VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState), |
1468 |
VMSTATE_END_OF_LIST() |
1469 |
} |
1470 |
}; |
1471 |
|
1472 |
static const VMStateDescription vmstate_pxa2xx_i2c = { |
1473 |
.name = "pxa2xx_i2c",
|
1474 |
.version_id = 1,
|
1475 |
.minimum_version_id = 1,
|
1476 |
.minimum_version_id_old = 1,
|
1477 |
.fields = (VMStateField []) { |
1478 |
VMSTATE_UINT16(control, PXA2xxI2CState), |
1479 |
VMSTATE_UINT16(status, PXA2xxI2CState), |
1480 |
VMSTATE_UINT8(ibmr, PXA2xxI2CState), |
1481 |
VMSTATE_UINT8(data, PXA2xxI2CState), |
1482 |
VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, |
1483 |
vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *), |
1484 |
VMSTATE_END_OF_LIST() |
1485 |
} |
1486 |
}; |
1487 |
|
1488 |
static int pxa2xx_i2c_slave_init(i2c_slave *i2c) |
1489 |
{ |
1490 |
/* Nothing to do. */
|
1491 |
return 0; |
1492 |
} |
1493 |
|
1494 |
static I2CSlaveInfo pxa2xx_i2c_slave_info = {
|
1495 |
.qdev.name = "pxa2xx-i2c-slave",
|
1496 |
.qdev.size = sizeof(PXA2xxI2CSlaveState),
|
1497 |
.init = pxa2xx_i2c_slave_init, |
1498 |
.event = pxa2xx_i2c_event, |
1499 |
.recv = pxa2xx_i2c_rx, |
1500 |
.send = pxa2xx_i2c_tx |
1501 |
}; |
1502 |
|
1503 |
PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, |
1504 |
qemu_irq irq, uint32_t region_size) |
1505 |
{ |
1506 |
DeviceState *dev; |
1507 |
SysBusDevice *i2c_dev; |
1508 |
PXA2xxI2CState *s; |
1509 |
|
1510 |
i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c")); |
1511 |
qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1); |
1512 |
qdev_prop_set_uint32(&i2c_dev->qdev, "offset",
|
1513 |
base - (base & (~region_size) & TARGET_PAGE_MASK)); |
1514 |
|
1515 |
qdev_init_nofail(&i2c_dev->qdev); |
1516 |
|
1517 |
sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
|
1518 |
sysbus_connect_irq(i2c_dev, 0, irq);
|
1519 |
|
1520 |
s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev); |
1521 |
/* FIXME: Should the slave device really be on a separate bus? */
|
1522 |
dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0); |
1523 |
s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev)); |
1524 |
s->slave->host = s; |
1525 |
|
1526 |
return s;
|
1527 |
} |
1528 |
|
1529 |
static int pxa2xx_i2c_initfn(SysBusDevice *dev) |
1530 |
{ |
1531 |
PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev); |
1532 |
int iomemtype;
|
1533 |
|
1534 |
s->bus = i2c_init_bus(&dev->qdev, "i2c");
|
1535 |
|
1536 |
iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn, |
1537 |
pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN); |
1538 |
sysbus_init_mmio(dev, s->region_size, iomemtype); |
1539 |
sysbus_init_irq(dev, &s->irq); |
1540 |
|
1541 |
return 0; |
1542 |
} |
1543 |
|
1544 |
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s) |
1545 |
{ |
1546 |
return s->bus;
|
1547 |
} |
1548 |
|
1549 |
static SysBusDeviceInfo pxa2xx_i2c_info = {
|
1550 |
.init = pxa2xx_i2c_initfn, |
1551 |
.qdev.name = "pxa2xx_i2c",
|
1552 |
.qdev.desc = "PXA2xx I2C Bus Controller",
|
1553 |
.qdev.size = sizeof(PXA2xxI2CState),
|
1554 |
.qdev.vmsd = &vmstate_pxa2xx_i2c, |
1555 |
.qdev.props = (Property[]) { |
1556 |
DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), |
1557 |
DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), |
1558 |
DEFINE_PROP_END_OF_LIST(), |
1559 |
}, |
1560 |
}; |
1561 |
|
1562 |
/* PXA Inter-IC Sound Controller */
|
1563 |
static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) |
1564 |
{ |
1565 |
i2s->rx_len = 0;
|
1566 |
i2s->tx_len = 0;
|
1567 |
i2s->fifo_len = 0;
|
1568 |
i2s->clk = 0x1a;
|
1569 |
i2s->control[0] = 0x00; |
1570 |
i2s->control[1] = 0x00; |
1571 |
i2s->status = 0x00;
|
1572 |
i2s->mask = 0x00;
|
1573 |
} |
1574 |
|
1575 |
#define SACR_TFTH(val) ((val >> 8) & 0xf) |
1576 |
#define SACR_RFTH(val) ((val >> 12) & 0xf) |
1577 |
#define SACR_DREC(val) (val & (1 << 3)) |
1578 |
#define SACR_DPRL(val) (val & (1 << 4)) |
1579 |
|
1580 |
static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) |
1581 |
{ |
1582 |
int rfs, tfs;
|
1583 |
rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
|
1584 |
!SACR_DREC(i2s->control[1]);
|
1585 |
tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
|
1586 |
i2s->enable && !SACR_DPRL(i2s->control[1]);
|
1587 |
|
1588 |
qemu_set_irq(i2s->rx_dma, rfs); |
1589 |
qemu_set_irq(i2s->tx_dma, tfs); |
1590 |
|
1591 |
i2s->status &= 0xe0;
|
1592 |
if (i2s->fifo_len < 16 || !i2s->enable) |
1593 |
i2s->status |= 1 << 0; /* TNF */ |
1594 |
if (i2s->rx_len)
|
1595 |
i2s->status |= 1 << 1; /* RNE */ |
1596 |
if (i2s->enable)
|
1597 |
i2s->status |= 1 << 2; /* BSY */ |
1598 |
if (tfs)
|
1599 |
i2s->status |= 1 << 3; /* TFS */ |
1600 |
if (rfs)
|
1601 |
i2s->status |= 1 << 4; /* RFS */ |
1602 |
if (!(i2s->tx_len && i2s->enable))
|
1603 |
i2s->status |= i2s->fifo_len << 8; /* TFL */ |
1604 |
i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ |
1605 |
|
1606 |
qemu_set_irq(i2s->irq, i2s->status & i2s->mask); |
1607 |
} |
1608 |
|
1609 |
#define SACR0 0x00 /* Serial Audio Global Control register */ |
1610 |
#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ |
1611 |
#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ |
1612 |
#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ |
1613 |
#define SAICR 0x18 /* Serial Audio Interrupt Clear register */ |
1614 |
#define SADIV 0x60 /* Serial Audio Clock Divider register */ |
1615 |
#define SADR 0x80 /* Serial Audio Data register */ |
1616 |
|
1617 |
static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) |
1618 |
{ |
1619 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1620 |
|
1621 |
switch (addr) {
|
1622 |
case SACR0:
|
1623 |
return s->control[0]; |
1624 |
case SACR1:
|
1625 |
return s->control[1]; |
1626 |
case SASR0:
|
1627 |
return s->status;
|
1628 |
case SAIMR:
|
1629 |
return s->mask;
|
1630 |
case SAICR:
|
1631 |
return 0; |
1632 |
case SADIV:
|
1633 |
return s->clk;
|
1634 |
case SADR:
|
1635 |
if (s->rx_len > 0) { |
1636 |
s->rx_len --; |
1637 |
pxa2xx_i2s_update(s); |
1638 |
return s->codec_in(s->opaque);
|
1639 |
} |
1640 |
return 0; |
1641 |
default:
|
1642 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1643 |
break;
|
1644 |
} |
1645 |
return 0; |
1646 |
} |
1647 |
|
1648 |
static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr, |
1649 |
uint32_t value) |
1650 |
{ |
1651 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1652 |
uint32_t *sample; |
1653 |
|
1654 |
switch (addr) {
|
1655 |
case SACR0:
|
1656 |
if (value & (1 << 3)) /* RST */ |
1657 |
pxa2xx_i2s_reset(s); |
1658 |
s->control[0] = value & 0xff3d; |
1659 |
if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ |
1660 |
for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) |
1661 |
s->codec_out(s->opaque, *sample); |
1662 |
s->status &= ~(1 << 7); /* I2SOFF */ |
1663 |
} |
1664 |
if (value & (1 << 4)) /* EFWR */ |
1665 |
printf("%s: Attempt to use special function\n", __FUNCTION__);
|
1666 |
s->enable = (value & 9) == 1; /* ENB && !RST*/ |
1667 |
pxa2xx_i2s_update(s); |
1668 |
break;
|
1669 |
case SACR1:
|
1670 |
s->control[1] = value & 0x0039; |
1671 |
if (value & (1 << 5)) /* ENLBF */ |
1672 |
printf("%s: Attempt to use loopback function\n", __FUNCTION__);
|
1673 |
if (value & (1 << 4)) /* DPRL */ |
1674 |
s->fifo_len = 0;
|
1675 |
pxa2xx_i2s_update(s); |
1676 |
break;
|
1677 |
case SAIMR:
|
1678 |
s->mask = value & 0x0078;
|
1679 |
pxa2xx_i2s_update(s); |
1680 |
break;
|
1681 |
case SAICR:
|
1682 |
s->status &= ~(value & (3 << 5)); |
1683 |
pxa2xx_i2s_update(s); |
1684 |
break;
|
1685 |
case SADIV:
|
1686 |
s->clk = value & 0x007f;
|
1687 |
break;
|
1688 |
case SADR:
|
1689 |
if (s->tx_len && s->enable) {
|
1690 |
s->tx_len --; |
1691 |
pxa2xx_i2s_update(s); |
1692 |
s->codec_out(s->opaque, value); |
1693 |
} else if (s->fifo_len < 16) { |
1694 |
s->fifo[s->fifo_len ++] = value; |
1695 |
pxa2xx_i2s_update(s); |
1696 |
} |
1697 |
break;
|
1698 |
default:
|
1699 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1700 |
} |
1701 |
} |
1702 |
|
1703 |
static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = { |
1704 |
pxa2xx_i2s_read, |
1705 |
pxa2xx_i2s_read, |
1706 |
pxa2xx_i2s_read, |
1707 |
}; |
1708 |
|
1709 |
static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = { |
1710 |
pxa2xx_i2s_write, |
1711 |
pxa2xx_i2s_write, |
1712 |
pxa2xx_i2s_write, |
1713 |
}; |
1714 |
|
1715 |
static void pxa2xx_i2s_save(QEMUFile *f, void *opaque) |
1716 |
{ |
1717 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1718 |
|
1719 |
qemu_put_be32s(f, &s->control[0]);
|
1720 |
qemu_put_be32s(f, &s->control[1]);
|
1721 |
qemu_put_be32s(f, &s->status); |
1722 |
qemu_put_be32s(f, &s->mask); |
1723 |
qemu_put_be32s(f, &s->clk); |
1724 |
|
1725 |
qemu_put_be32(f, s->enable); |
1726 |
qemu_put_be32(f, s->rx_len); |
1727 |
qemu_put_be32(f, s->tx_len); |
1728 |
qemu_put_be32(f, s->fifo_len); |
1729 |
} |
1730 |
|
1731 |
static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id) |
1732 |
{ |
1733 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1734 |
|
1735 |
qemu_get_be32s(f, &s->control[0]);
|
1736 |
qemu_get_be32s(f, &s->control[1]);
|
1737 |
qemu_get_be32s(f, &s->status); |
1738 |
qemu_get_be32s(f, &s->mask); |
1739 |
qemu_get_be32s(f, &s->clk); |
1740 |
|
1741 |
s->enable = qemu_get_be32(f); |
1742 |
s->rx_len = qemu_get_be32(f); |
1743 |
s->tx_len = qemu_get_be32(f); |
1744 |
s->fifo_len = qemu_get_be32(f); |
1745 |
|
1746 |
return 0; |
1747 |
} |
1748 |
|
1749 |
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) |
1750 |
{ |
1751 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1752 |
uint32_t *sample; |
1753 |
|
1754 |
/* Signal FIFO errors */
|
1755 |
if (s->enable && s->tx_len)
|
1756 |
s->status |= 1 << 5; /* TUR */ |
1757 |
if (s->enable && s->rx_len)
|
1758 |
s->status |= 1 << 6; /* ROR */ |
1759 |
|
1760 |
/* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
|
1761 |
* handle the cases where it makes a difference. */
|
1762 |
s->tx_len = tx - s->fifo_len; |
1763 |
s->rx_len = rx; |
1764 |
/* Note that is s->codec_out wasn't set, we wouldn't get called. */
|
1765 |
if (s->enable)
|
1766 |
for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
|
1767 |
s->codec_out(s->opaque, *sample); |
1768 |
pxa2xx_i2s_update(s); |
1769 |
} |
1770 |
|
1771 |
static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
|
1772 |
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) |
1773 |
{ |
1774 |
int iomemtype;
|
1775 |
PXA2xxI2SState *s = (PXA2xxI2SState *) |
1776 |
qemu_mallocz(sizeof(PXA2xxI2SState));
|
1777 |
|
1778 |
s->irq = irq; |
1779 |
s->rx_dma = rx_dma; |
1780 |
s->tx_dma = tx_dma; |
1781 |
s->data_req = pxa2xx_i2s_data_req; |
1782 |
|
1783 |
pxa2xx_i2s_reset(s); |
1784 |
|
1785 |
iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn, |
1786 |
pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN); |
1787 |
cpu_register_physical_memory(base, 0x100000, iomemtype);
|
1788 |
|
1789 |
register_savevm(NULL, "pxa2xx_i2s", base, 0, |
1790 |
pxa2xx_i2s_save, pxa2xx_i2s_load, s); |
1791 |
|
1792 |
return s;
|
1793 |
} |
1794 |
|
1795 |
/* PXA Fast Infra-red Communications Port */
|
1796 |
struct PXA2xxFIrState {
|
1797 |
qemu_irq irq; |
1798 |
qemu_irq rx_dma; |
1799 |
qemu_irq tx_dma; |
1800 |
int enable;
|
1801 |
CharDriverState *chr; |
1802 |
|
1803 |
uint8_t control[3];
|
1804 |
uint8_t status[2];
|
1805 |
|
1806 |
int rx_len;
|
1807 |
int rx_start;
|
1808 |
uint8_t rx_fifo[64];
|
1809 |
}; |
1810 |
|
1811 |
static void pxa2xx_fir_reset(PXA2xxFIrState *s) |
1812 |
{ |
1813 |
s->control[0] = 0x00; |
1814 |
s->control[1] = 0x00; |
1815 |
s->control[2] = 0x00; |
1816 |
s->status[0] = 0x00; |
1817 |
s->status[1] = 0x00; |
1818 |
s->enable = 0;
|
1819 |
} |
1820 |
|
1821 |
static inline void pxa2xx_fir_update(PXA2xxFIrState *s) |
1822 |
{ |
1823 |
static const int tresh[4] = { 8, 16, 32, 0 }; |
1824 |
int intr = 0; |
1825 |
if ((s->control[0] & (1 << 4)) && /* RXE */ |
1826 |
s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ |
1827 |
s->status[0] |= 1 << 4; /* RFS */ |
1828 |
else
|
1829 |
s->status[0] &= ~(1 << 4); /* RFS */ |
1830 |
if (s->control[0] & (1 << 3)) /* TXE */ |
1831 |
s->status[0] |= 1 << 3; /* TFS */ |
1832 |
else
|
1833 |
s->status[0] &= ~(1 << 3); /* TFS */ |
1834 |
if (s->rx_len)
|
1835 |
s->status[1] |= 1 << 2; /* RNE */ |
1836 |
else
|
1837 |
s->status[1] &= ~(1 << 2); /* RNE */ |
1838 |
if (s->control[0] & (1 << 4)) /* RXE */ |
1839 |
s->status[1] |= 1 << 0; /* RSY */ |
1840 |
else
|
1841 |
s->status[1] &= ~(1 << 0); /* RSY */ |
1842 |
|
1843 |
intr |= (s->control[0] & (1 << 5)) && /* RIE */ |
1844 |
(s->status[0] & (1 << 4)); /* RFS */ |
1845 |
intr |= (s->control[0] & (1 << 6)) && /* TIE */ |
1846 |
(s->status[0] & (1 << 3)); /* TFS */ |
1847 |
intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ |
1848 |
(s->status[0] & (1 << 6)); /* EOC */ |
1849 |
intr |= (s->control[0] & (1 << 2)) && /* TUS */ |
1850 |
(s->status[0] & (1 << 1)); /* TUR */ |
1851 |
intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ |
1852 |
|
1853 |
qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); |
1854 |
qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); |
1855 |
|
1856 |
qemu_set_irq(s->irq, intr && s->enable); |
1857 |
} |
1858 |
|
1859 |
#define ICCR0 0x00 /* FICP Control register 0 */ |
1860 |
#define ICCR1 0x04 /* FICP Control register 1 */ |
1861 |
#define ICCR2 0x08 /* FICP Control register 2 */ |
1862 |
#define ICDR 0x0c /* FICP Data register */ |
1863 |
#define ICSR0 0x14 /* FICP Status register 0 */ |
1864 |
#define ICSR1 0x18 /* FICP Status register 1 */ |
1865 |
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ |
1866 |
|
1867 |
static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) |
1868 |
{ |
1869 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1870 |
uint8_t ret; |
1871 |
|
1872 |
switch (addr) {
|
1873 |
case ICCR0:
|
1874 |
return s->control[0]; |
1875 |
case ICCR1:
|
1876 |
return s->control[1]; |
1877 |
case ICCR2:
|
1878 |
return s->control[2]; |
1879 |
case ICDR:
|
1880 |
s->status[0] &= ~0x01; |
1881 |
s->status[1] &= ~0x72; |
1882 |
if (s->rx_len) {
|
1883 |
s->rx_len --; |
1884 |
ret = s->rx_fifo[s->rx_start ++]; |
1885 |
s->rx_start &= 63;
|
1886 |
pxa2xx_fir_update(s); |
1887 |
return ret;
|
1888 |
} |
1889 |
printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
|
1890 |
break;
|
1891 |
case ICSR0:
|
1892 |
return s->status[0]; |
1893 |
case ICSR1:
|
1894 |
return s->status[1] | (1 << 3); /* TNF */ |
1895 |
case ICFOR:
|
1896 |
return s->rx_len;
|
1897 |
default:
|
1898 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1899 |
break;
|
1900 |
} |
1901 |
return 0; |
1902 |
} |
1903 |
|
1904 |
static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr, |
1905 |
uint32_t value) |
1906 |
{ |
1907 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1908 |
uint8_t ch; |
1909 |
|
1910 |
switch (addr) {
|
1911 |
case ICCR0:
|
1912 |
s->control[0] = value;
|
1913 |
if (!(value & (1 << 4))) /* RXE */ |
1914 |
s->rx_len = s->rx_start = 0;
|
1915 |
if (!(value & (1 << 3))) { /* TXE */ |
1916 |
/* Nop */
|
1917 |
} |
1918 |
s->enable = value & 1; /* ITR */ |
1919 |
if (!s->enable)
|
1920 |
s->status[0] = 0; |
1921 |
pxa2xx_fir_update(s); |
1922 |
break;
|
1923 |
case ICCR1:
|
1924 |
s->control[1] = value;
|
1925 |
break;
|
1926 |
case ICCR2:
|
1927 |
s->control[2] = value & 0x3f; |
1928 |
pxa2xx_fir_update(s); |
1929 |
break;
|
1930 |
case ICDR:
|
1931 |
if (s->control[2] & (1 << 2)) /* TXP */ |
1932 |
ch = value; |
1933 |
else
|
1934 |
ch = ~value; |
1935 |
if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ |
1936 |
qemu_chr_write(s->chr, &ch, 1);
|
1937 |
break;
|
1938 |
case ICSR0:
|
1939 |
s->status[0] &= ~(value & 0x66); |
1940 |
pxa2xx_fir_update(s); |
1941 |
break;
|
1942 |
case ICFOR:
|
1943 |
break;
|
1944 |
default:
|
1945 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1946 |
} |
1947 |
} |
1948 |
|
1949 |
static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = { |
1950 |
pxa2xx_fir_read, |
1951 |
pxa2xx_fir_read, |
1952 |
pxa2xx_fir_read, |
1953 |
}; |
1954 |
|
1955 |
static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = { |
1956 |
pxa2xx_fir_write, |
1957 |
pxa2xx_fir_write, |
1958 |
pxa2xx_fir_write, |
1959 |
}; |
1960 |
|
1961 |
static int pxa2xx_fir_is_empty(void *opaque) |
1962 |
{ |
1963 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1964 |
return (s->rx_len < 64); |
1965 |
} |
1966 |
|
1967 |
static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) |
1968 |
{ |
1969 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1970 |
if (!(s->control[0] & (1 << 4))) /* RXE */ |
1971 |
return;
|
1972 |
|
1973 |
while (size --) {
|
1974 |
s->status[1] |= 1 << 4; /* EOF */ |
1975 |
if (s->rx_len >= 64) { |
1976 |
s->status[1] |= 1 << 6; /* ROR */ |
1977 |
break;
|
1978 |
} |
1979 |
|
1980 |
if (s->control[2] & (1 << 3)) /* RXP */ |
1981 |
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
|
1982 |
else
|
1983 |
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
|
1984 |
} |
1985 |
|
1986 |
pxa2xx_fir_update(s); |
1987 |
} |
1988 |
|
1989 |
static void pxa2xx_fir_event(void *opaque, int event) |
1990 |
{ |
1991 |
} |
1992 |
|
1993 |
static void pxa2xx_fir_save(QEMUFile *f, void *opaque) |
1994 |
{ |
1995 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1996 |
int i;
|
1997 |
|
1998 |
qemu_put_be32(f, s->enable); |
1999 |
|
2000 |
qemu_put_8s(f, &s->control[0]);
|
2001 |
qemu_put_8s(f, &s->control[1]);
|
2002 |
qemu_put_8s(f, &s->control[2]);
|
2003 |
qemu_put_8s(f, &s->status[0]);
|
2004 |
qemu_put_8s(f, &s->status[1]);
|
2005 |
|
2006 |
qemu_put_byte(f, s->rx_len); |
2007 |
for (i = 0; i < s->rx_len; i ++) |
2008 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
|
2009 |
} |
2010 |
|
2011 |
static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) |
2012 |
{ |
2013 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
2014 |
int i;
|
2015 |
|
2016 |
s->enable = qemu_get_be32(f); |
2017 |
|
2018 |
qemu_get_8s(f, &s->control[0]);
|
2019 |
qemu_get_8s(f, &s->control[1]);
|
2020 |
qemu_get_8s(f, &s->control[2]);
|
2021 |
qemu_get_8s(f, &s->status[0]);
|
2022 |
qemu_get_8s(f, &s->status[1]);
|
2023 |
|
2024 |
s->rx_len = qemu_get_byte(f); |
2025 |
s->rx_start = 0;
|
2026 |
for (i = 0; i < s->rx_len; i ++) |
2027 |
s->rx_fifo[i] = qemu_get_byte(f); |
2028 |
|
2029 |
return 0; |
2030 |
} |
2031 |
|
2032 |
static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
|
2033 |
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, |
2034 |
CharDriverState *chr) |
2035 |
{ |
2036 |
int iomemtype;
|
2037 |
PXA2xxFIrState *s = (PXA2xxFIrState *) |
2038 |
qemu_mallocz(sizeof(PXA2xxFIrState));
|
2039 |
|
2040 |
s->irq = irq; |
2041 |
s->rx_dma = rx_dma; |
2042 |
s->tx_dma = tx_dma; |
2043 |
s->chr = chr; |
2044 |
|
2045 |
pxa2xx_fir_reset(s); |
2046 |
|
2047 |
iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn, |
2048 |
pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN); |
2049 |
cpu_register_physical_memory(base, 0x1000, iomemtype);
|
2050 |
|
2051 |
if (chr)
|
2052 |
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, |
2053 |
pxa2xx_fir_rx, pxa2xx_fir_event, s); |
2054 |
|
2055 |
register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save, |
2056 |
pxa2xx_fir_load, s); |
2057 |
|
2058 |
return s;
|
2059 |
} |
2060 |
|
2061 |
static void pxa2xx_reset(void *opaque, int line, int level) |
2062 |
{ |
2063 |
PXA2xxState *s = (PXA2xxState *) opaque; |
2064 |
|
2065 |
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ |
2066 |
cpu_reset(s->env); |
2067 |
/* TODO: reset peripherals */
|
2068 |
} |
2069 |
} |
2070 |
|
2071 |
/* Initialise a PXA270 integrated chip (ARM based core). */
|
2072 |
PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) |
2073 |
{ |
2074 |
PXA2xxState *s; |
2075 |
int iomemtype, i;
|
2076 |
DriveInfo *dinfo; |
2077 |
s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
|
2078 |
|
2079 |
if (revision && strncmp(revision, "pxa27", 5)) { |
2080 |
fprintf(stderr, "Machine requires a PXA27x processor.\n");
|
2081 |
exit(1);
|
2082 |
} |
2083 |
if (!revision)
|
2084 |
revision = "pxa270";
|
2085 |
|
2086 |
s->env = cpu_init(revision); |
2087 |
if (!s->env) {
|
2088 |
fprintf(stderr, "Unable to find CPU definition\n");
|
2089 |
exit(1);
|
2090 |
} |
2091 |
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; |
2092 |
|
2093 |
/* SDRAM & Internal Memory Storage */
|
2094 |
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, |
2095 |
sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram", |
2096 |
sdram_size) | IO_MEM_RAM); |
2097 |
cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, |
2098 |
0x40000, qemu_ram_alloc(NULL, "pxa270.internal", |
2099 |
0x40000) | IO_MEM_RAM);
|
2100 |
|
2101 |
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
|
2102 |
|
2103 |
s->dma = pxa27x_dma_init(0x40000000,
|
2104 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); |
2105 |
|
2106 |
sysbus_create_varargs("pxa27x-timer", 0x40a00000, |
2107 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
|
2108 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
|
2109 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
|
2110 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
|
2111 |
qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), |
2112 |
NULL);
|
2113 |
|
2114 |
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121); |
2115 |
|
2116 |
dinfo = drive_get(IF_SD, 0, 0); |
2117 |
if (!dinfo) {
|
2118 |
fprintf(stderr, "qemu: missing SecureDigital device\n");
|
2119 |
exit(1);
|
2120 |
} |
2121 |
s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
|
2122 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
2123 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), |
2124 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); |
2125 |
|
2126 |
for (i = 0; pxa270_serial[i].io_base; i ++) |
2127 |
if (serial_hds[i])
|
2128 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2129 |
serial_mm_init(pxa270_serial[i].io_base, 2,
|
2130 |
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), |
2131 |
14857000 / 16, serial_hds[i], 1, 1); |
2132 |
#else
|
2133 |
serial_mm_init(pxa270_serial[i].io_base, 2,
|
2134 |
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), |
2135 |
14857000 / 16, serial_hds[i], 1, 0); |
2136 |
#endif
|
2137 |
else
|
2138 |
break;
|
2139 |
if (serial_hds[i])
|
2140 |
s->fir = pxa2xx_fir_init(0x40800000,
|
2141 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
2142 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
2143 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), |
2144 |
serial_hds[i]); |
2145 |
|
2146 |
s->lcd = pxa2xx_lcdc_init(0x44000000,
|
2147 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
2148 |
|
2149 |
s->cm_base = 0x41300000;
|
2150 |
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
2151 |
s->clkcfg = 0x00000009; /* Turbo mode active */ |
2152 |
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn, |
2153 |
pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN); |
2154 |
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
|
2155 |
register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s); |
2156 |
|
2157 |
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
|
2158 |
|
2159 |
s->mm_base = 0x48000000;
|
2160 |
s->mm_regs[MDMRS >> 2] = 0x00020002; |
2161 |
s->mm_regs[MDREFR >> 2] = 0x03ca4000; |
2162 |
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ |
2163 |
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn, |
2164 |
pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN); |
2165 |
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
|
2166 |
register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s); |
2167 |
|
2168 |
s->pm_base = 0x40f00000;
|
2169 |
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn, |
2170 |
pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN); |
2171 |
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
|
2172 |
register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s); |
2173 |
|
2174 |
for (i = 0; pxa27x_ssp[i].io_base; i ++); |
2175 |
s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
|
2176 |
for (i = 0; pxa27x_ssp[i].io_base; i ++) { |
2177 |
DeviceState *dev; |
2178 |
dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
|
2179 |
qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); |
2180 |
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
|
2181 |
} |
2182 |
|
2183 |
if (usb_enabled) {
|
2184 |
sysbus_create_simple("sysbus-ohci", 0x4c000000, |
2185 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); |
2186 |
} |
2187 |
|
2188 |
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); |
2189 |
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000); |
2190 |
|
2191 |
s->rtc_base = 0x40900000;
|
2192 |
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn, |
2193 |
pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); |
2194 |
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
|
2195 |
pxa2xx_rtc_init(s); |
2196 |
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, |
2197 |
pxa2xx_rtc_load, s); |
2198 |
|
2199 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
2200 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
|
2201 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, |
2202 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
|
2203 |
|
2204 |
s->i2s = pxa2xx_i2s_init(0x40400000,
|
2205 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
2206 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), |
2207 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); |
2208 |
|
2209 |
s->kp = pxa27x_keypad_init(0x41500000,
|
2210 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); |
2211 |
|
2212 |
/* GPIO1 resets the processor */
|
2213 |
/* The handler can be overridden by board-specific code */
|
2214 |
qdev_connect_gpio_out(s->gpio, 1, s->reset);
|
2215 |
return s;
|
2216 |
} |
2217 |
|
2218 |
/* Initialise a PXA255 integrated chip (ARM based core). */
|
2219 |
PXA2xxState *pxa255_init(unsigned int sdram_size) |
2220 |
{ |
2221 |
PXA2xxState *s; |
2222 |
int iomemtype, i;
|
2223 |
DriveInfo *dinfo; |
2224 |
|
2225 |
s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
|
2226 |
|
2227 |
s->env = cpu_init("pxa255");
|
2228 |
if (!s->env) {
|
2229 |
fprintf(stderr, "Unable to find CPU definition\n");
|
2230 |
exit(1);
|
2231 |
} |
2232 |
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; |
2233 |
|
2234 |
/* SDRAM & Internal Memory Storage */
|
2235 |
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size, |
2236 |
qemu_ram_alloc(NULL, "pxa255.sdram", |
2237 |
sdram_size) | IO_MEM_RAM); |
2238 |
cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE, |
2239 |
qemu_ram_alloc(NULL, "pxa255.internal", |
2240 |
PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM); |
2241 |
|
2242 |
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
|
2243 |
|
2244 |
s->dma = pxa255_dma_init(0x40000000,
|
2245 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); |
2246 |
|
2247 |
sysbus_create_varargs("pxa25x-timer", 0x40a00000, |
2248 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
|
2249 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
|
2250 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
|
2251 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
|
2252 |
NULL);
|
2253 |
|
2254 |
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85); |
2255 |
|
2256 |
dinfo = drive_get(IF_SD, 0, 0); |
2257 |
if (!dinfo) {
|
2258 |
fprintf(stderr, "qemu: missing SecureDigital device\n");
|
2259 |
exit(1);
|
2260 |
} |
2261 |
s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
|
2262 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
2263 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), |
2264 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); |
2265 |
|
2266 |
for (i = 0; pxa255_serial[i].io_base; i ++) |
2267 |
if (serial_hds[i]) {
|
2268 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2269 |
serial_mm_init(pxa255_serial[i].io_base, 2,
|
2270 |
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), |
2271 |
14745600 / 16, serial_hds[i], 1, 1); |
2272 |
#else
|
2273 |
serial_mm_init(pxa255_serial[i].io_base, 2,
|
2274 |
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), |
2275 |
14745600 / 16, serial_hds[i], 1, 0); |
2276 |
#endif
|
2277 |
} else {
|
2278 |
break;
|
2279 |
} |
2280 |
if (serial_hds[i])
|
2281 |
s->fir = pxa2xx_fir_init(0x40800000,
|
2282 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
2283 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
2284 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), |
2285 |
serial_hds[i]); |
2286 |
|
2287 |
s->lcd = pxa2xx_lcdc_init(0x44000000,
|
2288 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
2289 |
|
2290 |
s->cm_base = 0x41300000;
|
2291 |
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
2292 |
s->clkcfg = 0x00000009; /* Turbo mode active */ |
2293 |
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn, |
2294 |
pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN); |
2295 |
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
|
2296 |
register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s); |
2297 |
|
2298 |
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
|
2299 |
|
2300 |
s->mm_base = 0x48000000;
|
2301 |
s->mm_regs[MDMRS >> 2] = 0x00020002; |
2302 |
s->mm_regs[MDREFR >> 2] = 0x03ca4000; |
2303 |
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ |
2304 |
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn, |
2305 |
pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN); |
2306 |
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
|
2307 |
register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s); |
2308 |
|
2309 |
s->pm_base = 0x40f00000;
|
2310 |
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn, |
2311 |
pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN); |
2312 |
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
|
2313 |
register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s); |
2314 |
|
2315 |
for (i = 0; pxa255_ssp[i].io_base; i ++); |
2316 |
s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
|
2317 |
for (i = 0; pxa255_ssp[i].io_base; i ++) { |
2318 |
DeviceState *dev; |
2319 |
dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
|
2320 |
qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); |
2321 |
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
|
2322 |
} |
2323 |
|
2324 |
if (usb_enabled) {
|
2325 |
sysbus_create_simple("sysbus-ohci", 0x4c000000, |
2326 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); |
2327 |
} |
2328 |
|
2329 |
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); |
2330 |
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000); |
2331 |
|
2332 |
s->rtc_base = 0x40900000;
|
2333 |
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn, |
2334 |
pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); |
2335 |
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
|
2336 |
pxa2xx_rtc_init(s); |
2337 |
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, |
2338 |
pxa2xx_rtc_load, s); |
2339 |
|
2340 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
2341 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
|
2342 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, |
2343 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
|
2344 |
|
2345 |
s->i2s = pxa2xx_i2s_init(0x40400000,
|
2346 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
2347 |
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), |
2348 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); |
2349 |
|
2350 |
/* GPIO1 resets the processor */
|
2351 |
/* The handler can be overridden by board-specific code */
|
2352 |
qdev_connect_gpio_out(s->gpio, 1, s->reset);
|
2353 |
return s;
|
2354 |
} |
2355 |
|
2356 |
static void pxa2xx_register_devices(void) |
2357 |
{ |
2358 |
i2c_register_slave(&pxa2xx_i2c_slave_info); |
2359 |
sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init); |
2360 |
sysbus_register_withprop(&pxa2xx_i2c_info); |
2361 |
} |
2362 |
|
2363 |
device_init(pxa2xx_register_devices) |