root / target-i386 / machine.c @ 216c07c3
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| 1 |
#include "hw/hw.h" |
|---|---|
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#include "hw/boards.h" |
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#include "hw/pc.h" |
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#include "hw/isa.h" |
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#include "host-utils.h" |
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|
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#include "exec-all.h" |
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#include "kvm.h" |
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|
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static const VMStateDescription vmstate_segment = { |
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.name = "segment",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT32(selector, SegmentCache), |
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VMSTATE_UINTTL(base, SegmentCache), |
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VMSTATE_UINT32(limit, SegmentCache), |
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VMSTATE_UINT32(flags, SegmentCache), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static void cpu_put_seg(QEMUFile *f, SegmentCache *dt) |
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{
|
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vmstate_save_state(f, &vmstate_segment, dt); |
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} |
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|
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static void cpu_get_seg(QEMUFile *f, SegmentCache *dt) |
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{
|
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vmstate_load_state(f, &vmstate_segment, dt, vmstate_segment.version_id); |
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} |
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|
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static const VMStateDescription vmstate_xmm_reg = { |
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.name = "xmm_reg",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
|
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
|
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static void cpu_put_xmm_reg(QEMUFile *f, XMMReg *xmm_reg) |
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{
|
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vmstate_save_state(f, &vmstate_xmm_reg, xmm_reg); |
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} |
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|
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static void cpu_get_xmm_reg(QEMUFile *f, XMMReg *xmm_reg) |
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{
|
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vmstate_load_state(f, &vmstate_xmm_reg, xmm_reg, vmstate_xmm_reg.version_id); |
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} |
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|
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static const VMStateDescription vmstate_mtrr_var = { |
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.name = "mtrr_var",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(base, MTRRVar), |
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VMSTATE_UINT64(mask, MTRRVar), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static void cpu_put_mtrr_var(QEMUFile *f, MTRRVar *mtrr_var) |
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{
|
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vmstate_save_state(f, &vmstate_mtrr_var, mtrr_var); |
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} |
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|
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static void cpu_get_mtrr_var(QEMUFile *f, MTRRVar *mtrr_var) |
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{
|
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vmstate_load_state(f, &vmstate_mtrr_var, mtrr_var, vmstate_mtrr_var.version_id); |
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} |
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|
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static void cpu_pre_save(void *opaque) |
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{
|
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CPUState *env = opaque; |
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int i, bit;
|
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|
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cpu_synchronize_state(env); |
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|
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/* FPU */
|
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env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
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env->fptag_vmstate = 0;
|
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for(i = 0; i < 8; i++) { |
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env->fptag_vmstate |= ((!env->fptags[i]) << i); |
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} |
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|
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#ifdef USE_X86LDOUBLE
|
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env->fpregs_format_vmstate = 0;
|
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#else
|
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env->fpregs_format_vmstate = 1;
|
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#endif
|
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|
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/* There can only be one pending IRQ set in the bitmap at a time, so try
|
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to find it and save its number instead (-1 for none). */
|
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env->pending_irq_vmstate = -1;
|
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for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) { |
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if (env->interrupt_bitmap[i]) {
|
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bit = ctz64(env->interrupt_bitmap[i]); |
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env->pending_irq_vmstate = i * 64 + bit;
|
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break;
|
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} |
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} |
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} |
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|
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void cpu_save(QEMUFile *f, void *opaque) |
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{
|
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CPUState *env = opaque; |
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int i;
|
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|
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cpu_pre_save(opaque); |
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|
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for(i = 0; i < CPU_NB_REGS; i++) |
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qemu_put_betls(f, &env->regs[i]); |
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qemu_put_betls(f, &env->eip); |
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qemu_put_betls(f, &env->eflags); |
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qemu_put_be32s(f, &env->hflags); |
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|
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/* FPU */
|
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qemu_put_be16s(f, &env->fpuc); |
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qemu_put_be16s(f, &env->fpus_vmstate); |
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qemu_put_be16s(f, &env->fptag_vmstate); |
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|
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qemu_put_be16s(f, &env->fpregs_format_vmstate); |
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|
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for(i = 0; i < 8; i++) { |
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#ifdef USE_X86LDOUBLE
|
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{
|
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uint64_t mant; |
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uint16_t exp; |
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/* we save the real CPU data (in case of MMX usage only 'mant'
|
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contains the MMX register */
|
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cpu_get_fp80(&mant, &exp, env->fpregs[i].d); |
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qemu_put_be64(f, mant); |
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qemu_put_be16(f, exp); |
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} |
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#else
|
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/* if we use doubles for float emulation, we save the doubles to
|
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avoid losing information in case of MMX usage. It can give
|
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problems if the image is restored on a CPU where long
|
| 145 |
doubles are used instead. */
|
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qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
|
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#endif
|
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} |
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|
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for(i = 0; i < 6; i++) |
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cpu_put_seg(f, &env->segs[i]); |
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cpu_put_seg(f, &env->ldt); |
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cpu_put_seg(f, &env->tr); |
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cpu_put_seg(f, &env->gdt); |
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cpu_put_seg(f, &env->idt); |
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|
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qemu_put_be32s(f, &env->sysenter_cs); |
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qemu_put_betls(f, &env->sysenter_esp); |
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qemu_put_betls(f, &env->sysenter_eip); |
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|
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qemu_put_betls(f, &env->cr[0]);
|
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qemu_put_betls(f, &env->cr[2]);
|
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qemu_put_betls(f, &env->cr[3]);
|
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qemu_put_betls(f, &env->cr[4]);
|
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|
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for(i = 0; i < 8; i++) |
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qemu_put_betls(f, &env->dr[i]); |
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|
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/* MMU */
|
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qemu_put_sbe32s(f, &env->a20_mask); |
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|
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/* XMM */
|
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qemu_put_be32s(f, &env->mxcsr); |
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for(i = 0; i < CPU_NB_REGS; i++) { |
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cpu_put_xmm_reg(f, &env->xmm_regs[i]); |
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} |
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|
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#ifdef TARGET_X86_64
|
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qemu_put_be64s(f, &env->efer); |
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qemu_put_be64s(f, &env->star); |
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qemu_put_be64s(f, &env->lstar); |
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qemu_put_be64s(f, &env->cstar); |
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qemu_put_be64s(f, &env->fmask); |
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qemu_put_be64s(f, &env->kernelgsbase); |
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#endif
|
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qemu_put_be32s(f, &env->smbase); |
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|
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qemu_put_be64s(f, &env->pat); |
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qemu_put_be32s(f, &env->hflags2); |
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|
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qemu_put_be64s(f, &env->vm_hsave); |
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qemu_put_be64s(f, &env->vm_vmcb); |
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qemu_put_be64s(f, &env->tsc_offset); |
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qemu_put_be64s(f, &env->intercept); |
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qemu_put_be16s(f, &env->intercept_cr_read); |
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qemu_put_be16s(f, &env->intercept_cr_write); |
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qemu_put_be16s(f, &env->intercept_dr_read); |
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qemu_put_be16s(f, &env->intercept_dr_write); |
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qemu_put_be32s(f, &env->intercept_exceptions); |
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qemu_put_8s(f, &env->v_tpr); |
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|
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/* MTRRs */
|
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for(i = 0; i < 11; i++) |
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qemu_put_be64s(f, &env->mtrr_fixed[i]); |
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qemu_put_be64s(f, &env->mtrr_deftype); |
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for(i = 0; i < 8; i++) { |
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cpu_put_mtrr_var(f, &env->mtrr_var[i]); |
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} |
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|
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/* KVM-related states */
|
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|
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qemu_put_sbe32s(f, &env->pending_irq_vmstate); |
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qemu_put_be32s(f, &env->mp_state); |
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qemu_put_be64s(f, &env->tsc); |
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|
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/* MCE */
|
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qemu_put_be64s(f, &env->mcg_cap); |
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qemu_put_be64s(f, &env->mcg_status); |
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qemu_put_be64s(f, &env->mcg_ctl); |
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for (i = 0; i < MCE_BANKS_DEF * 4; i++) { |
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qemu_put_be64s(f, &env->mce_banks[i]); |
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} |
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qemu_put_be64s(f, &env->tsc_aux); |
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} |
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|
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#ifdef USE_X86LDOUBLE
|
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/* XXX: add that in a FPU generic layer */
|
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union x86_longdouble {
|
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uint64_t mant; |
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uint16_t exp; |
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}; |
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|
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#define MANTD1(fp) (fp & ((1LL << 52) - 1)) |
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#define EXPBIAS1 1023 |
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#define EXPD1(fp) ((fp >> 52) & 0x7FF) |
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#define SIGND1(fp) ((fp >> 32) & 0x80000000) |
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|
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static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp) |
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{
|
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int e;
|
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/* mantissa */
|
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p->mant = (MANTD1(temp) << 11) | (1LL << 63); |
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/* exponent + sign */
|
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e = EXPD1(temp) - EXPBIAS1 + 16383;
|
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e |= SIGND1(temp) >> 16;
|
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p->exp = e; |
| 247 |
} |
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#endif
|
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|
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static int cpu_pre_load(void *opaque) |
| 251 |
{
|
| 252 |
CPUState *env = opaque; |
| 253 |
|
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cpu_synchronize_state(env); |
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return 0; |
| 256 |
} |
| 257 |
|
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static int cpu_post_load(void *opaque, int version_id) |
| 259 |
{
|
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CPUState *env = opaque; |
| 261 |
int i;
|
| 262 |
|
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/* XXX: restore FPU round state */
|
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env->fpstt = (env->fpus_vmstate >> 11) & 7; |
| 265 |
env->fpus = env->fpus_vmstate & ~0x3800;
|
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env->fptag_vmstate ^= 0xff;
|
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for(i = 0; i < 8; i++) { |
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env->fptags[i] = (env->fptag_vmstate >> i) & 1;
|
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} |
| 270 |
|
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cpu_breakpoint_remove_all(env, BP_CPU); |
| 272 |
cpu_watchpoint_remove_all(env, BP_CPU); |
| 273 |
for (i = 0; i < 4; i++) |
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hw_breakpoint_insert(env, i); |
| 275 |
|
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if (version_id >= 9) { |
| 277 |
memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap)); |
| 278 |
if (env->pending_irq_vmstate >= 0) { |
| 279 |
env->interrupt_bitmap[env->pending_irq_vmstate / 64] |=
|
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(uint64_t)1 << (env->pending_irq_vmstate % 64); |
| 281 |
} |
| 282 |
} |
| 283 |
|
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return cpu_post_load(env, version_id);
|
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} |
| 286 |
|
| 287 |
int cpu_load(QEMUFile *f, void *opaque, int version_id) |
| 288 |
{
|
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CPUState *env = opaque; |
| 290 |
int i, guess_mmx;
|
| 291 |
|
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cpu_pre_load(env); |
| 293 |
|
| 294 |
if (version_id < 3 || version_id > CPU_SAVE_VERSION) |
| 295 |
return -EINVAL;
|
| 296 |
for(i = 0; i < CPU_NB_REGS; i++) |
| 297 |
qemu_get_betls(f, &env->regs[i]); |
| 298 |
qemu_get_betls(f, &env->eip); |
| 299 |
qemu_get_betls(f, &env->eflags); |
| 300 |
qemu_get_be32s(f, &env->hflags); |
| 301 |
|
| 302 |
qemu_get_be16s(f, &env->fpuc); |
| 303 |
qemu_get_be16s(f, &env->fpus_vmstate); |
| 304 |
qemu_get_be16s(f, &env->fptag_vmstate); |
| 305 |
qemu_get_be16s(f, &env->fpregs_format_vmstate); |
| 306 |
|
| 307 |
/* NOTE: we cannot always restore the FPU state if the image come
|
| 308 |
from a host with a different 'USE_X86LDOUBLE' define. We guess
|
| 309 |
if we are in an MMX state to restore correctly in that case. */
|
| 310 |
guess_mmx = ((env->fptag_vmstate == 0xff) && (env->fpus_vmstate & 0x3800) == 0); |
| 311 |
for(i = 0; i < 8; i++) { |
| 312 |
uint64_t mant; |
| 313 |
uint16_t exp; |
| 314 |
|
| 315 |
switch(env->fpregs_format_vmstate) {
|
| 316 |
case 0: |
| 317 |
mant = qemu_get_be64(f); |
| 318 |
exp = qemu_get_be16(f); |
| 319 |
#ifdef USE_X86LDOUBLE
|
| 320 |
env->fpregs[i].d = cpu_set_fp80(mant, exp); |
| 321 |
#else
|
| 322 |
/* difficult case */
|
| 323 |
if (guess_mmx)
|
| 324 |
env->fpregs[i].mmx.MMX_Q(0) = mant;
|
| 325 |
else
|
| 326 |
env->fpregs[i].d = cpu_set_fp80(mant, exp); |
| 327 |
#endif
|
| 328 |
break;
|
| 329 |
case 1: |
| 330 |
mant = qemu_get_be64(f); |
| 331 |
#ifdef USE_X86LDOUBLE
|
| 332 |
{
|
| 333 |
union x86_longdouble *p;
|
| 334 |
/* difficult case */
|
| 335 |
p = (void *)&env->fpregs[i];
|
| 336 |
if (guess_mmx) {
|
| 337 |
p->mant = mant; |
| 338 |
p->exp = 0xffff;
|
| 339 |
} else {
|
| 340 |
fp64_to_fp80(p, mant); |
| 341 |
} |
| 342 |
} |
| 343 |
#else
|
| 344 |
env->fpregs[i].mmx.MMX_Q(0) = mant;
|
| 345 |
#endif
|
| 346 |
break;
|
| 347 |
default:
|
| 348 |
return -EINVAL;
|
| 349 |
} |
| 350 |
} |
| 351 |
|
| 352 |
for(i = 0; i < 6; i++) |
| 353 |
cpu_get_seg(f, &env->segs[i]); |
| 354 |
cpu_get_seg(f, &env->ldt); |
| 355 |
cpu_get_seg(f, &env->tr); |
| 356 |
cpu_get_seg(f, &env->gdt); |
| 357 |
cpu_get_seg(f, &env->idt); |
| 358 |
|
| 359 |
qemu_get_be32s(f, &env->sysenter_cs); |
| 360 |
if (version_id >= 7) { |
| 361 |
qemu_get_betls(f, &env->sysenter_esp); |
| 362 |
qemu_get_betls(f, &env->sysenter_eip); |
| 363 |
} else {
|
| 364 |
env->sysenter_esp = qemu_get_be32(f); |
| 365 |
env->sysenter_eip = qemu_get_be32(f); |
| 366 |
} |
| 367 |
|
| 368 |
qemu_get_betls(f, &env->cr[0]);
|
| 369 |
qemu_get_betls(f, &env->cr[2]);
|
| 370 |
qemu_get_betls(f, &env->cr[3]);
|
| 371 |
qemu_get_betls(f, &env->cr[4]);
|
| 372 |
|
| 373 |
for(i = 0; i < 8; i++) |
| 374 |
qemu_get_betls(f, &env->dr[i]); |
| 375 |
|
| 376 |
qemu_get_sbe32s(f, &env->a20_mask); |
| 377 |
|
| 378 |
qemu_get_be32s(f, &env->mxcsr); |
| 379 |
for(i = 0; i < CPU_NB_REGS; i++) { |
| 380 |
cpu_get_xmm_reg(f, &env->xmm_regs[i]); |
| 381 |
} |
| 382 |
|
| 383 |
#ifdef TARGET_X86_64
|
| 384 |
qemu_get_be64s(f, &env->efer); |
| 385 |
qemu_get_be64s(f, &env->star); |
| 386 |
qemu_get_be64s(f, &env->lstar); |
| 387 |
qemu_get_be64s(f, &env->cstar); |
| 388 |
qemu_get_be64s(f, &env->fmask); |
| 389 |
qemu_get_be64s(f, &env->kernelgsbase); |
| 390 |
#endif
|
| 391 |
if (version_id >= 4) { |
| 392 |
qemu_get_be32s(f, &env->smbase); |
| 393 |
} |
| 394 |
if (version_id >= 5) { |
| 395 |
qemu_get_be64s(f, &env->pat); |
| 396 |
qemu_get_be32s(f, &env->hflags2); |
| 397 |
if (version_id < 6) |
| 398 |
qemu_get_be32s(f, &env->halted); |
| 399 |
|
| 400 |
qemu_get_be64s(f, &env->vm_hsave); |
| 401 |
qemu_get_be64s(f, &env->vm_vmcb); |
| 402 |
qemu_get_be64s(f, &env->tsc_offset); |
| 403 |
qemu_get_be64s(f, &env->intercept); |
| 404 |
qemu_get_be16s(f, &env->intercept_cr_read); |
| 405 |
qemu_get_be16s(f, &env->intercept_cr_write); |
| 406 |
qemu_get_be16s(f, &env->intercept_dr_read); |
| 407 |
qemu_get_be16s(f, &env->intercept_dr_write); |
| 408 |
qemu_get_be32s(f, &env->intercept_exceptions); |
| 409 |
qemu_get_8s(f, &env->v_tpr); |
| 410 |
} |
| 411 |
|
| 412 |
if (version_id >= 8) { |
| 413 |
/* MTRRs */
|
| 414 |
for(i = 0; i < 11; i++) |
| 415 |
qemu_get_be64s(f, &env->mtrr_fixed[i]); |
| 416 |
qemu_get_be64s(f, &env->mtrr_deftype); |
| 417 |
for(i = 0; i < 8; i++) { |
| 418 |
cpu_get_mtrr_var(f, &env->mtrr_var[i]); |
| 419 |
} |
| 420 |
} |
| 421 |
|
| 422 |
if (version_id >= 9) { |
| 423 |
qemu_get_sbe32s(f, &env->pending_irq_vmstate); |
| 424 |
qemu_get_be32s(f, &env->mp_state); |
| 425 |
qemu_get_be64s(f, &env->tsc); |
| 426 |
} |
| 427 |
|
| 428 |
if (version_id >= 10) { |
| 429 |
qemu_get_be64s(f, &env->mcg_cap); |
| 430 |
qemu_get_be64s(f, &env->mcg_status); |
| 431 |
qemu_get_be64s(f, &env->mcg_ctl); |
| 432 |
for (i = 0; i < MCE_BANKS_DEF * 4; i++) { |
| 433 |
qemu_get_be64s(f, &env->mce_banks[i]); |
| 434 |
} |
| 435 |
} |
| 436 |
|
| 437 |
if (version_id >= 11) { |
| 438 |
qemu_get_be64s(f, &env->tsc_aux); |
| 439 |
} |
| 440 |
|
| 441 |
tlb_flush(env, 1);
|
| 442 |
return 0; |
| 443 |
} |