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1
/*
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 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
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 */
20
#include <stdarg.h>
21
#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
25

    
26
#include "cpu.h"
27
#include "exec-all.h"
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#include "disas.h"
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#include "tcg-op.h"
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#include "qemu-common.h"
31

    
32
#include "helper.h"
33
#define GEN_HELPER 1
34
#include "helper.h"
35

    
36
#define CPU_SINGLE_STEP 0x1
37
#define CPU_BRANCH_STEP 0x2
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#define GDBSTUB_SINGLE_STEP 0x4
39

    
40
/* Include definitions for instructions classes and implementations flags */
41
//#define DO_SINGLE_STEP
42
//#define PPC_DEBUG_DISAS
43
//#define DO_PPC_STATISTICS
44

    
45
/*****************************************************************************/
46
/* Code translation helpers                                                  */
47

    
48
/* global register indexes */
49
static TCGv_ptr cpu_env;
50
static char cpu_reg_names[10*3 + 22*4 /* GPR */
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#if !defined(TARGET_PPC64)
52
    + 10*4 + 22*5 /* SPE GPRh */
53
#endif
54
    + 10*4 + 22*5 /* FPR */
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    + 2*(10*6 + 22*7) /* AVRh, AVRl */
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    + 8*5 /* CRF */];
57
static TCGv cpu_gpr[32];
58
#if !defined(TARGET_PPC64)
59
static TCGv cpu_gprh[32];
60
#endif
61
static TCGv_i64 cpu_fpr[32];
62
static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
63
static TCGv_i32 cpu_crf[8];
64
static TCGv cpu_nip;
65
static TCGv cpu_msr;
66
static TCGv cpu_ctr;
67
static TCGv cpu_lr;
68
static TCGv cpu_xer;
69
static TCGv cpu_reserve;
70
static TCGv_i32 cpu_fpscr;
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static TCGv_i32 cpu_access_type;
72

    
73
#include "gen-icount.h"
74

    
75
void ppc_translate_init(void)
76
{
77
    int i;
78
    char* p;
79
    static int done_init = 0;
80

    
81
    if (done_init)
82
        return;
83

    
84
    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
85

    
86
    p = cpu_reg_names;
87

    
88
    for (i = 0; i < 8; i++) {
89
        sprintf(p, "crf%d", i);
90
        cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
91
                                            offsetof(CPUState, crf[i]), p);
92
        p += 5;
93
    }
94

    
95
    for (i = 0; i < 32; i++) {
96
        sprintf(p, "r%d", i);
97
        cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
98
                                        offsetof(CPUState, gpr[i]), p);
99
        p += (i < 10) ? 3 : 4;
100
#if !defined(TARGET_PPC64)
101
        sprintf(p, "r%dH", i);
102
        cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
103
                                             offsetof(CPUState, gprh[i]), p);
104
        p += (i < 10) ? 4 : 5;
105
#endif
106

    
107
        sprintf(p, "fp%d", i);
108
        cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
109
                                            offsetof(CPUState, fpr[i]), p);
110
        p += (i < 10) ? 4 : 5;
111

    
112
        sprintf(p, "avr%dH", i);
113
#ifdef WORDS_BIGENDIAN
114
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
115
                                             offsetof(CPUState, avr[i].u64[0]), p);
116
#else
117
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
118
                                             offsetof(CPUState, avr[i].u64[1]), p);
119
#endif
120
        p += (i < 10) ? 6 : 7;
121

    
122
        sprintf(p, "avr%dL", i);
123
#ifdef WORDS_BIGENDIAN
124
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
125
                                             offsetof(CPUState, avr[i].u64[1]), p);
126
#else
127
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
128
                                             offsetof(CPUState, avr[i].u64[0]), p);
129
#endif
130
        p += (i < 10) ? 6 : 7;
131
    }
132

    
133
    cpu_nip = tcg_global_mem_new(TCG_AREG0,
134
                                 offsetof(CPUState, nip), "nip");
135

    
136
    cpu_msr = tcg_global_mem_new(TCG_AREG0,
137
                                 offsetof(CPUState, msr), "msr");
138

    
139
    cpu_ctr = tcg_global_mem_new(TCG_AREG0,
140
                                 offsetof(CPUState, ctr), "ctr");
141

    
142
    cpu_lr = tcg_global_mem_new(TCG_AREG0,
143
                                offsetof(CPUState, lr), "lr");
144

    
145
    cpu_xer = tcg_global_mem_new(TCG_AREG0,
146
                                 offsetof(CPUState, xer), "xer");
147

    
148
    cpu_reserve = tcg_global_mem_new(TCG_AREG0,
149
                                     offsetof(CPUState, reserve), "reserve");
150

    
151
    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
152
                                       offsetof(CPUState, fpscr), "fpscr");
153

    
154
    cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
155
                                             offsetof(CPUState, access_type), "access_type");
156

    
157
    /* register helpers */
158
#define GEN_HELPER 2
159
#include "helper.h"
160

    
161
    done_init = 1;
162
}
163

    
164
/* internal defines */
165
typedef struct DisasContext {
166
    struct TranslationBlock *tb;
167
    target_ulong nip;
168
    uint32_t opcode;
169
    uint32_t exception;
170
    /* Routine used to access memory */
171
    int mem_idx;
172
    int access_type;
173
    /* Translation flags */
174
    int le_mode;
175
#if defined(TARGET_PPC64)
176
    int sf_mode;
177
#endif
178
    int fpu_enabled;
179
    int altivec_enabled;
180
    int spe_enabled;
181
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
182
    int singlestep_enabled;
183
} DisasContext;
184

    
185
struct opc_handler_t {
186
    /* invalid bits */
187
    uint32_t inval;
188
    /* instruction type */
189
    uint64_t type;
190
    /* handler */
191
    void (*handler)(DisasContext *ctx);
192
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
193
    const char *oname;
194
#endif
195
#if defined(DO_PPC_STATISTICS)
196
    uint64_t count;
197
#endif
198
};
199

    
200
static always_inline void gen_reset_fpstatus (void)
201
{
202
#ifdef CONFIG_SOFTFLOAT
203
    gen_helper_reset_fpstatus();
204
#endif
205
}
206

    
207
static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
208
{
209
    TCGv_i32 t0 = tcg_temp_new_i32();
210

    
211
    if (set_fprf != 0) {
212
        /* This case might be optimized later */
213
        tcg_gen_movi_i32(t0, 1);
214
        gen_helper_compute_fprf(t0, arg, t0);
215
        if (unlikely(set_rc)) {
216
            tcg_gen_mov_i32(cpu_crf[1], t0);
217
        }
218
        gen_helper_float_check_status();
219
    } else if (unlikely(set_rc)) {
220
        /* We always need to compute fpcc */
221
        tcg_gen_movi_i32(t0, 0);
222
        gen_helper_compute_fprf(t0, arg, t0);
223
        tcg_gen_mov_i32(cpu_crf[1], t0);
224
    }
225

    
226
    tcg_temp_free_i32(t0);
227
}
228

    
229
static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
230
{
231
    if (ctx->access_type != access_type) {
232
        tcg_gen_movi_i32(cpu_access_type, access_type);
233
        ctx->access_type = access_type;
234
    }
235
}
236

    
237
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
238
{
239
#if defined(TARGET_PPC64)
240
    if (ctx->sf_mode)
241
        tcg_gen_movi_tl(cpu_nip, nip);
242
    else
243
#endif
244
        tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
245
}
246

    
247
static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
248
{
249
    TCGv_i32 t0, t1;
250
    if (ctx->exception == POWERPC_EXCP_NONE) {
251
        gen_update_nip(ctx, ctx->nip);
252
    }
253
    t0 = tcg_const_i32(excp);
254
    t1 = tcg_const_i32(error);
255
    gen_helper_raise_exception_err(t0, t1);
256
    tcg_temp_free_i32(t0);
257
    tcg_temp_free_i32(t1);
258
    ctx->exception = (excp);
259
}
260

    
261
static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
262
{
263
    TCGv_i32 t0;
264
    if (ctx->exception == POWERPC_EXCP_NONE) {
265
        gen_update_nip(ctx, ctx->nip);
266
    }
267
    t0 = tcg_const_i32(excp);
268
    gen_helper_raise_exception(t0);
269
    tcg_temp_free_i32(t0);
270
    ctx->exception = (excp);
271
}
272

    
273
static always_inline void gen_debug_exception (DisasContext *ctx)
274
{
275
    TCGv_i32 t0;
276
    gen_update_nip(ctx, ctx->nip);
277
    t0 = tcg_const_i32(EXCP_DEBUG);
278
    gen_helper_raise_exception(t0);
279
    tcg_temp_free_i32(t0);
280
}
281

    
282
static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
283
{
284
    gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
285
}
286

    
287
/* Stop translation */
288
static always_inline void gen_stop_exception (DisasContext *ctx)
289
{
290
    gen_update_nip(ctx, ctx->nip);
291
    ctx->exception = POWERPC_EXCP_STOP;
292
}
293

    
294
/* No need to update nip here, as execution flow will change */
295
static always_inline void gen_sync_exception (DisasContext *ctx)
296
{
297
    ctx->exception = POWERPC_EXCP_SYNC;
298
}
299

    
300
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
301
static void gen_##name (DisasContext *ctx);                                   \
302
GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
303
static void gen_##name (DisasContext *ctx)
304

    
305
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
306
static void gen_##name (DisasContext *ctx);                                   \
307
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \
308
static void gen_##name (DisasContext *ctx)
309

    
310
typedef struct opcode_t {
311
    unsigned char opc1, opc2, opc3;
312
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
313
    unsigned char pad[5];
314
#else
315
    unsigned char pad[1];
316
#endif
317
    opc_handler_t handler;
318
    const char *oname;
319
} opcode_t;
320

    
321
/*****************************************************************************/
322
/***                           Instruction decoding                        ***/
323
#define EXTRACT_HELPER(name, shift, nb)                                       \
324
static always_inline uint32_t name (uint32_t opcode)                          \
325
{                                                                             \
326
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
327
}
328

    
329
#define EXTRACT_SHELPER(name, shift, nb)                                      \
330
static always_inline int32_t name (uint32_t opcode)                           \
331
{                                                                             \
332
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
333
}
334

    
335
/* Opcode part 1 */
336
EXTRACT_HELPER(opc1, 26, 6);
337
/* Opcode part 2 */
338
EXTRACT_HELPER(opc2, 1, 5);
339
/* Opcode part 3 */
340
EXTRACT_HELPER(opc3, 6, 5);
341
/* Update Cr0 flags */
342
EXTRACT_HELPER(Rc, 0, 1);
343
/* Destination */
344
EXTRACT_HELPER(rD, 21, 5);
345
/* Source */
346
EXTRACT_HELPER(rS, 21, 5);
347
/* First operand */
348
EXTRACT_HELPER(rA, 16, 5);
349
/* Second operand */
350
EXTRACT_HELPER(rB, 11, 5);
351
/* Third operand */
352
EXTRACT_HELPER(rC, 6, 5);
353
/***                               Get CRn                                 ***/
354
EXTRACT_HELPER(crfD, 23, 3);
355
EXTRACT_HELPER(crfS, 18, 3);
356
EXTRACT_HELPER(crbD, 21, 5);
357
EXTRACT_HELPER(crbA, 16, 5);
358
EXTRACT_HELPER(crbB, 11, 5);
359
/* SPR / TBL */
360
EXTRACT_HELPER(_SPR, 11, 10);
361
static always_inline uint32_t SPR (uint32_t opcode)
362
{
363
    uint32_t sprn = _SPR(opcode);
364

    
365
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
366
}
367
/***                              Get constants                            ***/
368
EXTRACT_HELPER(IMM, 12, 8);
369
/* 16 bits signed immediate value */
370
EXTRACT_SHELPER(SIMM, 0, 16);
371
/* 16 bits unsigned immediate value */
372
EXTRACT_HELPER(UIMM, 0, 16);
373
/* 5 bits signed immediate value */
374
EXTRACT_HELPER(SIMM5, 16, 5);
375
/* Bit count */
376
EXTRACT_HELPER(NB, 11, 5);
377
/* Shift count */
378
EXTRACT_HELPER(SH, 11, 5);
379
/* Vector shift count */
380
EXTRACT_HELPER(VSH, 6, 4);
381
/* Mask start */
382
EXTRACT_HELPER(MB, 6, 5);
383
/* Mask end */
384
EXTRACT_HELPER(ME, 1, 5);
385
/* Trap operand */
386
EXTRACT_HELPER(TO, 21, 5);
387

    
388
EXTRACT_HELPER(CRM, 12, 8);
389
EXTRACT_HELPER(FM, 17, 8);
390
EXTRACT_HELPER(SR, 16, 4);
391
EXTRACT_HELPER(FPIMM, 12, 4);
392

    
393
/***                            Jump target decoding                       ***/
394
/* Displacement */
395
EXTRACT_SHELPER(d, 0, 16);
396
/* Immediate address */
397
static always_inline target_ulong LI (uint32_t opcode)
398
{
399
    return (opcode >> 0) & 0x03FFFFFC;
400
}
401

    
402
static always_inline uint32_t BD (uint32_t opcode)
403
{
404
    return (opcode >> 0) & 0xFFFC;
405
}
406

    
407
EXTRACT_HELPER(BO, 21, 5);
408
EXTRACT_HELPER(BI, 16, 5);
409
/* Absolute/relative address */
410
EXTRACT_HELPER(AA, 1, 1);
411
/* Link */
412
EXTRACT_HELPER(LK, 0, 1);
413

    
414
/* Create a mask between <start> and <end> bits */
415
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
416
{
417
    target_ulong ret;
418

    
419
#if defined(TARGET_PPC64)
420
    if (likely(start == 0)) {
421
        ret = UINT64_MAX << (63 - end);
422
    } else if (likely(end == 63)) {
423
        ret = UINT64_MAX >> start;
424
    }
425
#else
426
    if (likely(start == 0)) {
427
        ret = UINT32_MAX << (31  - end);
428
    } else if (likely(end == 31)) {
429
        ret = UINT32_MAX >> start;
430
    }
431
#endif
432
    else {
433
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
434
            (((target_ulong)(-1ULL) >> (end)) >> 1);
435
        if (unlikely(start > end))
436
            return ~ret;
437
    }
438

    
439
    return ret;
440
}
441

    
442
/*****************************************************************************/
443
/* PowerPC Instructions types definitions                                    */
444
enum {
445
    PPC_NONE           = 0x0000000000000000ULL,
446
    /* PowerPC base instructions set                                         */
447
    PPC_INSNS_BASE     = 0x0000000000000001ULL,
448
    /*   integer operations instructions                                     */
449
#define PPC_INTEGER PPC_INSNS_BASE
450
    /*   flow control instructions                                           */
451
#define PPC_FLOW    PPC_INSNS_BASE
452
    /*   virtual memory instructions                                         */
453
#define PPC_MEM     PPC_INSNS_BASE
454
    /*   ld/st with reservation instructions                                 */
455
#define PPC_RES     PPC_INSNS_BASE
456
    /*   spr/msr access instructions                                         */
457
#define PPC_MISC    PPC_INSNS_BASE
458
    /* Deprecated instruction sets                                           */
459
    /*   Original POWER instruction set                                      */
460
    PPC_POWER          = 0x0000000000000002ULL,
461
    /*   POWER2 instruction set extension                                    */
462
    PPC_POWER2         = 0x0000000000000004ULL,
463
    /*   Power RTC support                                                   */
464
    PPC_POWER_RTC      = 0x0000000000000008ULL,
465
    /*   Power-to-PowerPC bridge (601)                                       */
466
    PPC_POWER_BR       = 0x0000000000000010ULL,
467
    /* 64 bits PowerPC instruction set                                       */
468
    PPC_64B            = 0x0000000000000020ULL,
469
    /*   New 64 bits extensions (PowerPC 2.0x)                               */
470
    PPC_64BX           = 0x0000000000000040ULL,
471
    /*   64 bits hypervisor extensions                                       */
472
    PPC_64H            = 0x0000000000000080ULL,
473
    /*   New wait instruction (PowerPC 2.0x)                                 */
474
    PPC_WAIT           = 0x0000000000000100ULL,
475
    /*   Time base mftb instruction                                          */
476
    PPC_MFTB           = 0x0000000000000200ULL,
477

    
478
    /* Fixed-point unit extensions                                           */
479
    /*   PowerPC 602 specific                                                */
480
    PPC_602_SPEC       = 0x0000000000000400ULL,
481
    /*   isel instruction                                                    */
482
    PPC_ISEL           = 0x0000000000000800ULL,
483
    /*   popcntb instruction                                                 */
484
    PPC_POPCNTB        = 0x0000000000001000ULL,
485
    /*   string load / store                                                 */
486
    PPC_STRING         = 0x0000000000002000ULL,
487

    
488
    /* Floating-point unit extensions                                        */
489
    /*   Optional floating point instructions                                */
490
    PPC_FLOAT          = 0x0000000000010000ULL,
491
    /* New floating-point extensions (PowerPC 2.0x)                          */
492
    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
493
    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
494
    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
495
    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
496
    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
497
    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
498
    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
499

    
500
    /* Vector/SIMD extensions                                                */
501
    /*   Altivec support                                                     */
502
    PPC_ALTIVEC        = 0x0000000001000000ULL,
503
    /*   PowerPC 2.03 SPE extension                                          */
504
    PPC_SPE            = 0x0000000002000000ULL,
505
    /*   PowerPC 2.03 SPE floating-point extension                           */
506
    PPC_SPEFPU         = 0x0000000004000000ULL,
507

    
508
    /* Optional memory control instructions                                  */
509
    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
510
    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
511
    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
512
    /*   sync instruction                                                    */
513
    PPC_MEM_SYNC       = 0x0000000080000000ULL,
514
    /*   eieio instruction                                                   */
515
    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
516

    
517
    /* Cache control instructions                                            */
518
    PPC_CACHE          = 0x0000000200000000ULL,
519
    /*   icbi instruction                                                    */
520
    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
521
    /*   dcbz instruction with fixed cache line size                         */
522
    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
523
    /*   dcbz instruction with tunable cache line size                       */
524
    PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
525
    /*   dcba instruction                                                    */
526
    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
527
    /*   Freescale cache locking instructions                                */
528
    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
529

    
530
    /* MMU related extensions                                                */
531
    /*   external control instructions                                       */
532
    PPC_EXTERN         = 0x0000010000000000ULL,
533
    /*   segment register access instructions                                */
534
    PPC_SEGMENT        = 0x0000020000000000ULL,
535
    /*   PowerPC 6xx TLB management instructions                             */
536
    PPC_6xx_TLB        = 0x0000040000000000ULL,
537
    /* PowerPC 74xx TLB management instructions                              */
538
    PPC_74xx_TLB       = 0x0000080000000000ULL,
539
    /*   PowerPC 40x TLB management instructions                             */
540
    PPC_40x_TLB        = 0x0000100000000000ULL,
541
    /*   segment register access instructions for PowerPC 64 "bridge"        */
542
    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
543
    /*   SLB management                                                      */
544
    PPC_SLBI           = 0x0000400000000000ULL,
545

    
546
    /* Embedded PowerPC dedicated instructions                               */
547
    PPC_WRTEE          = 0x0001000000000000ULL,
548
    /* PowerPC 40x exception model                                           */
549
    PPC_40x_EXCP       = 0x0002000000000000ULL,
550
    /* PowerPC 405 Mac instructions                                          */
551
    PPC_405_MAC        = 0x0004000000000000ULL,
552
    /* PowerPC 440 specific instructions                                     */
553
    PPC_440_SPEC       = 0x0008000000000000ULL,
554
    /* BookE (embedded) PowerPC specification                                */
555
    PPC_BOOKE          = 0x0010000000000000ULL,
556
    /* mfapidi instruction                                                   */
557
    PPC_MFAPIDI        = 0x0020000000000000ULL,
558
    /* tlbiva instruction                                                    */
559
    PPC_TLBIVA         = 0x0040000000000000ULL,
560
    /* tlbivax instruction                                                   */
561
    PPC_TLBIVAX        = 0x0080000000000000ULL,
562
    /* PowerPC 4xx dedicated instructions                                    */
563
    PPC_4xx_COMMON     = 0x0100000000000000ULL,
564
    /* PowerPC 40x ibct instructions                                         */
565
    PPC_40x_ICBT       = 0x0200000000000000ULL,
566
    /* rfmci is not implemented in all BookE PowerPC                         */
567
    PPC_RFMCI          = 0x0400000000000000ULL,
568
    /* rfdi instruction                                                      */
569
    PPC_RFDI           = 0x0800000000000000ULL,
570
    /* DCR accesses                                                          */
571
    PPC_DCR            = 0x1000000000000000ULL,
572
    /* DCR extended accesse                                                  */
573
    PPC_DCRX           = 0x2000000000000000ULL,
574
    /* user-mode DCR access, implemented in PowerPC 460                      */
575
    PPC_DCRUX          = 0x4000000000000000ULL,
576
};
577

    
578
/*****************************************************************************/
579
/* PowerPC instructions table                                                */
580
#if HOST_LONG_BITS == 64
581
#define OPC_ALIGN 8
582
#else
583
#define OPC_ALIGN 4
584
#endif
585
#if defined(__APPLE__)
586
#define OPCODES_SECTION                                                       \
587
    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
588
#else
589
#define OPCODES_SECTION                                                       \
590
    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
591
#endif
592

    
593
#if defined(DO_PPC_STATISTICS)
594
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
595
OPCODES_SECTION opcode_t opc_##name = {                                       \
596
    .opc1 = op1,                                                              \
597
    .opc2 = op2,                                                              \
598
    .opc3 = op3,                                                              \
599
    .pad  = { 0, },                                                           \
600
    .handler = {                                                              \
601
        .inval   = invl,                                                      \
602
        .type = _typ,                                                         \
603
        .handler = &gen_##name,                                               \
604
        .oname = stringify(name),                                             \
605
    },                                                                        \
606
    .oname = stringify(name),                                                 \
607
}
608
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
609
OPCODES_SECTION opcode_t opc_##name = {                                       \
610
    .opc1 = op1,                                                              \
611
    .opc2 = op2,                                                              \
612
    .opc3 = op3,                                                              \
613
    .pad  = { 0, },                                                           \
614
    .handler = {                                                              \
615
        .inval   = invl,                                                      \
616
        .type = _typ,                                                         \
617
        .handler = &gen_##name,                                               \
618
        .oname = onam,                                                        \
619
    },                                                                        \
620
    .oname = onam,                                                            \
621
}
622
#else
623
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
624
OPCODES_SECTION opcode_t opc_##name = {                                       \
625
    .opc1 = op1,                                                              \
626
    .opc2 = op2,                                                              \
627
    .opc3 = op3,                                                              \
628
    .pad  = { 0, },                                                           \
629
    .handler = {                                                              \
630
        .inval   = invl,                                                      \
631
        .type = _typ,                                                         \
632
        .handler = &gen_##name,                                               \
633
    },                                                                        \
634
    .oname = stringify(name),                                                 \
635
}
636
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
637
OPCODES_SECTION opcode_t opc_##name = {                                       \
638
    .opc1 = op1,                                                              \
639
    .opc2 = op2,                                                              \
640
    .opc3 = op3,                                                              \
641
    .pad  = { 0, },                                                           \
642
    .handler = {                                                              \
643
        .inval   = invl,                                                      \
644
        .type = _typ,                                                         \
645
        .handler = &gen_##name,                                               \
646
    },                                                                        \
647
    .oname = onam,                                                            \
648
}
649
#endif
650

    
651
#define GEN_OPCODE_MARK(name)                                                 \
652
OPCODES_SECTION opcode_t opc_##name = {                                       \
653
    .opc1 = 0xFF,                                                             \
654
    .opc2 = 0xFF,                                                             \
655
    .opc3 = 0xFF,                                                             \
656
    .pad  = { 0, },                                                           \
657
    .handler = {                                                              \
658
        .inval   = 0x00000000,                                                \
659
        .type = 0x00,                                                         \
660
        .handler = NULL,                                                      \
661
    },                                                                        \
662
    .oname = stringify(name),                                                 \
663
}
664

    
665
/* SPR load/store helpers */
666
static always_inline void gen_load_spr(TCGv t, int reg)
667
{
668
    tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
669
}
670

    
671
static always_inline void gen_store_spr(int reg, TCGv t)
672
{
673
    tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
674
}
675

    
676
/* Start opcode list */
677
GEN_OPCODE_MARK(start);
678

    
679
/* Invalid instruction */
680
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
681
{
682
    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
683
}
684

    
685
static opc_handler_t invalid_handler = {
686
    .inval   = 0xFFFFFFFF,
687
    .type    = PPC_NONE,
688
    .handler = gen_invalid,
689
};
690

    
691
/***                           Integer comparison                          ***/
692

    
693
static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
694
{
695
    int l1, l2, l3;
696

    
697
    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
698
    tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
699
    tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
700

    
701
    l1 = gen_new_label();
702
    l2 = gen_new_label();
703
    l3 = gen_new_label();
704
    if (s) {
705
        tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
706
        tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
707
    } else {
708
        tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
709
        tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
710
    }
711
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
712
    tcg_gen_br(l3);
713
    gen_set_label(l1);
714
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
715
    tcg_gen_br(l3);
716
    gen_set_label(l2);
717
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
718
    gen_set_label(l3);
719
}
720

    
721
static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
722
{
723
    TCGv t0 = tcg_const_local_tl(arg1);
724
    gen_op_cmp(arg0, t0, s, crf);
725
    tcg_temp_free(t0);
726
}
727

    
728
#if defined(TARGET_PPC64)
729
static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
730
{
731
    TCGv t0, t1;
732
    t0 = tcg_temp_local_new();
733
    t1 = tcg_temp_local_new();
734
    if (s) {
735
        tcg_gen_ext32s_tl(t0, arg0);
736
        tcg_gen_ext32s_tl(t1, arg1);
737
    } else {
738
        tcg_gen_ext32u_tl(t0, arg0);
739
        tcg_gen_ext32u_tl(t1, arg1);
740
    }
741
    gen_op_cmp(t0, t1, s, crf);
742
    tcg_temp_free(t1);
743
    tcg_temp_free(t0);
744
}
745

    
746
static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
747
{
748
    TCGv t0 = tcg_const_local_tl(arg1);
749
    gen_op_cmp32(arg0, t0, s, crf);
750
    tcg_temp_free(t0);
751
}
752
#endif
753

    
754
static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
755
{
756
#if defined(TARGET_PPC64)
757
    if (!(ctx->sf_mode))
758
        gen_op_cmpi32(reg, 0, 1, 0);
759
    else
760
#endif
761
        gen_op_cmpi(reg, 0, 1, 0);
762
}
763

    
764
/* cmp */
765
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
766
{
767
#if defined(TARGET_PPC64)
768
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
769
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
770
                     1, crfD(ctx->opcode));
771
    else
772
#endif
773
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
774
                   1, crfD(ctx->opcode));
775
}
776

    
777
/* cmpi */
778
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
779
{
780
#if defined(TARGET_PPC64)
781
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
782
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
783
                      1, crfD(ctx->opcode));
784
    else
785
#endif
786
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
787
                    1, crfD(ctx->opcode));
788
}
789

    
790
/* cmpl */
791
GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
792
{
793
#if defined(TARGET_PPC64)
794
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
795
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
796
                     0, crfD(ctx->opcode));
797
    else
798
#endif
799
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
800
                   0, crfD(ctx->opcode));
801
}
802

    
803
/* cmpli */
804
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
805
{
806
#if defined(TARGET_PPC64)
807
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
808
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
809
                      0, crfD(ctx->opcode));
810
    else
811
#endif
812
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
813
                    0, crfD(ctx->opcode));
814
}
815

    
816
/* isel (PowerPC 2.03 specification) */
817
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
818
{
819
    int l1, l2;
820
    uint32_t bi = rC(ctx->opcode);
821
    uint32_t mask;
822
    TCGv_i32 t0;
823

    
824
    l1 = gen_new_label();
825
    l2 = gen_new_label();
826

    
827
    mask = 1 << (3 - (bi & 0x03));
828
    t0 = tcg_temp_new_i32();
829
    tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
830
    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
831
    if (rA(ctx->opcode) == 0)
832
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
833
    else
834
        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
835
    tcg_gen_br(l2);
836
    gen_set_label(l1);
837
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
838
    gen_set_label(l2);
839
    tcg_temp_free_i32(t0);
840
}
841

    
842
/***                           Integer arithmetic                          ***/
843

    
844
static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
845
{
846
    int l1;
847
    TCGv t0;
848

    
849
    l1 = gen_new_label();
850
    /* Start with XER OV disabled, the most likely case */
851
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
852
    t0 = tcg_temp_local_new();
853
    tcg_gen_xor_tl(t0, arg0, arg1);
854
#if defined(TARGET_PPC64)
855
    if (!ctx->sf_mode)
856
        tcg_gen_ext32s_tl(t0, t0);
857
#endif
858
    if (sub)
859
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
860
    else
861
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
862
    tcg_gen_xor_tl(t0, arg1, arg2);
863
#if defined(TARGET_PPC64)
864
    if (!ctx->sf_mode)
865
        tcg_gen_ext32s_tl(t0, t0);
866
#endif
867
    if (sub)
868
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
869
    else
870
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
871
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
872
    gen_set_label(l1);
873
    tcg_temp_free(t0);
874
}
875

    
876
static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
877
{
878
    int l1 = gen_new_label();
879

    
880
#if defined(TARGET_PPC64)
881
    if (!(ctx->sf_mode)) {
882
        TCGv t0, t1;
883
        t0 = tcg_temp_new();
884
        t1 = tcg_temp_new();
885

    
886
        tcg_gen_ext32u_tl(t0, arg1);
887
        tcg_gen_ext32u_tl(t1, arg2);
888
        if (sub) {
889
            tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
890
        } else {
891
            tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
892
        }
893
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
894
        gen_set_label(l1);
895
        tcg_temp_free(t0);
896
        tcg_temp_free(t1);
897
    } else
898
#endif
899
    {
900
        if (sub) {
901
            tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
902
        } else {
903
            tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
904
        }
905
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
906
        gen_set_label(l1);
907
    }
908
}
909

    
910
/* Common add function */
911
static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
912
                                           int add_ca, int compute_ca, int compute_ov)
913
{
914
    TCGv t0, t1;
915

    
916
    if ((!compute_ca && !compute_ov) ||
917
        (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2)))  {
918
        t0 = ret;
919
    } else {
920
        t0 = tcg_temp_local_new();
921
    }
922

    
923
    if (add_ca) {
924
        t1 = tcg_temp_local_new();
925
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
926
        tcg_gen_shri_tl(t1, t1, XER_CA);
927
    }
928

    
929
    if (compute_ca && compute_ov) {
930
        /* Start with XER CA and OV disabled, the most likely case */
931
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
932
    } else if (compute_ca) {
933
        /* Start with XER CA disabled, the most likely case */
934
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
935
    } else if (compute_ov) {
936
        /* Start with XER OV disabled, the most likely case */
937
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
938
    }
939

    
940
    tcg_gen_add_tl(t0, arg1, arg2);
941

    
942
    if (compute_ca) {
943
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
944
    }
945
    if (add_ca) {
946
        tcg_gen_add_tl(t0, t0, t1);
947
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
948
        tcg_temp_free(t1);
949
    }
950
    if (compute_ov) {
951
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
952
    }
953

    
954
    if (unlikely(Rc(ctx->opcode) != 0))
955
        gen_set_Rc0(ctx, t0);
956

    
957
    if (!TCGV_EQUAL(t0, ret)) {
958
        tcg_gen_mov_tl(ret, t0);
959
        tcg_temp_free(t0);
960
    }
961
}
962
/* Add functions with two operands */
963
#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
964
GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER)                  \
965
{                                                                             \
966
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
967
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
968
                     add_ca, compute_ca, compute_ov);                         \
969
}
970
/* Add functions with one operand and one immediate */
971
#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
972
                                add_ca, compute_ca, compute_ov)               \
973
GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER)                  \
974
{                                                                             \
975
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
976
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
977
                     cpu_gpr[rA(ctx->opcode)], t0,                            \
978
                     add_ca, compute_ca, compute_ov);                         \
979
    tcg_temp_free(t0);                                                        \
980
}
981

    
982
/* add  add.  addo  addo. */
983
GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
984
GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
985
/* addc  addc.  addco  addco. */
986
GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
987
GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
988
/* adde  adde.  addeo  addeo. */
989
GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
990
GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
991
/* addme  addme.  addmeo  addmeo.  */
992
GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
993
GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
994
/* addze  addze.  addzeo  addzeo.*/
995
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
996
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
997
/* addi */
998
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
999
{
1000
    target_long simm = SIMM(ctx->opcode);
1001

    
1002
    if (rA(ctx->opcode) == 0) {
1003
        /* li case */
1004
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1005
    } else {
1006
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1007
    }
1008
}
1009
/* addic  addic.*/
1010
static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1011
                                        int compute_Rc0)
1012
{
1013
    target_long simm = SIMM(ctx->opcode);
1014

    
1015
    /* Start with XER CA and OV disabled, the most likely case */
1016
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1017

    
1018
    if (likely(simm != 0)) {
1019
        TCGv t0 = tcg_temp_local_new();
1020
        tcg_gen_addi_tl(t0, arg1, simm);
1021
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1022
        tcg_gen_mov_tl(ret, t0);
1023
        tcg_temp_free(t0);
1024
    } else {
1025
        tcg_gen_mov_tl(ret, arg1);
1026
    }
1027
    if (compute_Rc0) {
1028
        gen_set_Rc0(ctx, ret);
1029
    }
1030
}
1031
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1032
{
1033
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1034
}
1035
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1036
{
1037
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1038
}
1039
/* addis */
1040
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1041
{
1042
    target_long simm = SIMM(ctx->opcode);
1043

    
1044
    if (rA(ctx->opcode) == 0) {
1045
        /* lis case */
1046
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1047
    } else {
1048
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1049
    }
1050
}
1051

    
1052
static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1053
                                             int sign, int compute_ov)
1054
{
1055
    int l1 = gen_new_label();
1056
    int l2 = gen_new_label();
1057
    TCGv_i32 t0 = tcg_temp_local_new_i32();
1058
    TCGv_i32 t1 = tcg_temp_local_new_i32();
1059

    
1060
    tcg_gen_trunc_tl_i32(t0, arg1);
1061
    tcg_gen_trunc_tl_i32(t1, arg2);
1062
    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1063
    if (sign) {
1064
        int l3 = gen_new_label();
1065
        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1066
        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1067
        gen_set_label(l3);
1068
        tcg_gen_div_i32(t0, t0, t1);
1069
    } else {
1070
        tcg_gen_divu_i32(t0, t0, t1);
1071
    }
1072
    if (compute_ov) {
1073
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1074
    }
1075
    tcg_gen_br(l2);
1076
    gen_set_label(l1);
1077
    if (sign) {
1078
        tcg_gen_sari_i32(t0, t0, 31);
1079
    } else {
1080
        tcg_gen_movi_i32(t0, 0);
1081
    }
1082
    if (compute_ov) {
1083
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1084
    }
1085
    gen_set_label(l2);
1086
    tcg_gen_extu_i32_tl(ret, t0);
1087
    tcg_temp_free_i32(t0);
1088
    tcg_temp_free_i32(t1);
1089
    if (unlikely(Rc(ctx->opcode) != 0))
1090
        gen_set_Rc0(ctx, ret);
1091
}
1092
/* Div functions */
1093
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
1094
GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)                  \
1095
{                                                                             \
1096
    gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1097
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1098
                     sign, compute_ov);                                       \
1099
}
1100
/* divwu  divwu.  divwuo  divwuo.   */
1101
GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1102
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1103
/* divw  divw.  divwo  divwo.   */
1104
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1105
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1106
#if defined(TARGET_PPC64)
1107
static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1108
                                             int sign, int compute_ov)
1109
{
1110
    int l1 = gen_new_label();
1111
    int l2 = gen_new_label();
1112

    
1113
    tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1114
    if (sign) {
1115
        int l3 = gen_new_label();
1116
        tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1117
        tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1118
        gen_set_label(l3);
1119
        tcg_gen_div_i64(ret, arg1, arg2);
1120
    } else {
1121
        tcg_gen_divu_i64(ret, arg1, arg2);
1122
    }
1123
    if (compute_ov) {
1124
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1125
    }
1126
    tcg_gen_br(l2);
1127
    gen_set_label(l1);
1128
    if (sign) {
1129
        tcg_gen_sari_i64(ret, arg1, 63);
1130
    } else {
1131
        tcg_gen_movi_i64(ret, 0);
1132
    }
1133
    if (compute_ov) {
1134
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1135
    }
1136
    gen_set_label(l2);
1137
    if (unlikely(Rc(ctx->opcode) != 0))
1138
        gen_set_Rc0(ctx, ret);
1139
}
1140
#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
1141
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)                      \
1142
{                                                                             \
1143
    gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1144
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1145
                      sign, compute_ov);                                      \
1146
}
1147
/* divwu  divwu.  divwuo  divwuo.   */
1148
GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1149
GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1150
/* divw  divw.  divwo  divwo.   */
1151
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1152
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1153
#endif
1154

    
1155
/* mulhw  mulhw. */
1156
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1157
{
1158
    TCGv_i64 t0, t1;
1159

    
1160
    t0 = tcg_temp_new_i64();
1161
    t1 = tcg_temp_new_i64();
1162
#if defined(TARGET_PPC64)
1163
    tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1164
    tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1165
    tcg_gen_mul_i64(t0, t0, t1);
1166
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1167
#else
1168
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1169
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1170
    tcg_gen_mul_i64(t0, t0, t1);
1171
    tcg_gen_shri_i64(t0, t0, 32);
1172
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1173
#endif
1174
    tcg_temp_free_i64(t0);
1175
    tcg_temp_free_i64(t1);
1176
    if (unlikely(Rc(ctx->opcode) != 0))
1177
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1178
}
1179
/* mulhwu  mulhwu.  */
1180
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1181
{
1182
    TCGv_i64 t0, t1;
1183

    
1184
    t0 = tcg_temp_new_i64();
1185
    t1 = tcg_temp_new_i64();
1186
#if defined(TARGET_PPC64)
1187
    tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1188
    tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1189
    tcg_gen_mul_i64(t0, t0, t1);
1190
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1191
#else
1192
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1193
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1194
    tcg_gen_mul_i64(t0, t0, t1);
1195
    tcg_gen_shri_i64(t0, t0, 32);
1196
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1197
#endif
1198
    tcg_temp_free_i64(t0);
1199
    tcg_temp_free_i64(t1);
1200
    if (unlikely(Rc(ctx->opcode) != 0))
1201
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1202
}
1203
/* mullw  mullw. */
1204
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1205
{
1206
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1207
                   cpu_gpr[rB(ctx->opcode)]);
1208
    tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1209
    if (unlikely(Rc(ctx->opcode) != 0))
1210
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1211
}
1212
/* mullwo  mullwo. */
1213
GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1214
{
1215
    int l1;
1216
    TCGv_i64 t0, t1;
1217

    
1218
    t0 = tcg_temp_new_i64();
1219
    t1 = tcg_temp_new_i64();
1220
    l1 = gen_new_label();
1221
    /* Start with XER OV disabled, the most likely case */
1222
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1223
#if defined(TARGET_PPC64)
1224
    tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1225
    tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1226
#else
1227
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1228
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1229
#endif
1230
    tcg_gen_mul_i64(t0, t0, t1);
1231
#if defined(TARGET_PPC64)
1232
    tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1233
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1234
#else
1235
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1236
    tcg_gen_ext32s_i64(t1, t0);
1237
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1238
#endif
1239
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1240
    gen_set_label(l1);
1241
    tcg_temp_free_i64(t0);
1242
    tcg_temp_free_i64(t1);
1243
    if (unlikely(Rc(ctx->opcode) != 0))
1244
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1245
}
1246
/* mulli */
1247
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1248
{
1249
    tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1250
                    SIMM(ctx->opcode));
1251
}
1252
#if defined(TARGET_PPC64)
1253
#define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
1254
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)                      \
1255
{                                                                             \
1256
    gen_helper_##name (cpu_gpr[rD(ctx->opcode)],                              \
1257
                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);   \
1258
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1259
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1260
}
1261
/* mulhd  mulhd. */
1262
GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1263
/* mulhdu  mulhdu. */
1264
GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1265
/* mulld  mulld. */
1266
GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1267
{
1268
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1269
                   cpu_gpr[rB(ctx->opcode)]);
1270
    if (unlikely(Rc(ctx->opcode) != 0))
1271
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1272
}
1273
/* mulldo  mulldo. */
1274
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1275
#endif
1276

    
1277
/* neg neg. nego nego. */
1278
static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1279
{
1280
    int l1 = gen_new_label();
1281
    int l2 = gen_new_label();
1282
    TCGv t0 = tcg_temp_local_new();
1283
#if defined(TARGET_PPC64)
1284
    if (ctx->sf_mode) {
1285
        tcg_gen_mov_tl(t0, arg1);
1286
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1287
    } else
1288
#endif
1289
    {
1290
        tcg_gen_ext32s_tl(t0, arg1);
1291
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1292
    }
1293
    tcg_gen_neg_tl(ret, arg1);
1294
    if (ov_check) {
1295
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1296
    }
1297
    tcg_gen_br(l2);
1298
    gen_set_label(l1);
1299
    tcg_gen_mov_tl(ret, t0);
1300
    if (ov_check) {
1301
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1302
    }
1303
    gen_set_label(l2);
1304
    tcg_temp_free(t0);
1305
    if (unlikely(Rc(ctx->opcode) != 0))
1306
        gen_set_Rc0(ctx, ret);
1307
}
1308
GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1309
{
1310
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1311
}
1312
GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1313
{
1314
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1315
}
1316

    
1317
/* Common subf function */
1318
static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1319
                                            int add_ca, int compute_ca, int compute_ov)
1320
{
1321
    TCGv t0, t1;
1322

    
1323
    if ((!compute_ca && !compute_ov) ||
1324
        (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2)))  {
1325
        t0 = ret;
1326
    } else {
1327
        t0 = tcg_temp_local_new();
1328
    }
1329

    
1330
    if (add_ca) {
1331
        t1 = tcg_temp_local_new();
1332
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1333
        tcg_gen_shri_tl(t1, t1, XER_CA);
1334
    }
1335

    
1336
    if (compute_ca && compute_ov) {
1337
        /* Start with XER CA and OV disabled, the most likely case */
1338
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1339
    } else if (compute_ca) {
1340
        /* Start with XER CA disabled, the most likely case */
1341
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1342
    } else if (compute_ov) {
1343
        /* Start with XER OV disabled, the most likely case */
1344
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1345
    }
1346

    
1347
    if (add_ca) {
1348
        tcg_gen_not_tl(t0, arg1);
1349
        tcg_gen_add_tl(t0, t0, arg2);
1350
        gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1351
        tcg_gen_add_tl(t0, t0, t1);
1352
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
1353
        tcg_temp_free(t1);
1354
    } else {
1355
        tcg_gen_sub_tl(t0, arg2, arg1);
1356
        if (compute_ca) {
1357
            gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1358
        }
1359
    }
1360
    if (compute_ov) {
1361
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1362
    }
1363

    
1364
    if (unlikely(Rc(ctx->opcode) != 0))
1365
        gen_set_Rc0(ctx, t0);
1366

    
1367
    if (!TCGV_EQUAL(t0, ret)) {
1368
        tcg_gen_mov_tl(ret, t0);
1369
        tcg_temp_free(t0);
1370
    }
1371
}
1372
/* Sub functions with Two operands functions */
1373
#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
1374
GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER)                  \
1375
{                                                                             \
1376
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1377
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1378
                      add_ca, compute_ca, compute_ov);                        \
1379
}
1380
/* Sub functions with one operand and one immediate */
1381
#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
1382
                                add_ca, compute_ca, compute_ov)               \
1383
GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER)                  \
1384
{                                                                             \
1385
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
1386
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1387
                      cpu_gpr[rA(ctx->opcode)], t0,                           \
1388
                      add_ca, compute_ca, compute_ov);                        \
1389
    tcg_temp_free(t0);                                                        \
1390
}
1391
/* subf  subf.  subfo  subfo. */
1392
GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1393
GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1394
/* subfc  subfc.  subfco  subfco. */
1395
GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1396
GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1397
/* subfe  subfe.  subfeo  subfo. */
1398
GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1399
GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1400
/* subfme  subfme.  subfmeo  subfmeo.  */
1401
GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1402
GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1403
/* subfze  subfze.  subfzeo  subfzeo.*/
1404
GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1405
GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1406
/* subfic */
1407
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1408
{
1409
    /* Start with XER CA and OV disabled, the most likely case */
1410
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1411
    TCGv t0 = tcg_temp_local_new();
1412
    TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1413
    tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1414
    gen_op_arith_compute_ca(ctx, t0, t1, 1);
1415
    tcg_temp_free(t1);
1416
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1417
    tcg_temp_free(t0);
1418
}
1419

    
1420
/***                            Integer logical                            ***/
1421
#define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
1422
GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)                          \
1423
{                                                                             \
1424
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
1425
       cpu_gpr[rB(ctx->opcode)]);                                             \
1426
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1427
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1428
}
1429

    
1430
#define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
1431
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
1432
{                                                                             \
1433
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
1434
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1435
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1436
}
1437

    
1438
/* and & and. */
1439
GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1440
/* andc & andc. */
1441
GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1442
/* andi. */
1443
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1444
{
1445
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1446
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1447
}
1448
/* andis. */
1449
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1450
{
1451
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1452
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1453
}
1454
/* cntlzw */
1455
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1456
{
1457
    gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1458
    if (unlikely(Rc(ctx->opcode) != 0))
1459
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1460
}
1461
/* eqv & eqv. */
1462
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1463
/* extsb & extsb. */
1464
GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1465
/* extsh & extsh. */
1466
GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1467
/* nand & nand. */
1468
GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1469
/* nor & nor. */
1470
GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1471
/* or & or. */
1472
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1473
{
1474
    int rs, ra, rb;
1475

    
1476
    rs = rS(ctx->opcode);
1477
    ra = rA(ctx->opcode);
1478
    rb = rB(ctx->opcode);
1479
    /* Optimisation for mr. ri case */
1480
    if (rs != ra || rs != rb) {
1481
        if (rs != rb)
1482
            tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1483
        else
1484
            tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1485
        if (unlikely(Rc(ctx->opcode) != 0))
1486
            gen_set_Rc0(ctx, cpu_gpr[ra]);
1487
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1488
        gen_set_Rc0(ctx, cpu_gpr[rs]);
1489
#if defined(TARGET_PPC64)
1490
    } else {
1491
        int prio = 0;
1492

    
1493
        switch (rs) {
1494
        case 1:
1495
            /* Set process priority to low */
1496
            prio = 2;
1497
            break;
1498
        case 6:
1499
            /* Set process priority to medium-low */
1500
            prio = 3;
1501
            break;
1502
        case 2:
1503
            /* Set process priority to normal */
1504
            prio = 4;
1505
            break;
1506
#if !defined(CONFIG_USER_ONLY)
1507
        case 31:
1508
            if (ctx->mem_idx > 0) {
1509
                /* Set process priority to very low */
1510
                prio = 1;
1511
            }
1512
            break;
1513
        case 5:
1514
            if (ctx->mem_idx > 0) {
1515
                /* Set process priority to medium-hight */
1516
                prio = 5;
1517
            }
1518
            break;
1519
        case 3:
1520
            if (ctx->mem_idx > 0) {
1521
                /* Set process priority to high */
1522
                prio = 6;
1523
            }
1524
            break;
1525
        case 7:
1526
            if (ctx->mem_idx > 1) {
1527
                /* Set process priority to very high */
1528
                prio = 7;
1529
            }
1530
            break;
1531
#endif
1532
        default:
1533
            /* nop */
1534
            break;
1535
        }
1536
        if (prio) {
1537
            TCGv t0 = tcg_temp_new();
1538
            gen_load_spr(t0, SPR_PPR);
1539
            tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1540
            tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1541
            gen_store_spr(SPR_PPR, t0);
1542
            tcg_temp_free(t0);
1543
        }
1544
#endif
1545
    }
1546
}
1547
/* orc & orc. */
1548
GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1549
/* xor & xor. */
1550
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1551
{
1552
    /* Optimisation for "set to zero" case */
1553
    if (rS(ctx->opcode) != rB(ctx->opcode))
1554
        tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1555
    else
1556
        tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1557
    if (unlikely(Rc(ctx->opcode) != 0))
1558
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1559
}
1560
/* ori */
1561
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1562
{
1563
    target_ulong uimm = UIMM(ctx->opcode);
1564

    
1565
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1566
        /* NOP */
1567
        /* XXX: should handle special NOPs for POWER series */
1568
        return;
1569
    }
1570
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1571
}
1572
/* oris */
1573
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1574
{
1575
    target_ulong uimm = UIMM(ctx->opcode);
1576

    
1577
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1578
        /* NOP */
1579
        return;
1580
    }
1581
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1582
}
1583
/* xori */
1584
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1585
{
1586
    target_ulong uimm = UIMM(ctx->opcode);
1587

    
1588
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1589
        /* NOP */
1590
        return;
1591
    }
1592
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1593
}
1594
/* xoris */
1595
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1596
{
1597
    target_ulong uimm = UIMM(ctx->opcode);
1598

    
1599
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1600
        /* NOP */
1601
        return;
1602
    }
1603
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1604
}
1605
/* popcntb : PowerPC 2.03 specification */
1606
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1607
{
1608
#if defined(TARGET_PPC64)
1609
    if (ctx->sf_mode)
1610
        gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1611
    else
1612
#endif
1613
        gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1614
}
1615

    
1616
#if defined(TARGET_PPC64)
1617
/* extsw & extsw. */
1618
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1619
/* cntlzd */
1620
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1621
{
1622
    gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1623
    if (unlikely(Rc(ctx->opcode) != 0))
1624
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1625
}
1626
#endif
1627

    
1628
/***                             Integer rotate                            ***/
1629
/* rlwimi & rlwimi. */
1630
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1631
{
1632
    uint32_t mb, me, sh;
1633

    
1634
    mb = MB(ctx->opcode);
1635
    me = ME(ctx->opcode);
1636
    sh = SH(ctx->opcode);
1637
    if (likely(sh == 0 && mb == 0 && me == 31)) {
1638
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1639
    } else {
1640
        target_ulong mask;
1641
        TCGv t1;
1642
        TCGv t0 = tcg_temp_new();
1643
#if defined(TARGET_PPC64)
1644
        TCGv_i32 t2 = tcg_temp_new_i32();
1645
        tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1646
        tcg_gen_rotli_i32(t2, t2, sh);
1647
        tcg_gen_extu_i32_i64(t0, t2);
1648
        tcg_temp_free_i32(t2);
1649
#else
1650
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1651
#endif
1652
#if defined(TARGET_PPC64)
1653
        mb += 32;
1654
        me += 32;
1655
#endif
1656
        mask = MASK(mb, me);
1657
        t1 = tcg_temp_new();
1658
        tcg_gen_andi_tl(t0, t0, mask);
1659
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1660
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1661
        tcg_temp_free(t0);
1662
        tcg_temp_free(t1);
1663
    }
1664
    if (unlikely(Rc(ctx->opcode) != 0))
1665
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1666
}
1667
/* rlwinm & rlwinm. */
1668
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1669
{
1670
    uint32_t mb, me, sh;
1671

    
1672
    sh = SH(ctx->opcode);
1673
    mb = MB(ctx->opcode);
1674
    me = ME(ctx->opcode);
1675

    
1676
    if (likely(mb == 0 && me == (31 - sh))) {
1677
        if (likely(sh == 0)) {
1678
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1679
        } else {
1680
            TCGv t0 = tcg_temp_new();
1681
            tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1682
            tcg_gen_shli_tl(t0, t0, sh);
1683
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1684
            tcg_temp_free(t0);
1685
        }
1686
    } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1687
        TCGv t0 = tcg_temp_new();
1688
        tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1689
        tcg_gen_shri_tl(t0, t0, mb);
1690
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1691
        tcg_temp_free(t0);
1692
    } else {
1693
        TCGv t0 = tcg_temp_new();
1694
#if defined(TARGET_PPC64)
1695
        TCGv_i32 t1 = tcg_temp_new_i32();
1696
        tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1697
        tcg_gen_rotli_i32(t1, t1, sh);
1698
        tcg_gen_extu_i32_i64(t0, t1);
1699
        tcg_temp_free_i32(t1);
1700
#else
1701
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1702
#endif
1703
#if defined(TARGET_PPC64)
1704
        mb += 32;
1705
        me += 32;
1706
#endif
1707
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1708
        tcg_temp_free(t0);
1709
    }
1710
    if (unlikely(Rc(ctx->opcode) != 0))
1711
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1712
}
1713
/* rlwnm & rlwnm. */
1714
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1715
{
1716
    uint32_t mb, me;
1717
    TCGv t0;
1718
#if defined(TARGET_PPC64)
1719
    TCGv_i32 t1, t2;
1720
#endif
1721

    
1722
    mb = MB(ctx->opcode);
1723
    me = ME(ctx->opcode);
1724
    t0 = tcg_temp_new();
1725
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1726
#if defined(TARGET_PPC64)
1727
    t1 = tcg_temp_new_i32();
1728
    t2 = tcg_temp_new_i32();
1729
    tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1730
    tcg_gen_trunc_i64_i32(t2, t0);
1731
    tcg_gen_rotl_i32(t1, t1, t2);
1732
    tcg_gen_extu_i32_i64(t0, t1);
1733
    tcg_temp_free_i32(t1);
1734
    tcg_temp_free_i32(t2);
1735
#else
1736
    tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1737
#endif
1738
    if (unlikely(mb != 0 || me != 31)) {
1739
#if defined(TARGET_PPC64)
1740
        mb += 32;
1741
        me += 32;
1742
#endif
1743
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1744
    } else {
1745
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1746
    }
1747
    tcg_temp_free(t0);
1748
    if (unlikely(Rc(ctx->opcode) != 0))
1749
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1750
}
1751

    
1752
#if defined(TARGET_PPC64)
1753
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1754
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1755
{                                                                             \
1756
    gen_##name(ctx, 0);                                                       \
1757
}                                                                             \
1758
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1759
             PPC_64B)                                                         \
1760
{                                                                             \
1761
    gen_##name(ctx, 1);                                                       \
1762
}
1763
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1764
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1765
{                                                                             \
1766
    gen_##name(ctx, 0, 0);                                                    \
1767
}                                                                             \
1768
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
1769
             PPC_64B)                                                         \
1770
{                                                                             \
1771
    gen_##name(ctx, 0, 1);                                                    \
1772
}                                                                             \
1773
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1774
             PPC_64B)                                                         \
1775
{                                                                             \
1776
    gen_##name(ctx, 1, 0);                                                    \
1777
}                                                                             \
1778
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
1779
             PPC_64B)                                                         \
1780
{                                                                             \
1781
    gen_##name(ctx, 1, 1);                                                    \
1782
}
1783

    
1784
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1785
                                      uint32_t me, uint32_t sh)
1786
{
1787
    if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1788
        tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1789
    } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1790
        tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1791
    } else {
1792
        TCGv t0 = tcg_temp_new();
1793
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1794
        if (likely(mb == 0 && me == 63)) {
1795
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1796
        } else {
1797
            tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1798
        }
1799
        tcg_temp_free(t0);
1800
    }
1801
    if (unlikely(Rc(ctx->opcode) != 0))
1802
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1803
}
1804
/* rldicl - rldicl. */
1805
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1806
{
1807
    uint32_t sh, mb;
1808

    
1809
    sh = SH(ctx->opcode) | (shn << 5);
1810
    mb = MB(ctx->opcode) | (mbn << 5);
1811
    gen_rldinm(ctx, mb, 63, sh);
1812
}
1813
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1814
/* rldicr - rldicr. */
1815
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1816
{
1817
    uint32_t sh, me;
1818

    
1819
    sh = SH(ctx->opcode) | (shn << 5);
1820
    me = MB(ctx->opcode) | (men << 5);
1821
    gen_rldinm(ctx, 0, me, sh);
1822
}
1823
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1824
/* rldic - rldic. */
1825
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1826
{
1827
    uint32_t sh, mb;
1828

    
1829
    sh = SH(ctx->opcode) | (shn << 5);
1830
    mb = MB(ctx->opcode) | (mbn << 5);
1831
    gen_rldinm(ctx, mb, 63 - sh, sh);
1832
}
1833
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1834

    
1835
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1836
                                     uint32_t me)
1837
{
1838
    TCGv t0;
1839

    
1840
    mb = MB(ctx->opcode);
1841
    me = ME(ctx->opcode);
1842
    t0 = tcg_temp_new();
1843
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1844
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1845
    if (unlikely(mb != 0 || me != 63)) {
1846
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1847
    } else {
1848
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1849
    }
1850
    tcg_temp_free(t0);
1851
    if (unlikely(Rc(ctx->opcode) != 0))
1852
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1853
}
1854

    
1855
/* rldcl - rldcl. */
1856
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1857
{
1858
    uint32_t mb;
1859

    
1860
    mb = MB(ctx->opcode) | (mbn << 5);
1861
    gen_rldnm(ctx, mb, 63);
1862
}
1863
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1864
/* rldcr - rldcr. */
1865
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1866
{
1867
    uint32_t me;
1868

    
1869
    me = MB(ctx->opcode) | (men << 5);
1870
    gen_rldnm(ctx, 0, me);
1871
}
1872
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1873
/* rldimi - rldimi. */
1874
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1875
{
1876
    uint32_t sh, mb, me;
1877

    
1878
    sh = SH(ctx->opcode) | (shn << 5);
1879
    mb = MB(ctx->opcode) | (mbn << 5);
1880
    me = 63 - sh;
1881
    if (unlikely(sh == 0 && mb == 0)) {
1882
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1883
    } else {
1884
        TCGv t0, t1;
1885
        target_ulong mask;
1886

    
1887
        t0 = tcg_temp_new();
1888
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1889
        t1 = tcg_temp_new();
1890
        mask = MASK(mb, me);
1891
        tcg_gen_andi_tl(t0, t0, mask);
1892
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1893
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1894
        tcg_temp_free(t0);
1895
        tcg_temp_free(t1);
1896
    }
1897
    if (unlikely(Rc(ctx->opcode) != 0))
1898
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1899
}
1900
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1901
#endif
1902

    
1903
/***                             Integer shift                             ***/
1904
/* slw & slw. */
1905
GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1906
{
1907
    TCGv t0;
1908
    int l1, l2;
1909
    l1 = gen_new_label();
1910
    l2 = gen_new_label();
1911

    
1912
    t0 = tcg_temp_local_new();
1913
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1914
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1915
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1916
    tcg_gen_br(l2);
1917
    gen_set_label(l1);
1918
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1919
    tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1920
    gen_set_label(l2);
1921
    tcg_temp_free(t0);
1922
    if (unlikely(Rc(ctx->opcode) != 0))
1923
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1924
}
1925
/* sraw & sraw. */
1926
GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1927
{
1928
    gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1929
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1930
    if (unlikely(Rc(ctx->opcode) != 0))
1931
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1932
}
1933
/* srawi & srawi. */
1934
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1935
{
1936
    int sh = SH(ctx->opcode);
1937
    if (sh != 0) {
1938
        int l1, l2;
1939
        TCGv t0;
1940
        l1 = gen_new_label();
1941
        l2 = gen_new_label();
1942
        t0 = tcg_temp_local_new();
1943
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1944
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1945
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1946
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1947
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1948
        tcg_gen_br(l2);
1949
        gen_set_label(l1);
1950
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1951
        gen_set_label(l2);
1952
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1953
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1954
        tcg_temp_free(t0);
1955
    } else {
1956
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1957
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1958
    }
1959
    if (unlikely(Rc(ctx->opcode) != 0))
1960
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1961
}
1962
/* srw & srw. */
1963
GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1964
{
1965
    TCGv t0, t1;
1966
    int l1, l2;
1967
    l1 = gen_new_label();
1968
    l2 = gen_new_label();
1969

    
1970
    t0 = tcg_temp_local_new();
1971
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1972
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1973
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1974
    tcg_gen_br(l2);
1975
    gen_set_label(l1);
1976
    t1 = tcg_temp_new();
1977
    tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1978
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1979
    tcg_temp_free(t1);
1980
    gen_set_label(l2);
1981
    tcg_temp_free(t0);
1982
    if (unlikely(Rc(ctx->opcode) != 0))
1983
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1984
}
1985
#if defined(TARGET_PPC64)
1986
/* sld & sld. */
1987
GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1988
{
1989
    TCGv t0;
1990
    int l1, l2;
1991
    l1 = gen_new_label();
1992
    l2 = gen_new_label();
1993

    
1994
    t0 = tcg_temp_local_new();
1995
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1996
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
1997
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1998
    tcg_gen_br(l2);
1999
    gen_set_label(l1);
2000
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2001
    gen_set_label(l2);
2002
    tcg_temp_free(t0);
2003
    if (unlikely(Rc(ctx->opcode) != 0))
2004
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2005
}
2006
/* srad & srad. */
2007
GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2008
{
2009
    gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2010
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2011
    if (unlikely(Rc(ctx->opcode) != 0))
2012
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2013
}
2014
/* sradi & sradi. */
2015
static always_inline void gen_sradi (DisasContext *ctx, int n)
2016
{
2017
    int sh = SH(ctx->opcode) + (n << 5);
2018
    if (sh != 0) {
2019
        int l1, l2;
2020
        TCGv t0;
2021
        l1 = gen_new_label();
2022
        l2 = gen_new_label();
2023
        t0 = tcg_temp_local_new();
2024
        tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2025
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2026
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2027
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2028
        tcg_gen_br(l2);
2029
        gen_set_label(l1);
2030
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2031
        gen_set_label(l2);
2032
        tcg_temp_free(t0);
2033
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2034
    } else {
2035
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2036
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2037
    }
2038
    if (unlikely(Rc(ctx->opcode) != 0))
2039
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2040
}
2041
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2042
{
2043
    gen_sradi(ctx, 0);
2044
}
2045
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2046
{
2047
    gen_sradi(ctx, 1);
2048
}
2049
/* srd & srd. */
2050
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2051
{
2052
    TCGv t0;
2053
    int l1, l2;
2054
    l1 = gen_new_label();
2055
    l2 = gen_new_label();
2056

    
2057
    t0 = tcg_temp_local_new();
2058
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2059
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2060
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2061
    tcg_gen_br(l2);
2062
    gen_set_label(l1);
2063
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2064
    gen_set_label(l2);
2065
    tcg_temp_free(t0);
2066
    if (unlikely(Rc(ctx->opcode) != 0))
2067
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2068
}
2069
#endif
2070

    
2071
/***                       Floating-Point arithmetic                       ***/
2072
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
2073
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
2074
{                                                                             \
2075
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2076
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2077
        return;                                                               \
2078
    }                                                                         \
2079
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2080
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2081
    gen_reset_fpstatus();                                                     \
2082
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2083
                     cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);     \
2084
    if (isfloat) {                                                            \
2085
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2086
    }                                                                         \
2087
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf,                      \
2088
                     Rc(ctx->opcode) != 0);                                   \
2089
}
2090

    
2091
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
2092
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
2093
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2094

    
2095
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
2096
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
2097
{                                                                             \
2098
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2099
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2100
        return;                                                               \
2101
    }                                                                         \
2102
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2103
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2104
    gen_reset_fpstatus();                                                     \
2105
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2106
                     cpu_fpr[rB(ctx->opcode)]);                               \
2107
    if (isfloat) {                                                            \
2108
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2109
    }                                                                         \
2110
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2111
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2112
}
2113
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
2114
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2115
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2116

    
2117
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
2118
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
2119
{                                                                             \
2120
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2121
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2122
        return;                                                               \
2123
    }                                                                         \
2124
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2125
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2126
    gen_reset_fpstatus();                                                     \
2127
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2128
                       cpu_fpr[rC(ctx->opcode)]);                             \
2129
    if (isfloat) {                                                            \
2130
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2131
    }                                                                         \
2132
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2133
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2134
}
2135
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
2136
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2137
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2138

    
2139
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
2140
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
2141
{                                                                             \
2142
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2143
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2144
        return;                                                               \
2145
    }                                                                         \
2146
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2147
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2148
    gen_reset_fpstatus();                                                     \
2149
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
2150
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2151
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2152
}
2153

    
2154
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
2155
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
2156
{                                                                             \
2157
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2158
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2159
        return;                                                               \
2160
    }                                                                         \
2161
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2162
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2163
    gen_reset_fpstatus();                                                     \
2164
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
2165
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2166
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2167
}
2168

    
2169
/* fadd - fadds */
2170
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2171
/* fdiv - fdivs */
2172
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2173
/* fmul - fmuls */
2174
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2175

    
2176
/* fre */
2177
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2178

    
2179
/* fres */
2180
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2181

    
2182
/* frsqrte */
2183
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2184

    
2185
/* frsqrtes */
2186
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2187
{
2188
    if (unlikely(!ctx->fpu_enabled)) {
2189
        gen_exception(ctx, POWERPC_EXCP_FPU);
2190
        return;
2191
    }
2192
    /* NIP cannot be restored if the memory exception comes from an helper */
2193
    gen_update_nip(ctx, ctx->nip - 4);
2194
    gen_reset_fpstatus();
2195
    gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2196
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2197
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2198
}
2199

    
2200
/* fsel */
2201
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2202
/* fsub - fsubs */
2203
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2204
/* Optional: */
2205
/* fsqrt */
2206
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2207
{
2208
    if (unlikely(!ctx->fpu_enabled)) {
2209
        gen_exception(ctx, POWERPC_EXCP_FPU);
2210
        return;
2211
    }
2212
    /* NIP cannot be restored if the memory exception comes from an helper */
2213
    gen_update_nip(ctx, ctx->nip - 4);
2214
    gen_reset_fpstatus();
2215
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2216
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2217
}
2218

    
2219
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2220
{
2221
    if (unlikely(!ctx->fpu_enabled)) {
2222
        gen_exception(ctx, POWERPC_EXCP_FPU);
2223
        return;
2224
    }
2225
    /* NIP cannot be restored if the memory exception comes from an helper */
2226
    gen_update_nip(ctx, ctx->nip - 4);
2227
    gen_reset_fpstatus();
2228
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2229
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2230
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2231
}
2232

    
2233
/***                     Floating-Point multiply-and-add                   ***/
2234
/* fmadd - fmadds */
2235
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2236
/* fmsub - fmsubs */
2237
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2238
/* fnmadd - fnmadds */
2239
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2240
/* fnmsub - fnmsubs */
2241
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2242

    
2243
/***                     Floating-Point round & convert                    ***/
2244
/* fctiw */
2245
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2246
/* fctiwz */
2247
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2248
/* frsp */
2249
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2250
#if defined(TARGET_PPC64)
2251
/* fcfid */
2252
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2253
/* fctid */
2254
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2255
/* fctidz */
2256
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2257
#endif
2258

    
2259
/* frin */
2260
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2261
/* friz */
2262
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2263
/* frip */
2264
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2265
/* frim */
2266
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2267

    
2268
/***                         Floating-Point compare                        ***/
2269
/* fcmpo */
2270
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2271
{
2272
    TCGv_i32 crf;
2273
    if (unlikely(!ctx->fpu_enabled)) {
2274
        gen_exception(ctx, POWERPC_EXCP_FPU);
2275
        return;
2276
    }
2277
    /* NIP cannot be restored if the memory exception comes from an helper */
2278
    gen_update_nip(ctx, ctx->nip - 4);
2279
    gen_reset_fpstatus();
2280
    crf = tcg_const_i32(crfD(ctx->opcode));
2281
    gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2282
    tcg_temp_free_i32(crf);
2283
    gen_helper_float_check_status();
2284
}
2285

    
2286
/* fcmpu */
2287
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2288
{
2289
    TCGv_i32 crf;
2290
    if (unlikely(!ctx->fpu_enabled)) {
2291
        gen_exception(ctx, POWERPC_EXCP_FPU);
2292
        return;
2293
    }
2294
    /* NIP cannot be restored if the memory exception comes from an helper */
2295
    gen_update_nip(ctx, ctx->nip - 4);
2296
    gen_reset_fpstatus();
2297
    crf = tcg_const_i32(crfD(ctx->opcode));
2298
    gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2299
    tcg_temp_free_i32(crf);
2300
    gen_helper_float_check_status();
2301
}
2302

    
2303
/***                         Floating-point move                           ***/
2304
/* fabs */
2305
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2306
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2307

    
2308
/* fmr  - fmr. */
2309
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2310
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2311
{
2312
    if (unlikely(!ctx->fpu_enabled)) {
2313
        gen_exception(ctx, POWERPC_EXCP_FPU);
2314
        return;
2315
    }
2316
    tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2317
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2318
}
2319

    
2320
/* fnabs */
2321
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2322
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2323
/* fneg */
2324
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2325
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2326

    
2327
/***                  Floating-Point status & ctrl register                ***/
2328
/* mcrfs */
2329
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2330
{
2331
    int bfa;
2332

    
2333
    if (unlikely(!ctx->fpu_enabled)) {
2334
        gen_exception(ctx, POWERPC_EXCP_FPU);
2335
        return;
2336
    }
2337
    bfa = 4 * (7 - crfS(ctx->opcode));
2338
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2339
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2340
    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2341
}
2342

    
2343
/* mffs */
2344
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2345
{
2346
    if (unlikely(!ctx->fpu_enabled)) {
2347
        gen_exception(ctx, POWERPC_EXCP_FPU);
2348
        return;
2349
    }
2350
    gen_reset_fpstatus();
2351
    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2352
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2353
}
2354

    
2355
/* mtfsb0 */
2356
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2357
{
2358
    uint8_t crb;
2359

    
2360
    if (unlikely(!ctx->fpu_enabled)) {
2361
        gen_exception(ctx, POWERPC_EXCP_FPU);
2362
        return;
2363
    }
2364
    crb = 31 - crbD(ctx->opcode);
2365
    gen_reset_fpstatus();
2366
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2367
        TCGv_i32 t0;
2368
        /* NIP cannot be restored if the memory exception comes from an helper */
2369
        gen_update_nip(ctx, ctx->nip - 4);
2370
        t0 = tcg_const_i32(crb);
2371
        gen_helper_fpscr_clrbit(t0);
2372
        tcg_temp_free_i32(t0);
2373
    }
2374
    if (unlikely(Rc(ctx->opcode) != 0)) {
2375
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2376
    }
2377
}
2378

    
2379
/* mtfsb1 */
2380
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2381
{
2382
    uint8_t crb;
2383

    
2384
    if (unlikely(!ctx->fpu_enabled)) {
2385
        gen_exception(ctx, POWERPC_EXCP_FPU);
2386
        return;
2387
    }
2388
    crb = 31 - crbD(ctx->opcode);
2389
    gen_reset_fpstatus();
2390
    /* XXX: we pretend we can only do IEEE floating-point computations */
2391
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2392
        TCGv_i32 t0;
2393
        /* NIP cannot be restored if the memory exception comes from an helper */
2394
        gen_update_nip(ctx, ctx->nip - 4);
2395
        t0 = tcg_const_i32(crb);
2396
        gen_helper_fpscr_setbit(t0);
2397
        tcg_temp_free_i32(t0);
2398
    }
2399
    if (unlikely(Rc(ctx->opcode) != 0)) {
2400
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2401
    }
2402
    /* We can raise a differed exception */
2403
    gen_helper_float_check_status();
2404
}
2405

    
2406
/* mtfsf */
2407
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2408
{
2409
    TCGv_i32 t0;
2410

    
2411
    if (unlikely(!ctx->fpu_enabled)) {
2412
        gen_exception(ctx, POWERPC_EXCP_FPU);
2413
        return;
2414
    }
2415
    /* NIP cannot be restored if the memory exception comes from an helper */
2416
    gen_update_nip(ctx, ctx->nip - 4);
2417
    gen_reset_fpstatus();
2418
    t0 = tcg_const_i32(FM(ctx->opcode));
2419
    gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2420
    tcg_temp_free_i32(t0);
2421
    if (unlikely(Rc(ctx->opcode) != 0)) {
2422
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2423
    }
2424
    /* We can raise a differed exception */
2425
    gen_helper_float_check_status();
2426
}
2427

    
2428
/* mtfsfi */
2429
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2430
{
2431
    int bf, sh;
2432
    TCGv_i64 t0;
2433
    TCGv_i32 t1;
2434

    
2435
    if (unlikely(!ctx->fpu_enabled)) {
2436
        gen_exception(ctx, POWERPC_EXCP_FPU);
2437
        return;
2438
    }
2439
    bf = crbD(ctx->opcode) >> 2;
2440
    sh = 7 - bf;
2441
    /* NIP cannot be restored if the memory exception comes from an helper */
2442
    gen_update_nip(ctx, ctx->nip - 4);
2443
    gen_reset_fpstatus();
2444
    t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2445
    t1 = tcg_const_i32(1 << sh);
2446
    gen_helper_store_fpscr(t0, t1);
2447
    tcg_temp_free_i64(t0);
2448
    tcg_temp_free_i32(t1);
2449
    if (unlikely(Rc(ctx->opcode) != 0)) {
2450
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2451
    }
2452
    /* We can raise a differed exception */
2453
    gen_helper_float_check_status();
2454
}
2455

    
2456
/***                           Addressing modes                            ***/
2457
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2458
static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2459
{
2460
    target_long simm = SIMM(ctx->opcode);
2461

    
2462
    simm &= ~maskl;
2463
    if (rA(ctx->opcode) == 0) {
2464
#if defined(TARGET_PPC64)
2465
        if (!ctx->sf_mode) {
2466
            tcg_gen_movi_tl(EA, (uint32_t)simm);
2467
        } else
2468
#endif
2469
        tcg_gen_movi_tl(EA, simm);
2470
    } else if (likely(simm != 0)) {
2471
        tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2472
#if defined(TARGET_PPC64)
2473
        if (!ctx->sf_mode) {
2474
            tcg_gen_ext32u_tl(EA, EA);
2475
        }
2476
#endif
2477
    } else {
2478
#if defined(TARGET_PPC64)
2479
        if (!ctx->sf_mode) {
2480
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2481
        } else
2482
#endif
2483
        tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2484
    }
2485
}
2486

    
2487
static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2488
{
2489
    if (rA(ctx->opcode) == 0) {
2490
#if defined(TARGET_PPC64)
2491
        if (!ctx->sf_mode) {
2492
            tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2493
        } else
2494
#endif
2495
        tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2496
    } else {
2497
        tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2498
#if defined(TARGET_PPC64)
2499
        if (!ctx->sf_mode) {
2500
            tcg_gen_ext32u_tl(EA, EA);
2501
        }
2502
#endif
2503
    }
2504
}
2505

    
2506
static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2507
{
2508
    if (rA(ctx->opcode) == 0) {
2509
        tcg_gen_movi_tl(EA, 0);
2510
    } else {
2511
#if defined(TARGET_PPC64)
2512
        if (!ctx->sf_mode) {
2513
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2514
        } else
2515
#endif
2516
            tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2517
    }
2518
}
2519

    
2520
static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2521
{
2522
    tcg_gen_addi_tl(ret, arg1, val);
2523
#if defined(TARGET_PPC64)
2524
    if (!ctx->sf_mode) {
2525
        tcg_gen_ext32u_tl(ret, ret);
2526
    }
2527
#endif
2528
}
2529

    
2530
static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2531
{
2532
    int l1 = gen_new_label();
2533
    TCGv t0 = tcg_temp_new();
2534
    TCGv_i32 t1, t2;
2535
    /* NIP cannot be restored if the memory exception comes from an helper */
2536
    gen_update_nip(ctx, ctx->nip - 4);
2537
    tcg_gen_andi_tl(t0, EA, mask);
2538
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2539
    t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2540
    t2 = tcg_const_i32(0);
2541
    gen_helper_raise_exception_err(t1, t2);
2542
    tcg_temp_free_i32(t1);
2543
    tcg_temp_free_i32(t2);
2544
    gen_set_label(l1);
2545
    tcg_temp_free(t0);
2546
}
2547

    
2548
/***                             Integer load                              ***/
2549
static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2550
{
2551
    tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2552
}
2553

    
2554
static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2555
{
2556
    tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2557
}
2558

    
2559
static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2560
{
2561
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2562
    if (unlikely(ctx->le_mode)) {
2563
#if defined(TARGET_PPC64)
2564
        TCGv_i32 t0 = tcg_temp_new_i32();
2565
        tcg_gen_trunc_tl_i32(t0, arg1);
2566
        tcg_gen_bswap16_i32(t0, t0);
2567
        tcg_gen_extu_i32_tl(arg1, t0);
2568
        tcg_temp_free_i32(t0);
2569
#else
2570
        tcg_gen_bswap16_i32(arg1, arg1);
2571
#endif
2572
    }
2573
}
2574

    
2575
static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2576
{
2577
    if (unlikely(ctx->le_mode)) {
2578
#if defined(TARGET_PPC64)
2579
        TCGv_i32 t0;
2580
        tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2581
        t0 = tcg_temp_new_i32();
2582
        tcg_gen_trunc_tl_i32(t0, arg1);
2583
        tcg_gen_bswap16_i32(t0, t0);
2584
        tcg_gen_extu_i32_tl(arg1, t0);
2585
        tcg_gen_ext16s_tl(arg1, arg1);
2586
        tcg_temp_free_i32(t0);
2587
#else
2588
        tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2589
        tcg_gen_bswap16_i32(arg1, arg1);
2590
        tcg_gen_ext16s_i32(arg1, arg1);
2591
#endif
2592
    } else {
2593
        tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2594
    }
2595
}
2596

    
2597
static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2598
{
2599
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2600
    if (unlikely(ctx->le_mode)) {
2601
#if defined(TARGET_PPC64)
2602
        TCGv_i32 t0 = tcg_temp_new_i32();
2603
        tcg_gen_trunc_tl_i32(t0, arg1);
2604
        tcg_gen_bswap_i32(t0, t0);
2605
        tcg_gen_extu_i32_tl(arg1, t0);
2606
        tcg_temp_free_i32(t0);
2607
#else
2608
        tcg_gen_bswap_i32(arg1, arg1);
2609
#endif
2610
    }
2611
}
2612

    
2613
#if defined(TARGET_PPC64)
2614
static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2615
{
2616
    if (unlikely(ctx->mem_idx)) {
2617
        TCGv_i32 t0;
2618
        tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2619
        t0 = tcg_temp_new_i32();
2620
        tcg_gen_trunc_tl_i32(t0, arg1);
2621
        tcg_gen_bswap_i32(t0, t0);
2622
        tcg_gen_ext_i32_tl(arg1, t0);
2623
        tcg_temp_free_i32(t0);
2624
    } else
2625
        tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2626
}
2627
#endif
2628

    
2629
static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2630
{
2631
    tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2632
    if (unlikely(ctx->le_mode)) {
2633
        tcg_gen_bswap_i64(arg1, arg1);
2634
    }
2635
}
2636

    
2637
static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2638
{
2639
    tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2640
}
2641

    
2642
static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2643
{
2644
    if (unlikely(ctx->le_mode)) {
2645
#if defined(TARGET_PPC64)
2646
        TCGv_i32 t0;
2647
        TCGv t1;
2648
        t0 = tcg_temp_new_i32();
2649
        tcg_gen_trunc_tl_i32(t0, arg1);
2650
        tcg_gen_ext16u_i32(t0, t0);
2651
        tcg_gen_bswap16_i32(t0, t0);
2652
        t1 = tcg_temp_new();
2653
        tcg_gen_extu_i32_tl(t1, t0);
2654
        tcg_temp_free_i32(t0);
2655
        tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2656
        tcg_temp_free(t1);
2657
#else
2658
        TCGv t0 = tcg_temp_new();
2659
        tcg_gen_ext16u_tl(t0, arg1);
2660
        tcg_gen_bswap16_i32(t0, t0);
2661
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2662
        tcg_temp_free(t0);
2663
#endif
2664
    } else {
2665
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2666
    }
2667
}
2668

    
2669
static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2670
{
2671
    if (unlikely(ctx->le_mode)) {
2672
#if defined(TARGET_PPC64)
2673
        TCGv_i32 t0;
2674
        TCGv t1;
2675
        t0 = tcg_temp_new_i32();
2676
        tcg_gen_trunc_tl_i32(t0, arg1);
2677
        tcg_gen_bswap_i32(t0, t0);
2678
        t1 = tcg_temp_new();
2679
        tcg_gen_extu_i32_tl(t1, t0);
2680
        tcg_temp_free_i32(t0);
2681
        tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2682
        tcg_temp_free(t1);
2683
#else
2684
        TCGv t0 = tcg_temp_new_i32();
2685
        tcg_gen_bswap_i32(t0, arg1);
2686
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2687
        tcg_temp_free(t0);
2688
#endif
2689
    } else {
2690
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2691
    }
2692
}
2693

    
2694
static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2695
{
2696
    if (unlikely(ctx->le_mode)) {
2697
        TCGv_i64 t0 = tcg_temp_new_i64();
2698
        tcg_gen_bswap_i64(t0, arg1);
2699
        tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2700
        tcg_temp_free_i64(t0);
2701
    } else
2702
        tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2703
}
2704

    
2705
#define GEN_LD(name, ldop, opc, type)                                         \
2706
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
2707
{                                                                             \
2708
    TCGv EA;                                                                  \
2709
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2710
    EA = tcg_temp_new();                                                      \
2711
    gen_addr_imm_index(ctx, EA, 0);                                           \
2712
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2713
    tcg_temp_free(EA);                                                        \
2714
}
2715

    
2716
#define GEN_LDU(name, ldop, opc, type)                                        \
2717
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
2718
{                                                                             \
2719
    TCGv EA;                                                                  \
2720
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2721
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2722
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2723
        return;                                                               \
2724
    }                                                                         \
2725
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2726
    EA = tcg_temp_new();                                                      \
2727
    if (type == PPC_64B)                                                      \
2728
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2729
    else                                                                      \
2730
        gen_addr_imm_index(ctx, EA, 0);                                       \
2731
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2732
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2733
    tcg_temp_free(EA);                                                        \
2734
}
2735

    
2736
#define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
2737
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type)                     \
2738
{                                                                             \
2739
    TCGv EA;                                                                  \
2740
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2741
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2742
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2743
        return;                                                               \
2744
    }                                                                         \
2745
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2746
    EA = tcg_temp_new();                                                      \
2747
    gen_addr_reg_index(ctx, EA);                                              \
2748
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2749
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2750
    tcg_temp_free(EA);                                                        \
2751
}
2752

    
2753
#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
2754
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
2755
{                                                                             \
2756
    TCGv EA;                                                                  \
2757
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2758
    EA = tcg_temp_new();                                                      \
2759
    gen_addr_reg_index(ctx, EA);                                              \
2760
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2761
    tcg_temp_free(EA);                                                        \
2762
}
2763

    
2764
#define GEN_LDS(name, ldop, op, type)                                         \
2765
GEN_LD(name, ldop, op | 0x20, type);                                          \
2766
GEN_LDU(name, ldop, op | 0x21, type);                                         \
2767
GEN_LDUX(name, ldop, 0x17, op | 0x01, type);                                  \
2768
GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2769

    
2770
/* lbz lbzu lbzux lbzx */
2771
GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2772
/* lha lhau lhaux lhax */
2773
GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2774
/* lhz lhzu lhzux lhzx */
2775
GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2776
/* lwz lwzu lwzux lwzx */
2777
GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2778
#if defined(TARGET_PPC64)
2779
/* lwaux */
2780
GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2781
/* lwax */
2782
GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2783
/* ldux */
2784
GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2785
/* ldx */
2786
GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2787
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2788
{
2789
    TCGv EA;
2790
    if (Rc(ctx->opcode)) {
2791
        if (unlikely(rA(ctx->opcode) == 0 ||
2792
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2793
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2794
            return;
2795
        }
2796
    }
2797
    gen_set_access_type(ctx, ACCESS_INT);
2798
    EA = tcg_temp_new();
2799
    gen_addr_imm_index(ctx, EA, 0x03);
2800
    if (ctx->opcode & 0x02) {
2801
        /* lwa (lwau is undefined) */
2802
        gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2803
    } else {
2804
        /* ld - ldu */
2805
        gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2806
    }
2807
    if (Rc(ctx->opcode))
2808
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2809
    tcg_temp_free(EA);
2810
}
2811
/* lq */
2812
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2813
{
2814
#if defined(CONFIG_USER_ONLY)
2815
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2816
#else
2817
    int ra, rd;
2818
    TCGv EA;
2819

    
2820
    /* Restore CPU state */
2821
    if (unlikely(ctx->mem_idx == 0)) {
2822
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2823
        return;
2824
    }
2825
    ra = rA(ctx->opcode);
2826
    rd = rD(ctx->opcode);
2827
    if (unlikely((rd & 1) || rd == ra)) {
2828
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2829
        return;
2830
    }
2831
    if (unlikely(ctx->le_mode)) {
2832
        /* Little-endian mode is not handled */
2833
        gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2834
        return;
2835
    }
2836
    gen_set_access_type(ctx, ACCESS_INT);
2837
    EA = tcg_temp_new();
2838
    gen_addr_imm_index(ctx, EA, 0x0F);
2839
    gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2840
    gen_addr_add(ctx, EA, EA, 8);
2841
    gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2842
    tcg_temp_free(EA);
2843
#endif
2844
}
2845
#endif
2846

    
2847
/***                              Integer store                            ***/
2848
#define GEN_ST(name, stop, opc, type)                                         \
2849
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
2850
{                                                                             \
2851
    TCGv EA;                                                                  \
2852
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2853
    EA = tcg_temp_new();                                                      \
2854
    gen_addr_imm_index(ctx, EA, 0);                                           \
2855
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2856
    tcg_temp_free(EA);                                                        \
2857
}
2858

    
2859
#define GEN_STU(name, stop, opc, type)                                        \
2860
GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
2861
{                                                                             \
2862
    TCGv EA;                                                                  \
2863
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2864
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2865
        return;                                                               \
2866
    }                                                                         \
2867
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2868
    EA = tcg_temp_new();                                                      \
2869
    if (type == PPC_64B)                                                      \
2870
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2871
    else                                                                      \
2872
        gen_addr_imm_index(ctx, EA, 0);                                       \
2873
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2874
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2875
    tcg_temp_free(EA);                                                        \
2876
}
2877

    
2878
#define GEN_STUX(name, stop, opc2, opc3, type)                                \
2879
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type)                     \
2880
{                                                                             \
2881
    TCGv EA;                                                                  \
2882
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2883
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2884
        return;                                                               \
2885
    }                                                                         \
2886
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2887
    EA = tcg_temp_new();                                                      \
2888
    gen_addr_reg_index(ctx, EA);                                              \
2889
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2890
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2891
    tcg_temp_free(EA);                                                        \
2892
}
2893

    
2894
#define GEN_STX(name, stop, opc2, opc3, type)                                 \
2895
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
2896
{                                                                             \
2897
    TCGv EA;                                                                  \
2898
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2899
    EA = tcg_temp_new();                                                      \
2900
    gen_addr_reg_index(ctx, EA);                                              \
2901
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2902
    tcg_temp_free(EA);                                                        \
2903
}
2904

    
2905
#define GEN_STS(name, stop, op, type)                                         \
2906
GEN_ST(name, stop, op | 0x20, type);                                          \
2907
GEN_STU(name, stop, op | 0x21, type);                                         \
2908
GEN_STUX(name, stop, 0x17, op | 0x01, type);                                  \
2909
GEN_STX(name, stop, 0x17, op | 0x00, type)
2910

    
2911
/* stb stbu stbux stbx */
2912
GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2913
/* sth sthu sthux sthx */
2914
GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2915
/* stw stwu stwux stwx */
2916
GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2917
#if defined(TARGET_PPC64)
2918
GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2919
GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2920
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2921
{
2922
    int rs;
2923
    TCGv EA;
2924

    
2925
    rs = rS(ctx->opcode);
2926
    if ((ctx->opcode & 0x3) == 0x2) {
2927
#if defined(CONFIG_USER_ONLY)
2928
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2929
#else
2930
        /* stq */
2931
        if (unlikely(ctx->mem_idx == 0)) {
2932
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2933
            return;
2934
        }
2935
        if (unlikely(rs & 1)) {
2936
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2937
            return;
2938
        }
2939
        if (unlikely(ctx->le_mode)) {
2940
            /* Little-endian mode is not handled */
2941
            gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2942
            return;
2943
        }
2944
        gen_set_access_type(ctx, ACCESS_INT);
2945
        EA = tcg_temp_new();
2946
        gen_addr_imm_index(ctx, EA, 0x03);
2947
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2948
        gen_addr_add(ctx, EA, EA, 8);
2949
        gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2950
        tcg_temp_free(EA);
2951
#endif
2952
    } else {
2953
        /* std / stdu */
2954
        if (Rc(ctx->opcode)) {
2955
            if (unlikely(rA(ctx->opcode) == 0)) {
2956
                gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2957
                return;
2958
            }
2959
        }
2960
        gen_set_access_type(ctx, ACCESS_INT);
2961
        EA = tcg_temp_new();
2962
        gen_addr_imm_index(ctx, EA, 0x03);
2963
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2964
        if (Rc(ctx->opcode))
2965
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2966
        tcg_temp_free(EA);
2967
    }
2968
}
2969
#endif
2970
/***                Integer load and store with byte reverse               ***/
2971
/* lhbrx */
2972
static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2973
{
2974
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2975
    if (likely(!ctx->le_mode)) {
2976
#if defined(TARGET_PPC64)
2977
        TCGv_i32 t0 = tcg_temp_new_i32();
2978
        tcg_gen_trunc_tl_i32(t0, arg1);
2979
        tcg_gen_bswap16_i32(t0, t0);
2980
        tcg_gen_extu_i32_tl(arg1, t0);
2981
        tcg_temp_free_i32(t0);
2982
#else
2983
        tcg_gen_bswap16_i32(arg1, arg1);
2984
#endif
2985
    }
2986
}
2987
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2988

    
2989
/* lwbrx */
2990
static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2991
{
2992
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2993
    if (likely(!ctx->le_mode)) {
2994
#if defined(TARGET_PPC64)
2995
        TCGv_i32 t0 = tcg_temp_new_i32();
2996
        tcg_gen_trunc_tl_i32(t0, arg1);
2997
        tcg_gen_bswap_i32(t0, t0);
2998
        tcg_gen_extu_i32_tl(arg1, t0);
2999
        tcg_temp_free_i32(t0);
3000
#else
3001
        tcg_gen_bswap_i32(arg1, arg1);
3002
#endif
3003
    }
3004
}
3005
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3006

    
3007
/* sthbrx */
3008
static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3009
{
3010
    if (likely(!ctx->le_mode)) {
3011
#if defined(TARGET_PPC64)
3012
        TCGv_i32 t0;
3013
        TCGv t1;
3014
        t0 = tcg_temp_new_i32();
3015
        tcg_gen_trunc_tl_i32(t0, arg1);
3016
        tcg_gen_ext16u_i32(t0, t0);
3017
        tcg_gen_bswap16_i32(t0, t0);
3018
        t1 = tcg_temp_new();
3019
        tcg_gen_extu_i32_tl(t1, t0);
3020
        tcg_temp_free_i32(t0);
3021
        tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3022
        tcg_temp_free(t1);
3023
#else
3024
        TCGv t0 = tcg_temp_new();
3025
        tcg_gen_ext16u_tl(t0, arg1);
3026
        tcg_gen_bswap16_i32(t0, t0);
3027
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3028
        tcg_temp_free(t0);
3029
#endif
3030
    } else {
3031
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3032
    }
3033
}
3034
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3035

    
3036
/* stwbrx */
3037
static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3038
{
3039
    if (likely(!ctx->le_mode)) {
3040
#if defined(TARGET_PPC64)
3041
        TCGv_i32 t0;
3042
        TCGv t1;
3043
        t0 = tcg_temp_new_i32();
3044
        tcg_gen_trunc_tl_i32(t0, arg1);
3045
        tcg_gen_bswap_i32(t0, t0);
3046
        t1 = tcg_temp_new();
3047
        tcg_gen_extu_i32_tl(t1, t0);
3048
        tcg_temp_free_i32(t0);
3049
        tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3050
        tcg_temp_free(t1);
3051
#else
3052
        TCGv t0 = tcg_temp_new_i32();
3053
        tcg_gen_bswap_i32(t0, arg1);
3054
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3055
        tcg_temp_free(t0);
3056
#endif
3057
    } else {
3058
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3059
    }
3060
}
3061
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3062

    
3063
/***                    Integer load and store multiple                    ***/
3064
/* lmw */
3065
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3066
{
3067
    TCGv t0;
3068
    TCGv_i32 t1;
3069
    gen_set_access_type(ctx, ACCESS_INT);
3070
    /* NIP cannot be restored if the memory exception comes from an helper */
3071
    gen_update_nip(ctx, ctx->nip - 4);
3072
    t0 = tcg_temp_new();
3073
    t1 = tcg_const_i32(rD(ctx->opcode));
3074
    gen_addr_imm_index(ctx, t0, 0);
3075
    gen_helper_lmw(t0, t1);
3076
    tcg_temp_free(t0);
3077
    tcg_temp_free_i32(t1);
3078
}
3079

    
3080
/* stmw */
3081
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3082
{
3083
    TCGv t0;
3084
    TCGv_i32 t1;
3085
    gen_set_access_type(ctx, ACCESS_INT);
3086
    /* NIP cannot be restored if the memory exception comes from an helper */
3087
    gen_update_nip(ctx, ctx->nip - 4);
3088
    t0 = tcg_temp_new();
3089
    t1 = tcg_const_i32(rS(ctx->opcode));
3090
    gen_addr_imm_index(ctx, t0, 0);
3091
    gen_helper_stmw(t0, t1);
3092
    tcg_temp_free(t0);
3093
    tcg_temp_free_i32(t1);
3094
}
3095

    
3096
/***                    Integer load and store strings                     ***/
3097
/* lswi */
3098
/* PowerPC32 specification says we must generate an exception if
3099
 * rA is in the range of registers to be loaded.
3100
 * In an other hand, IBM says this is valid, but rA won't be loaded.
3101
 * For now, I'll follow the spec...
3102
 */
3103
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3104
{
3105
    TCGv t0;
3106
    TCGv_i32 t1, t2;
3107
    int nb = NB(ctx->opcode);
3108
    int start = rD(ctx->opcode);
3109
    int ra = rA(ctx->opcode);
3110
    int nr;
3111

    
3112
    if (nb == 0)
3113
        nb = 32;
3114
    nr = nb / 4;
3115
    if (unlikely(((start + nr) > 32  &&
3116
                  start <= ra && (start + nr - 32) > ra) ||
3117
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3118
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3119
        return;
3120
    }
3121
    gen_set_access_type(ctx, ACCESS_INT);
3122
    /* NIP cannot be restored if the memory exception comes from an helper */
3123
    gen_update_nip(ctx, ctx->nip - 4);
3124
    t0 = tcg_temp_new();
3125
    gen_addr_register(ctx, t0);
3126
    t1 = tcg_const_i32(nb);
3127
    t2 = tcg_const_i32(start);
3128
    gen_helper_lsw(t0, t1, t2);
3129
    tcg_temp_free(t0);
3130
    tcg_temp_free_i32(t1);
3131
    tcg_temp_free_i32(t2);
3132
}
3133

    
3134
/* lswx */
3135
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3136
{
3137
    TCGv t0;
3138
    TCGv_i32 t1, t2, t3;
3139
    gen_set_access_type(ctx, ACCESS_INT);
3140
    /* NIP cannot be restored if the memory exception comes from an helper */
3141
    gen_update_nip(ctx, ctx->nip - 4);
3142
    t0 = tcg_temp_new();
3143
    gen_addr_reg_index(ctx, t0);
3144
    t1 = tcg_const_i32(rD(ctx->opcode));
3145
    t2 = tcg_const_i32(rA(ctx->opcode));
3146
    t3 = tcg_const_i32(rB(ctx->opcode));
3147
    gen_helper_lswx(t0, t1, t2, t3);
3148
    tcg_temp_free(t0);
3149
    tcg_temp_free_i32(t1);
3150
    tcg_temp_free_i32(t2);
3151
    tcg_temp_free_i32(t3);
3152
}
3153

    
3154
/* stswi */
3155
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3156
{
3157
    TCGv t0;
3158
    TCGv_i32 t1, t2;
3159
    int nb = NB(ctx->opcode);
3160
    gen_set_access_type(ctx, ACCESS_INT);
3161
    /* NIP cannot be restored if the memory exception comes from an helper */
3162
    gen_update_nip(ctx, ctx->nip - 4);
3163
    t0 = tcg_temp_new();
3164
    gen_addr_register(ctx, t0);
3165
    if (nb == 0)
3166
        nb = 32;
3167
    t1 = tcg_const_i32(nb);
3168
    t2 = tcg_const_i32(rS(ctx->opcode));
3169
    gen_helper_stsw(t0, t1, t2);
3170
    tcg_temp_free(t0);
3171
    tcg_temp_free_i32(t1);
3172
    tcg_temp_free_i32(t2);
3173
}
3174

    
3175
/* stswx */
3176
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3177
{
3178
    TCGv t0;
3179
    TCGv_i32 t1, t2;
3180
    gen_set_access_type(ctx, ACCESS_INT);
3181
    /* NIP cannot be restored if the memory exception comes from an helper */
3182
    gen_update_nip(ctx, ctx->nip - 4);
3183
    t0 = tcg_temp_new();
3184
    gen_addr_reg_index(ctx, t0);
3185
    t1 = tcg_temp_new_i32();
3186
    tcg_gen_trunc_tl_i32(t1, cpu_xer);
3187
    tcg_gen_andi_i32(t1, t1, 0x7F);
3188
    t2 = tcg_const_i32(rS(ctx->opcode));
3189
    gen_helper_stsw(t0, t1, t2);
3190
    tcg_temp_free(t0);
3191
    tcg_temp_free_i32(t1);
3192
    tcg_temp_free_i32(t2);
3193
}
3194

    
3195
/***                        Memory synchronisation                         ***/
3196
/* eieio */
3197
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3198
{
3199
}
3200

    
3201
/* isync */
3202
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3203
{
3204
    gen_stop_exception(ctx);
3205
}
3206

    
3207
/* lwarx */
3208
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3209
{
3210
    TCGv t0;
3211
    gen_set_access_type(ctx, ACCESS_RES);
3212
    t0 = tcg_temp_local_new();
3213
    gen_addr_reg_index(ctx, t0);
3214
    gen_check_align(ctx, t0, 0x03);
3215
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3216
    tcg_gen_mov_tl(cpu_reserve, t0);
3217
    tcg_temp_free(t0);
3218
}
3219

    
3220
/* stwcx. */
3221
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3222
{
3223
    int l1;
3224
    TCGv t0;
3225
    gen_set_access_type(ctx, ACCESS_RES);
3226
    t0 = tcg_temp_local_new();
3227
    gen_addr_reg_index(ctx, t0);
3228
    gen_check_align(ctx, t0, 0x03);
3229
    tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3230
    tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3231
    tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3232
    l1 = gen_new_label();
3233
    tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3234
    tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3235
    gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3236
    gen_set_label(l1);
3237
    tcg_gen_movi_tl(cpu_reserve, -1);
3238
    tcg_temp_free(t0);
3239
}
3240

    
3241
#if defined(TARGET_PPC64)
3242
/* ldarx */
3243
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3244
{
3245
    TCGv t0;
3246
    gen_set_access_type(ctx, ACCESS_RES);
3247
    t0 = tcg_temp_local_new();
3248
    gen_addr_reg_index(ctx, t0);
3249
    gen_check_align(ctx, t0, 0x07);
3250
    gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3251
    tcg_gen_mov_tl(cpu_reserve, t0);
3252
    tcg_temp_free(t0);
3253
}
3254

    
3255
/* stdcx. */
3256
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3257
{
3258
    int l1;
3259
    TCGv t0;
3260
    gen_set_access_type(ctx, ACCESS_RES);
3261
    t0 = tcg_temp_local_new();
3262
    gen_addr_reg_index(ctx, t0);
3263
    gen_check_align(ctx, t0, 0x07);
3264
    tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3265
    tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3266
    tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3267
    l1 = gen_new_label();
3268
    tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3269
    tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3270
    gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3271
    gen_set_label(l1);
3272
    tcg_gen_movi_tl(cpu_reserve, -1);
3273
    tcg_temp_free(t0);
3274
}
3275
#endif /* defined(TARGET_PPC64) */
3276

    
3277
/* sync */
3278
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3279
{
3280
}
3281

    
3282
/* wait */
3283
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3284
{
3285
    TCGv_i32 t0 = tcg_temp_new_i32();
3286
    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3287
    tcg_temp_free_i32(t0);
3288
    /* Stop translation, as the CPU is supposed to sleep from now */
3289
    gen_exception_err(ctx, EXCP_HLT, 1);
3290
}
3291

    
3292
/***                         Floating-point load                           ***/
3293
#define GEN_LDF(name, ldop, opc, type)                                        \
3294
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
3295
{                                                                             \
3296
    TCGv EA;                                                                  \
3297
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3298
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3299
        return;                                                               \
3300
    }                                                                         \
3301
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3302
    EA = tcg_temp_new();                                                      \
3303
    gen_addr_imm_index(ctx, EA, 0);                                           \
3304
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3305
    tcg_temp_free(EA);                                                        \
3306
}
3307

    
3308
#define GEN_LDUF(name, ldop, opc, type)                                       \
3309
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
3310
{                                                                             \
3311
    TCGv EA;                                                                  \
3312
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3313
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3314
        return;                                                               \
3315
    }                                                                         \
3316
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3317
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3318
        return;                                                               \
3319
    }                                                                         \
3320
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3321
    EA = tcg_temp_new();                                                      \
3322
    gen_addr_imm_index(ctx, EA, 0);                                           \
3323
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3324
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3325
    tcg_temp_free(EA);                                                        \
3326
}
3327

    
3328
#define GEN_LDUXF(name, ldop, opc, type)                                      \
3329
GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type)                      \
3330
{                                                                             \
3331
    TCGv EA;                                                                  \
3332
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3333
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3334
        return;                                                               \
3335
    }                                                                         \
3336
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3337
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3338
        return;                                                               \
3339
    }                                                                         \
3340
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3341
    EA = tcg_temp_new();                                                      \
3342
    gen_addr_reg_index(ctx, EA);                                              \
3343
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3344
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3345
    tcg_temp_free(EA);                                                        \
3346
}
3347

    
3348
#define GEN_LDXF(name, ldop, opc2, opc3, type)                                \
3349
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
3350
{                                                                             \
3351
    TCGv EA;                                                                  \
3352
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3353
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3354
        return;                                                               \
3355
    }                                                                         \
3356
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3357
    EA = tcg_temp_new();                                                      \
3358
    gen_addr_reg_index(ctx, EA);                                              \
3359
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3360
    tcg_temp_free(EA);                                                        \
3361
}
3362

    
3363
#define GEN_LDFS(name, ldop, op, type)                                        \
3364
GEN_LDF(name, ldop, op | 0x20, type);                                         \
3365
GEN_LDUF(name, ldop, op | 0x21, type);                                        \
3366
GEN_LDUXF(name, ldop, op | 0x01, type);                                       \
3367
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3368

    
3369
static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3370
{
3371
    TCGv t0 = tcg_temp_new();
3372
    TCGv_i32 t1 = tcg_temp_new_i32();
3373
    gen_qemu_ld32u(ctx, t0, arg2);
3374
    tcg_gen_trunc_tl_i32(t1, t0);
3375
    tcg_temp_free(t0);
3376
    gen_helper_float32_to_float64(arg1, t1);
3377
    tcg_temp_free_i32(t1);
3378
}
3379

    
3380
 /* lfd lfdu lfdux lfdx */
3381
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3382
 /* lfs lfsu lfsux lfsx */
3383
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3384

    
3385
/***                         Floating-point store                          ***/
3386
#define GEN_STF(name, stop, opc, type)                                        \
3387
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
3388
{                                                                             \
3389
    TCGv EA;                                                                  \
3390
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3391
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3392
        return;                                                               \
3393
    }                                                                         \
3394
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3395
    EA = tcg_temp_new();                                                      \
3396
    gen_addr_imm_index(ctx, EA, 0);                                           \
3397
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3398
    tcg_temp_free(EA);                                                        \
3399
}
3400

    
3401
#define GEN_STUF(name, stop, opc, type)                                       \
3402
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
3403
{                                                                             \
3404
    TCGv EA;                                                                  \
3405
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3406
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3407
        return;                                                               \
3408
    }                                                                         \
3409
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3410
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3411
        return;                                                               \
3412
    }                                                                         \
3413
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3414
    EA = tcg_temp_new();                                                      \
3415
    gen_addr_imm_index(ctx, EA, 0);                                           \
3416
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3417
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3418
    tcg_temp_free(EA);                                                        \
3419
}
3420

    
3421
#define GEN_STUXF(name, stop, opc, type)                                      \
3422
GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type)                      \
3423
{                                                                             \
3424
    TCGv EA;                                                                  \
3425
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3426
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3427
        return;                                                               \
3428
    }                                                                         \
3429
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3430
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3431
        return;                                                               \
3432
    }                                                                         \
3433
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3434
    EA = tcg_temp_new();                                                      \
3435
    gen_addr_reg_index(ctx, EA);                                              \
3436
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3437
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3438
    tcg_temp_free(EA);                                                        \
3439
}
3440

    
3441
#define GEN_STXF(name, stop, opc2, opc3, type)                                \
3442
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
3443
{                                                                             \
3444
    TCGv EA;                                                                  \
3445
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3446
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3447
        return;                                                               \
3448
    }                                                                         \
3449
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3450
    EA = tcg_temp_new();                                                      \
3451
    gen_addr_reg_index(ctx, EA);                                              \
3452
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3453
    tcg_temp_free(EA);                                                        \
3454
}
3455

    
3456
#define GEN_STFS(name, stop, op, type)                                        \
3457
GEN_STF(name, stop, op | 0x20, type);                                         \
3458
GEN_STUF(name, stop, op | 0x21, type);                                        \
3459
GEN_STUXF(name, stop, op | 0x01, type);                                       \
3460
GEN_STXF(name, stop, 0x17, op | 0x00, type)
3461

    
3462
static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3463
{
3464
    TCGv_i32 t0 = tcg_temp_new_i32();
3465
    TCGv t1 = tcg_temp_new();
3466
    gen_helper_float64_to_float32(t0, arg1);
3467
    tcg_gen_extu_i32_tl(t1, t0);
3468
    tcg_temp_free_i32(t0);
3469
    gen_qemu_st32(ctx, t1, arg2);
3470
    tcg_temp_free(t1);
3471
}
3472

    
3473
/* stfd stfdu stfdux stfdx */
3474
GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3475
/* stfs stfsu stfsux stfsx */
3476
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3477

    
3478
/* Optional: */
3479
static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3480
{
3481
    TCGv t0 = tcg_temp_new();
3482
    tcg_gen_trunc_i64_tl(t0, arg1),
3483
    gen_qemu_st32(ctx, t0, arg2);
3484
    tcg_temp_free(t0);
3485
}
3486
/* stfiwx */
3487
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3488

    
3489
/***                                Branch                                 ***/
3490
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3491
                                       target_ulong dest)
3492
{
3493
    TranslationBlock *tb;
3494
    tb = ctx->tb;
3495
#if defined(TARGET_PPC64)
3496
    if (!ctx->sf_mode)
3497
        dest = (uint32_t) dest;
3498
#endif
3499
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3500
        likely(!ctx->singlestep_enabled)) {
3501
        tcg_gen_goto_tb(n);
3502
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3503
        tcg_gen_exit_tb((long)tb + n);
3504
    } else {
3505
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3506
        if (unlikely(ctx->singlestep_enabled)) {
3507
            if ((ctx->singlestep_enabled &
3508
                (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3509
                ctx->exception == POWERPC_EXCP_BRANCH) {
3510
                target_ulong tmp = ctx->nip;
3511
                ctx->nip = dest;
3512
                gen_exception(ctx, POWERPC_EXCP_TRACE);
3513
                ctx->nip = tmp;
3514
            }
3515
            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3516
                gen_debug_exception(ctx);
3517
            }
3518
        }
3519
        tcg_gen_exit_tb(0);
3520
    }
3521
}
3522

    
3523
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3524
{
3525
#if defined(TARGET_PPC64)
3526
    if (ctx->sf_mode == 0)
3527
        tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3528
    else
3529
#endif
3530
        tcg_gen_movi_tl(cpu_lr, nip);
3531
}
3532

    
3533
/* b ba bl bla */
3534
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3535
{
3536
    target_ulong li, target;
3537

    
3538
    ctx->exception = POWERPC_EXCP_BRANCH;
3539
    /* sign extend LI */
3540
#if defined(TARGET_PPC64)
3541
    if (ctx->sf_mode)
3542
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3543
    else
3544
#endif
3545
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3546
    if (likely(AA(ctx->opcode) == 0))
3547
        target = ctx->nip + li - 4;
3548
    else
3549
        target = li;
3550
    if (LK(ctx->opcode))
3551
        gen_setlr(ctx, ctx->nip);
3552
    gen_goto_tb(ctx, 0, target);
3553
}
3554

    
3555
#define BCOND_IM  0
3556
#define BCOND_LR  1
3557
#define BCOND_CTR 2
3558

    
3559
static always_inline void gen_bcond (DisasContext *ctx, int type)
3560
{
3561
    uint32_t bo = BO(ctx->opcode);
3562
    int l1 = gen_new_label();
3563
    TCGv target;
3564

    
3565
    ctx->exception = POWERPC_EXCP_BRANCH;
3566
    if (type == BCOND_LR || type == BCOND_CTR) {
3567
        target = tcg_temp_local_new();
3568
        if (type == BCOND_CTR)
3569
            tcg_gen_mov_tl(target, cpu_ctr);
3570
        else
3571
            tcg_gen_mov_tl(target, cpu_lr);
3572
    }
3573
    if (LK(ctx->opcode))
3574
        gen_setlr(ctx, ctx->nip);
3575
    l1 = gen_new_label();
3576
    if ((bo & 0x4) == 0) {
3577
        /* Decrement and test CTR */
3578
        TCGv temp = tcg_temp_new();
3579
        if (unlikely(type == BCOND_CTR)) {
3580
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3581
            return;
3582
        }
3583
        tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3584
#if defined(TARGET_PPC64)
3585
        if (!ctx->sf_mode)
3586
            tcg_gen_ext32u_tl(temp, cpu_ctr);
3587
        else
3588
#endif
3589
            tcg_gen_mov_tl(temp, cpu_ctr);
3590
        if (bo & 0x2) {
3591
            tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3592
        } else {
3593
            tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3594
        }
3595
        tcg_temp_free(temp);
3596
    }
3597
    if ((bo & 0x10) == 0) {
3598
        /* Test CR */
3599
        uint32_t bi = BI(ctx->opcode);
3600
        uint32_t mask = 1 << (3 - (bi & 0x03));
3601
        TCGv_i32 temp = tcg_temp_new_i32();
3602

    
3603
        if (bo & 0x8) {
3604
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3605
            tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3606
        } else {
3607
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3608
            tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3609
        }
3610
        tcg_temp_free_i32(temp);
3611
    }
3612
    if (type == BCOND_IM) {
3613
        target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3614
        if (likely(AA(ctx->opcode) == 0)) {
3615
            gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3616
        } else {
3617
            gen_goto_tb(ctx, 0, li);
3618
        }
3619
        gen_set_label(l1);
3620
        gen_goto_tb(ctx, 1, ctx->nip);
3621
    } else {
3622
#if defined(TARGET_PPC64)
3623
        if (!(ctx->sf_mode))
3624
            tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3625
        else
3626
#endif
3627
            tcg_gen_andi_tl(cpu_nip, target, ~3);
3628
        tcg_gen_exit_tb(0);
3629
        gen_set_label(l1);
3630
#if defined(TARGET_PPC64)
3631
        if (!(ctx->sf_mode))
3632
            tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3633
        else
3634
#endif
3635
            tcg_gen_movi_tl(cpu_nip, ctx->nip);
3636
        tcg_gen_exit_tb(0);
3637
    }
3638
}
3639

    
3640
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3641
{
3642
    gen_bcond(ctx, BCOND_IM);
3643
}
3644

    
3645
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3646
{
3647
    gen_bcond(ctx, BCOND_CTR);
3648
}
3649

    
3650
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3651
{
3652
    gen_bcond(ctx, BCOND_LR);
3653
}
3654

    
3655
/***                      Condition register logical                       ***/
3656
#define GEN_CRLOGIC(name, tcg_op, opc)                                        \
3657
GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                   \
3658
{                                                                             \
3659
    uint8_t bitmask;                                                          \
3660
    int sh;                                                                   \
3661
    TCGv_i32 t0, t1;                                                          \
3662
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3663
    t0 = tcg_temp_new_i32();                                                  \
3664
    if (sh > 0)                                                               \
3665
        tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
3666
    else if (sh < 0)                                                          \
3667
        tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
3668
    else                                                                      \
3669
        tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
3670
    t1 = tcg_temp_new_i32();                                                  \
3671
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3672
    if (sh > 0)                                                               \
3673
        tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
3674
    else if (sh < 0)                                                          \
3675
        tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
3676
    else                                                                      \
3677
        tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
3678
    tcg_op(t0, t0, t1);                                                       \
3679
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3680
    tcg_gen_andi_i32(t0, t0, bitmask);                                        \
3681
    tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
3682
    tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
3683
    tcg_temp_free_i32(t0);                                                    \
3684
    tcg_temp_free_i32(t1);                                                    \
3685
}
3686

    
3687
/* crand */
3688
GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3689
/* crandc */
3690
GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3691
/* creqv */
3692
GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3693
/* crnand */
3694
GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3695
/* crnor */
3696
GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3697
/* cror */
3698
GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3699
/* crorc */
3700
GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3701
/* crxor */
3702
GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3703
/* mcrf */
3704
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3705
{
3706
    tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3707
}
3708

    
3709
/***                           System linkage                              ***/
3710
/* rfi (mem_idx only) */
3711
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3712
{
3713
#if defined(CONFIG_USER_ONLY)
3714
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3715
#else
3716
    /* Restore CPU state */
3717
    if (unlikely(!ctx->mem_idx)) {
3718
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3719
        return;
3720
    }
3721
    gen_helper_rfi();
3722
    gen_sync_exception(ctx);
3723
#endif
3724
}
3725

    
3726
#if defined(TARGET_PPC64)
3727
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3728
{
3729
#if defined(CONFIG_USER_ONLY)
3730
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3731
#else
3732
    /* Restore CPU state */
3733
    if (unlikely(!ctx->mem_idx)) {
3734
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3735
        return;
3736
    }
3737
    gen_helper_rfid();
3738
    gen_sync_exception(ctx);
3739
#endif
3740
}
3741

    
3742
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3743
{
3744
#if defined(CONFIG_USER_ONLY)
3745
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3746
#else
3747
    /* Restore CPU state */
3748
    if (unlikely(ctx->mem_idx <= 1)) {
3749
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3750
        return;
3751
    }
3752
    gen_helper_hrfid();
3753
    gen_sync_exception(ctx);
3754
#endif
3755
}
3756
#endif
3757

    
3758
/* sc */
3759
#if defined(CONFIG_USER_ONLY)
3760
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3761
#else
3762
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3763
#endif
3764
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3765
{
3766
    uint32_t lev;
3767

    
3768
    lev = (ctx->opcode >> 5) & 0x7F;
3769
    gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3770
}
3771

    
3772
/***                                Trap                                   ***/
3773
/* tw */
3774
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3775
{
3776
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3777
    /* Update the nip since this might generate a trap exception */
3778
    gen_update_nip(ctx, ctx->nip);
3779
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3780
    tcg_temp_free_i32(t0);
3781
}
3782

    
3783
/* twi */
3784
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3785
{
3786
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3787
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3788
    /* Update the nip since this might generate a trap exception */
3789
    gen_update_nip(ctx, ctx->nip);
3790
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3791
    tcg_temp_free(t0);
3792
    tcg_temp_free_i32(t1);
3793
}
3794

    
3795
#if defined(TARGET_PPC64)
3796
/* td */
3797
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3798
{
3799
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3800
    /* Update the nip since this might generate a trap exception */
3801
    gen_update_nip(ctx, ctx->nip);
3802
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3803
    tcg_temp_free_i32(t0);
3804
}
3805

    
3806
/* tdi */
3807
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3808
{
3809
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3810
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3811
    /* Update the nip since this might generate a trap exception */
3812
    gen_update_nip(ctx, ctx->nip);
3813
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3814
    tcg_temp_free(t0);
3815
    tcg_temp_free_i32(t1);
3816
}
3817
#endif
3818

    
3819
/***                          Processor control                            ***/
3820
/* mcrxr */
3821
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3822
{
3823
    tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3824
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3825
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3826
}
3827

    
3828
/* mfcr */
3829
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3830
{
3831
    uint32_t crm, crn;
3832

    
3833
    if (likely(ctx->opcode & 0x00100000)) {
3834
        crm = CRM(ctx->opcode);
3835
        if (likely((crm ^ (crm - 1)) == 0)) {
3836
            crn = ffs(crm);
3837
            tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3838
        }
3839
    } else {
3840
        gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3841
    }
3842
}
3843

    
3844
/* mfmsr */
3845
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3846
{
3847
#if defined(CONFIG_USER_ONLY)
3848
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3849
#else
3850
    if (unlikely(!ctx->mem_idx)) {
3851
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3852
        return;
3853
    }
3854
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3855
#endif
3856
}
3857

    
3858
#if 1
3859
#define SPR_NOACCESS ((void *)(-1UL))
3860
#else
3861
static void spr_noaccess (void *opaque, int sprn)
3862
{
3863
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3864
    printf("ERROR: try to access SPR %d !\n", sprn);
3865
}
3866
#define SPR_NOACCESS (&spr_noaccess)
3867
#endif
3868

    
3869
/* mfspr */
3870
static always_inline void gen_op_mfspr (DisasContext *ctx)
3871
{
3872
    void (*read_cb)(void *opaque, int gprn, int sprn);
3873
    uint32_t sprn = SPR(ctx->opcode);
3874

    
3875
#if !defined(CONFIG_USER_ONLY)
3876
    if (ctx->mem_idx == 2)
3877
        read_cb = ctx->spr_cb[sprn].hea_read;
3878
    else if (ctx->mem_idx)
3879
        read_cb = ctx->spr_cb[sprn].oea_read;
3880
    else
3881
#endif
3882
        read_cb = ctx->spr_cb[sprn].uea_read;
3883
    if (likely(read_cb != NULL)) {
3884
        if (likely(read_cb != SPR_NOACCESS)) {
3885
            (*read_cb)(ctx, rD(ctx->opcode), sprn);
3886
        } else {
3887
            /* Privilege exception */
3888
            /* This is a hack to avoid warnings when running Linux:
3889
             * this OS breaks the PowerPC virtualisation model,
3890
             * allowing userland application to read the PVR
3891
             */
3892
            if (sprn != SPR_PVR) {
3893
                if (loglevel != 0) {
3894
                    fprintf(logfile, "Trying to read privileged spr %d %03x at "
3895
                            ADDRX "\n", sprn, sprn, ctx->nip);
3896
                }
3897
                printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3898
                       sprn, sprn, ctx->nip);
3899
            }
3900
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3901
        }
3902
    } else {
3903
        /* Not defined */
3904
        if (loglevel != 0) {
3905
            fprintf(logfile, "Trying to read invalid spr %d %03x at "
3906
                    ADDRX "\n", sprn, sprn, ctx->nip);
3907
        }
3908
        printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3909
               sprn, sprn, ctx->nip);
3910
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3911
    }
3912
}
3913

    
3914
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3915
{
3916
    gen_op_mfspr(ctx);
3917
}
3918

    
3919
/* mftb */
3920
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3921
{
3922
    gen_op_mfspr(ctx);
3923
}
3924

    
3925
/* mtcrf */
3926
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3927
{
3928
    uint32_t crm, crn;
3929

    
3930
    crm = CRM(ctx->opcode);
3931
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3932
        TCGv_i32 temp = tcg_temp_new_i32();
3933
        crn = ffs(crm);
3934
        tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3935
        tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3936
        tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3937
        tcg_temp_free_i32(temp);
3938
    } else {
3939
        TCGv_i32 temp = tcg_const_i32(crm);
3940
        gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3941
        tcg_temp_free_i32(temp);
3942
    }
3943
}
3944

    
3945
/* mtmsr */
3946
#if defined(TARGET_PPC64)
3947
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3948
{
3949
#if defined(CONFIG_USER_ONLY)
3950
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3951
#else
3952
    if (unlikely(!ctx->mem_idx)) {
3953
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3954
        return;
3955
    }
3956
    if (ctx->opcode & 0x00010000) {
3957
        /* Special form that does not need any synchronisation */
3958
        TCGv t0 = tcg_temp_new();
3959
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3960
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3961
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3962
        tcg_temp_free(t0);
3963
    } else {
3964
        /* XXX: we need to update nip before the store
3965
         *      if we enter power saving mode, we will exit the loop
3966
         *      directly from ppc_store_msr
3967
         */
3968
        gen_update_nip(ctx, ctx->nip);
3969
        gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3970
        /* Must stop the translation as machine state (may have) changed */
3971
        /* Note that mtmsr is not always defined as context-synchronizing */
3972
        gen_stop_exception(ctx);
3973
    }
3974
#endif
3975
}
3976
#endif
3977

    
3978
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3979
{
3980
#if defined(CONFIG_USER_ONLY)
3981
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3982
#else
3983
    if (unlikely(!ctx->mem_idx)) {
3984
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3985
        return;
3986
    }
3987
    if (ctx->opcode & 0x00010000) {
3988
        /* Special form that does not need any synchronisation */
3989
        TCGv t0 = tcg_temp_new();
3990
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3991
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3992
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3993
        tcg_temp_free(t0);
3994
    } else {
3995
        /* XXX: we need to update nip before the store
3996
         *      if we enter power saving mode, we will exit the loop
3997
         *      directly from ppc_store_msr
3998
         */
3999
        gen_update_nip(ctx, ctx->nip);
4000
#if defined(TARGET_PPC64)
4001
        if (!ctx->sf_mode) {
4002
            TCGv t0 = tcg_temp_new();
4003
            TCGv t1 = tcg_temp_new();
4004
            tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4005
            tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4006
            tcg_gen_or_tl(t0, t0, t1);
4007
            tcg_temp_free(t1);
4008
            gen_helper_store_msr(t0);
4009
            tcg_temp_free(t0);
4010
        } else
4011
#endif
4012
            gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4013
        /* Must stop the translation as machine state (may have) changed */
4014
        /* Note that mtmsr is not always defined as context-synchronizing */
4015
        gen_stop_exception(ctx);
4016
    }
4017
#endif
4018
}
4019

    
4020
/* mtspr */
4021
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4022
{
4023
    void (*write_cb)(void *opaque, int sprn, int gprn);
4024
    uint32_t sprn = SPR(ctx->opcode);
4025

    
4026
#if !defined(CONFIG_USER_ONLY)
4027
    if (ctx->mem_idx == 2)
4028
        write_cb = ctx->spr_cb[sprn].hea_write;
4029
    else if (ctx->mem_idx)
4030
        write_cb = ctx->spr_cb[sprn].oea_write;
4031
    else
4032
#endif
4033
        write_cb = ctx->spr_cb[sprn].uea_write;
4034
    if (likely(write_cb != NULL)) {
4035
        if (likely(write_cb != SPR_NOACCESS)) {
4036
            (*write_cb)(ctx, sprn, rS(ctx->opcode));
4037
        } else {
4038
            /* Privilege exception */
4039
            if (loglevel != 0) {
4040
                fprintf(logfile, "Trying to write privileged spr %d %03x at "
4041
                        ADDRX "\n", sprn, sprn, ctx->nip);
4042
            }
4043
            printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4044
                   sprn, sprn, ctx->nip);
4045
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4046
        }
4047
    } else {
4048
        /* Not defined */
4049
        if (loglevel != 0) {
4050
            fprintf(logfile, "Trying to write invalid spr %d %03x at "
4051
                    ADDRX "\n", sprn, sprn, ctx->nip);
4052
        }
4053
        printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4054
               sprn, sprn, ctx->nip);
4055
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4056
    }
4057
}
4058

    
4059
/***                         Cache management                              ***/
4060
/* dcbf */
4061
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4062
{
4063
    /* XXX: specification says this is treated as a load by the MMU */
4064
    TCGv t0;
4065
    gen_set_access_type(ctx, ACCESS_CACHE);
4066
    t0 = tcg_temp_new();
4067
    gen_addr_reg_index(ctx, t0);
4068
    gen_qemu_ld8u(ctx, t0, t0);
4069
    tcg_temp_free(t0);
4070
}
4071

    
4072
/* dcbi (Supervisor only) */
4073
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4074
{
4075
#if defined(CONFIG_USER_ONLY)
4076
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4077
#else
4078
    TCGv EA, val;
4079
    if (unlikely(!ctx->mem_idx)) {
4080
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4081
        return;
4082
    }
4083
    EA = tcg_temp_new();
4084
    gen_set_access_type(ctx, ACCESS_CACHE);
4085
    gen_addr_reg_index(ctx, EA);
4086
    val = tcg_temp_new();
4087
    /* XXX: specification says this should be treated as a store by the MMU */
4088
    gen_qemu_ld8u(ctx, val, EA);
4089
    gen_qemu_st8(ctx, val, EA);
4090
    tcg_temp_free(val);
4091
    tcg_temp_free(EA);
4092
#endif
4093
}
4094

    
4095
/* dcdst */
4096
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4097
{
4098
    /* XXX: specification say this is treated as a load by the MMU */
4099
    TCGv t0;
4100
    gen_set_access_type(ctx, ACCESS_CACHE);
4101
    t0 = tcg_temp_new();
4102
    gen_addr_reg_index(ctx, t0);
4103
    gen_qemu_ld8u(ctx, t0, t0);
4104
    tcg_temp_free(t0);
4105
}
4106

    
4107
/* dcbt */
4108
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4109
{
4110
    /* interpreted as no-op */
4111
    /* XXX: specification say this is treated as a load by the MMU
4112
     *      but does not generate any exception
4113
     */
4114
}
4115

    
4116
/* dcbtst */
4117
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4118
{
4119
    /* interpreted as no-op */
4120
    /* XXX: specification say this is treated as a load by the MMU
4121
     *      but does not generate any exception
4122
     */
4123
}
4124

    
4125
/* dcbz */
4126
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4127
{
4128
    TCGv t0;
4129
    gen_set_access_type(ctx, ACCESS_CACHE);
4130
    /* NIP cannot be restored if the memory exception comes from an helper */
4131
    gen_update_nip(ctx, ctx->nip - 4);
4132
    t0 = tcg_temp_new();
4133
    gen_addr_reg_index(ctx, t0);
4134
    gen_helper_dcbz(t0);
4135
    tcg_temp_free(t0);
4136
}
4137

    
4138
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4139
{
4140
    TCGv t0;
4141
    gen_set_access_type(ctx, ACCESS_CACHE);
4142
    /* NIP cannot be restored if the memory exception comes from an helper */
4143
    gen_update_nip(ctx, ctx->nip - 4);
4144
    t0 = tcg_temp_new();
4145
    gen_addr_reg_index(ctx, t0);
4146
    if (ctx->opcode & 0x00200000)
4147
        gen_helper_dcbz(t0);
4148
    else
4149
        gen_helper_dcbz_970(t0);
4150
    tcg_temp_free(t0);
4151
}
4152

    
4153
/* icbi */
4154
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4155
{
4156
    TCGv t0;
4157
    gen_set_access_type(ctx, ACCESS_CACHE);
4158
    /* NIP cannot be restored if the memory exception comes from an helper */
4159
    gen_update_nip(ctx, ctx->nip - 4);
4160
    t0 = tcg_temp_new();
4161
    gen_addr_reg_index(ctx, t0);
4162
    gen_helper_icbi(t0);
4163
    tcg_temp_free(t0);
4164
}
4165

    
4166
/* Optional: */
4167
/* dcba */
4168
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4169
{
4170
    /* interpreted as no-op */
4171
    /* XXX: specification say this is treated as a store by the MMU
4172
     *      but does not generate any exception
4173
     */
4174
}
4175

    
4176
/***                    Segment register manipulation                      ***/
4177
/* Supervisor only: */
4178
/* mfsr */
4179
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4180
{
4181
#if defined(CONFIG_USER_ONLY)
4182
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4183
#else
4184
    TCGv t0;
4185
    if (unlikely(!ctx->mem_idx)) {
4186
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4187
        return;
4188
    }
4189
    t0 = tcg_const_tl(SR(ctx->opcode));
4190
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4191
    tcg_temp_free(t0);
4192
#endif
4193
}
4194

    
4195
/* mfsrin */
4196
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4197
{
4198
#if defined(CONFIG_USER_ONLY)
4199
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4200
#else
4201
    TCGv t0;
4202
    if (unlikely(!ctx->mem_idx)) {
4203
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4204
        return;
4205
    }
4206
    t0 = tcg_temp_new();
4207
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4208
    tcg_gen_andi_tl(t0, t0, 0xF);
4209
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4210
    tcg_temp_free(t0);
4211
#endif
4212
}
4213

    
4214
/* mtsr */
4215
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4216
{
4217
#if defined(CONFIG_USER_ONLY)
4218
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4219
#else
4220
    TCGv t0;
4221
    if (unlikely(!ctx->mem_idx)) {
4222
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4223
        return;
4224
    }
4225
    t0 = tcg_const_tl(SR(ctx->opcode));
4226
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4227
    tcg_temp_free(t0);
4228
#endif
4229
}
4230

    
4231
/* mtsrin */
4232
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4233
{
4234
#if defined(CONFIG_USER_ONLY)
4235
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4236
#else
4237
    TCGv t0;
4238
    if (unlikely(!ctx->mem_idx)) {
4239
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4240
        return;
4241
    }
4242
    t0 = tcg_temp_new();
4243
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4244
    tcg_gen_andi_tl(t0, t0, 0xF);
4245
    gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4246
    tcg_temp_free(t0);
4247
#endif
4248
}
4249

    
4250
#if defined(TARGET_PPC64)
4251
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4252
/* mfsr */
4253
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4254
{
4255
#if defined(CONFIG_USER_ONLY)
4256
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4257
#else
4258
    TCGv t0;
4259
    if (unlikely(!ctx->mem_idx)) {
4260
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4261
        return;
4262
    }
4263
    t0 = tcg_const_tl(SR(ctx->opcode));
4264
    gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4265
    tcg_temp_free(t0);
4266
#endif
4267
}
4268

    
4269
/* mfsrin */
4270
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4271
             PPC_SEGMENT_64B)
4272
{
4273
#if defined(CONFIG_USER_ONLY)
4274
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4275
#else
4276
    TCGv t0;
4277
    if (unlikely(!ctx->mem_idx)) {
4278
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4279
        return;
4280
    }
4281
    t0 = tcg_temp_new();
4282
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4283
    tcg_gen_andi_tl(t0, t0, 0xF);
4284
    gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4285
    tcg_temp_free(t0);
4286
#endif
4287
}
4288

    
4289
/* mtsr */
4290
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4291
{
4292
#if defined(CONFIG_USER_ONLY)
4293
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4294
#else
4295
    TCGv t0;
4296
    if (unlikely(!ctx->mem_idx)) {
4297
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4298
        return;
4299
    }
4300
    t0 = tcg_const_tl(SR(ctx->opcode));
4301
    gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4302
    tcg_temp_free(t0);
4303
#endif
4304
}
4305

    
4306
/* mtsrin */
4307
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4308
             PPC_SEGMENT_64B)
4309
{
4310
#if defined(CONFIG_USER_ONLY)
4311
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4312
#else
4313
    TCGv t0;
4314
    if (unlikely(!ctx->mem_idx)) {
4315
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4316
        return;
4317
    }
4318
    t0 = tcg_temp_new();
4319
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4320
    tcg_gen_andi_tl(t0, t0, 0xF);
4321
    gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4322
    tcg_temp_free(t0);
4323
#endif
4324
}
4325
#endif /* defined(TARGET_PPC64) */
4326

    
4327
/***                      Lookaside buffer management                      ***/
4328
/* Optional & mem_idx only: */
4329
/* tlbia */
4330
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4331
{
4332
#if defined(CONFIG_USER_ONLY)
4333
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4334
#else
4335
    if (unlikely(!ctx->mem_idx)) {
4336
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4337
        return;
4338
    }
4339
    gen_helper_tlbia();
4340
#endif
4341
}
4342

    
4343
/* tlbie */
4344
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4345
{
4346
#if defined(CONFIG_USER_ONLY)
4347
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4348
#else
4349
    if (unlikely(!ctx->mem_idx)) {
4350
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4351
        return;
4352
    }
4353
#if defined(TARGET_PPC64)
4354
    if (!ctx->sf_mode) {
4355
        TCGv t0 = tcg_temp_new();
4356
        tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4357
        gen_helper_tlbie(t0);
4358
        tcg_temp_free(t0);
4359
    } else
4360
#endif
4361
        gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4362
#endif
4363
}
4364

    
4365
/* tlbsync */
4366
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4367
{
4368
#if defined(CONFIG_USER_ONLY)
4369
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4370
#else
4371
    if (unlikely(!ctx->mem_idx)) {
4372
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4373
        return;
4374
    }
4375
    /* This has no effect: it should ensure that all previous
4376
     * tlbie have completed
4377
     */
4378
    gen_stop_exception(ctx);
4379
#endif
4380
}
4381

    
4382
#if defined(TARGET_PPC64)
4383
/* slbia */
4384
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4385
{
4386
#if defined(CONFIG_USER_ONLY)
4387
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4388
#else
4389
    if (unlikely(!ctx->mem_idx)) {
4390
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4391
        return;
4392
    }
4393
    gen_helper_slbia();
4394
#endif
4395
}
4396

    
4397
/* slbie */
4398
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4399
{
4400
#if defined(CONFIG_USER_ONLY)
4401
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4402
#else
4403
    if (unlikely(!ctx->mem_idx)) {
4404
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4405
        return;
4406
    }
4407
    gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4408
#endif
4409
}
4410
#endif
4411

    
4412
/***                              External control                         ***/
4413
/* Optional: */
4414
/* eciwx */
4415
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4416
{
4417
    TCGv t0;
4418
    /* Should check EAR[E] ! */
4419
    gen_set_access_type(ctx, ACCESS_EXT);
4420
    t0 = tcg_temp_new();
4421
    gen_addr_reg_index(ctx, t0);
4422
    gen_check_align(ctx, t0, 0x03);
4423
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4424
    tcg_temp_free(t0);
4425
}
4426

    
4427
/* ecowx */
4428
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4429
{
4430
    TCGv t0;
4431
    /* Should check EAR[E] ! */
4432
    gen_set_access_type(ctx, ACCESS_EXT);
4433
    t0 = tcg_temp_new();
4434
    gen_addr_reg_index(ctx, t0);
4435
    gen_check_align(ctx, t0, 0x03);
4436
    gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4437
    tcg_temp_free(t0);
4438
}
4439

    
4440
/* PowerPC 601 specific instructions */
4441
/* abs - abs. */
4442
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4443
{
4444
    int l1 = gen_new_label();
4445
    int l2 = gen_new_label();
4446
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4447
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4448
    tcg_gen_br(l2);
4449
    gen_set_label(l1);
4450
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4451
    gen_set_label(l2);
4452
    if (unlikely(Rc(ctx->opcode) != 0))
4453
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4454
}
4455

    
4456
/* abso - abso. */
4457
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4458
{
4459
    int l1 = gen_new_label();
4460
    int l2 = gen_new_label();
4461
    int l3 = gen_new_label();
4462
    /* Start with XER OV disabled, the most likely case */
4463
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4464
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4465
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4466
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4467
    tcg_gen_br(l2);
4468
    gen_set_label(l1);
4469
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4470
    tcg_gen_br(l3);
4471
    gen_set_label(l2);
4472
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4473
    gen_set_label(l3);
4474
    if (unlikely(Rc(ctx->opcode) != 0))
4475
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4476
}
4477

    
4478
/* clcs */
4479
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4480
{
4481
    TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4482
    gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4483
    tcg_temp_free_i32(t0);
4484
    /* Rc=1 sets CR0 to an undefined state */
4485
}
4486

    
4487
/* div - div. */
4488
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4489
{
4490
    gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4491
    if (unlikely(Rc(ctx->opcode) != 0))
4492
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4493
}
4494

    
4495
/* divo - divo. */
4496
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4497
{
4498
    gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4499
    if (unlikely(Rc(ctx->opcode) != 0))
4500
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4501
}
4502

    
4503
/* divs - divs. */
4504
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4505
{
4506
    gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4507
    if (unlikely(Rc(ctx->opcode) != 0))
4508
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4509
}
4510

    
4511
/* divso - divso. */
4512
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4513
{
4514
    gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4515
    if (unlikely(Rc(ctx->opcode) != 0))
4516
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4517
}
4518

    
4519
/* doz - doz. */
4520
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4521
{
4522
    int l1 = gen_new_label();
4523
    int l2 = gen_new_label();
4524
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4525
    tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4526
    tcg_gen_br(l2);
4527
    gen_set_label(l1);
4528
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4529
    gen_set_label(l2);
4530
    if (unlikely(Rc(ctx->opcode) != 0))
4531
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4532
}
4533

    
4534
/* dozo - dozo. */
4535
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4536
{
4537
    int l1 = gen_new_label();
4538
    int l2 = gen_new_label();
4539
    TCGv t0 = tcg_temp_new();
4540
    TCGv t1 = tcg_temp_new();
4541
    TCGv t2 = tcg_temp_new();
4542
    /* Start with XER OV disabled, the most likely case */
4543
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4544
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4545
    tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4546
    tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4547
    tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4548
    tcg_gen_andc_tl(t1, t1, t2);
4549
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4550
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4551
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4552
    tcg_gen_br(l2);
4553
    gen_set_label(l1);
4554
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4555
    gen_set_label(l2);
4556
    tcg_temp_free(t0);
4557
    tcg_temp_free(t1);
4558
    tcg_temp_free(t2);
4559
    if (unlikely(Rc(ctx->opcode) != 0))
4560
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4561
}
4562

    
4563
/* dozi */
4564
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4565
{
4566
    target_long simm = SIMM(ctx->opcode);
4567
    int l1 = gen_new_label();
4568
    int l2 = gen_new_label();
4569
    tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4570
    tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4571
    tcg_gen_br(l2);
4572
    gen_set_label(l1);
4573
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4574
    gen_set_label(l2);
4575
    if (unlikely(Rc(ctx->opcode) != 0))
4576
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4577
}
4578

    
4579
/* lscbx - lscbx. */
4580
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4581
{
4582
    TCGv t0 = tcg_temp_new();
4583
    TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4584
    TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4585
    TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4586

    
4587
    gen_addr_reg_index(ctx, t0);
4588
    /* NIP cannot be restored if the memory exception comes from an helper */
4589
    gen_update_nip(ctx, ctx->nip - 4);
4590
    gen_helper_lscbx(t0, t0, t1, t2, t3);
4591
    tcg_temp_free_i32(t1);
4592
    tcg_temp_free_i32(t2);
4593
    tcg_temp_free_i32(t3);
4594
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4595
    tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4596
    if (unlikely(Rc(ctx->opcode) != 0))
4597
        gen_set_Rc0(ctx, t0);
4598
    tcg_temp_free(t0);
4599
}
4600

    
4601
/* maskg - maskg. */
4602
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4603
{
4604
    int l1 = gen_new_label();
4605
    TCGv t0 = tcg_temp_new();
4606
    TCGv t1 = tcg_temp_new();
4607
    TCGv t2 = tcg_temp_new();
4608
    TCGv t3 = tcg_temp_new();
4609
    tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4610
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4611
    tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4612
    tcg_gen_addi_tl(t2, t0, 1);
4613
    tcg_gen_shr_tl(t2, t3, t2);
4614
    tcg_gen_shr_tl(t3, t3, t1);
4615
    tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4616
    tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4617
    tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4618
    gen_set_label(l1);
4619
    tcg_temp_free(t0);
4620
    tcg_temp_free(t1);
4621
    tcg_temp_free(t2);
4622
    tcg_temp_free(t3);
4623
    if (unlikely(Rc(ctx->opcode) != 0))
4624
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4625
}
4626

    
4627
/* maskir - maskir. */
4628
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4629
{
4630
    TCGv t0 = tcg_temp_new();
4631
    TCGv t1 = tcg_temp_new();
4632
    tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4633
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4634
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4635
    tcg_temp_free(t0);
4636
    tcg_temp_free(t1);
4637
    if (unlikely(Rc(ctx->opcode) != 0))
4638
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4639
}
4640

    
4641
/* mul - mul. */
4642
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4643
{
4644
    TCGv_i64 t0 = tcg_temp_new_i64();
4645
    TCGv_i64 t1 = tcg_temp_new_i64();
4646
    TCGv t2 = tcg_temp_new();
4647
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4648
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4649
    tcg_gen_mul_i64(t0, t0, t1);
4650
    tcg_gen_trunc_i64_tl(t2, t0);
4651
    gen_store_spr(SPR_MQ, t2);
4652
    tcg_gen_shri_i64(t1, t0, 32);
4653
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4654
    tcg_temp_free_i64(t0);
4655
    tcg_temp_free_i64(t1);
4656
    tcg_temp_free(t2);
4657
    if (unlikely(Rc(ctx->opcode) != 0))
4658
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4659
}
4660

    
4661
/* mulo - mulo. */
4662
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4663
{
4664
    int l1 = gen_new_label();
4665
    TCGv_i64 t0 = tcg_temp_new_i64();
4666
    TCGv_i64 t1 = tcg_temp_new_i64();
4667
    TCGv t2 = tcg_temp_new();
4668
    /* Start with XER OV disabled, the most likely case */
4669
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4670
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4671
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4672
    tcg_gen_mul_i64(t0, t0, t1);
4673
    tcg_gen_trunc_i64_tl(t2, t0);
4674
    gen_store_spr(SPR_MQ, t2);
4675
    tcg_gen_shri_i64(t1, t0, 32);
4676
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4677
    tcg_gen_ext32s_i64(t1, t0);
4678
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4679
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4680
    gen_set_label(l1);
4681
    tcg_temp_free_i64(t0);
4682
    tcg_temp_free_i64(t1);
4683
    tcg_temp_free(t2);
4684
    if (unlikely(Rc(ctx->opcode) != 0))
4685
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4686
}
4687

    
4688
/* nabs - nabs. */
4689
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4690
{
4691
    int l1 = gen_new_label();
4692
    int l2 = gen_new_label();
4693
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4694
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4695
    tcg_gen_br(l2);
4696
    gen_set_label(l1);
4697
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4698
    gen_set_label(l2);
4699
    if (unlikely(Rc(ctx->opcode) != 0))
4700
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4701
}
4702

    
4703
/* nabso - nabso. */
4704
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4705
{
4706
    int l1 = gen_new_label();
4707
    int l2 = gen_new_label();
4708
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4709
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4710
    tcg_gen_br(l2);
4711
    gen_set_label(l1);
4712
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4713
    gen_set_label(l2);
4714
    /* nabs never overflows */
4715
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4716
    if (unlikely(Rc(ctx->opcode) != 0))
4717
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4718
}
4719

    
4720
/* rlmi - rlmi. */
4721
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4722
{
4723
    uint32_t mb = MB(ctx->opcode);
4724
    uint32_t me = ME(ctx->opcode);
4725
    TCGv t0 = tcg_temp_new();
4726
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4727
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4728
    tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4729
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4730
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4731
    tcg_temp_free(t0);
4732
    if (unlikely(Rc(ctx->opcode) != 0))
4733
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4734
}
4735

    
4736
/* rrib - rrib. */
4737
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4738
{
4739
    TCGv t0 = tcg_temp_new();
4740
    TCGv t1 = tcg_temp_new();
4741
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4742
    tcg_gen_movi_tl(t1, 0x80000000);
4743
    tcg_gen_shr_tl(t1, t1, t0);
4744
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4745
    tcg_gen_and_tl(t0, t0, t1);
4746
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4747
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4748
    tcg_temp_free(t0);
4749
    tcg_temp_free(t1);
4750
    if (unlikely(Rc(ctx->opcode) != 0))
4751
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4752
}
4753

    
4754
/* sle - sle. */
4755
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4756
{
4757
    TCGv t0 = tcg_temp_new();
4758
    TCGv t1 = tcg_temp_new();
4759
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4760
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4761
    tcg_gen_subfi_tl(t1, 32, t1);
4762
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4763
    tcg_gen_or_tl(t1, t0, t1);
4764
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4765
    gen_store_spr(SPR_MQ, t1);
4766
    tcg_temp_free(t0);
4767
    tcg_temp_free(t1);
4768
    if (unlikely(Rc(ctx->opcode) != 0))
4769
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4770
}
4771

    
4772
/* sleq - sleq. */
4773
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4774
{
4775
    TCGv t0 = tcg_temp_new();
4776
    TCGv t1 = tcg_temp_new();
4777
    TCGv t2 = tcg_temp_new();
4778
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4779
    tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4780
    tcg_gen_shl_tl(t2, t2, t0);
4781
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4782
    gen_load_spr(t1, SPR_MQ);
4783
    gen_store_spr(SPR_MQ, t0);
4784
    tcg_gen_and_tl(t0, t0, t2);
4785
    tcg_gen_andc_tl(t1, t1, t2);
4786
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4787
    tcg_temp_free(t0);
4788
    tcg_temp_free(t1);
4789
    tcg_temp_free(t2);
4790
    if (unlikely(Rc(ctx->opcode) != 0))
4791
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4792
}
4793

    
4794
/* sliq - sliq. */
4795
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4796
{
4797
    int sh = SH(ctx->opcode);
4798
    TCGv t0 = tcg_temp_new();
4799
    TCGv t1 = tcg_temp_new();
4800
    tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4801
    tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4802
    tcg_gen_or_tl(t1, t0, t1);
4803
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4804
    gen_store_spr(SPR_MQ, t1);
4805
    tcg_temp_free(t0);
4806
    tcg_temp_free(t1);
4807
    if (unlikely(Rc(ctx->opcode) != 0))
4808
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4809
}
4810

    
4811
/* slliq - slliq. */
4812
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4813
{
4814
    int sh = SH(ctx->opcode);
4815
    TCGv t0 = tcg_temp_new();
4816
    TCGv t1 = tcg_temp_new();
4817
    tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4818
    gen_load_spr(t1, SPR_MQ);
4819
    gen_store_spr(SPR_MQ, t0);
4820
    tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU << sh));
4821
    tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4822
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4823
    tcg_temp_free(t0);
4824
    tcg_temp_free(t1);
4825
    if (unlikely(Rc(ctx->opcode) != 0))
4826
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4827
}
4828

    
4829
/* sllq - sllq. */
4830
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4831
{
4832
    int l1 = gen_new_label();
4833
    int l2 = gen_new_label();
4834
    TCGv t0 = tcg_temp_local_new();
4835
    TCGv t1 = tcg_temp_local_new();
4836
    TCGv t2 = tcg_temp_local_new();
4837
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4838
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4839
    tcg_gen_shl_tl(t1, t1, t2);
4840
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4841
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4842
    gen_load_spr(t0, SPR_MQ);
4843
    tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4844
    tcg_gen_br(l2);
4845
    gen_set_label(l1);
4846
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4847
    gen_load_spr(t2, SPR_MQ);
4848
    tcg_gen_andc_tl(t1, t2, t1);
4849
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4850
    gen_set_label(l2);
4851
    tcg_temp_free(t0);
4852
    tcg_temp_free(t1);
4853
    tcg_temp_free(t2);
4854
    if (unlikely(Rc(ctx->opcode) != 0))
4855
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4856
}
4857

    
4858
/* slq - slq. */
4859
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4860
{
4861
    int l1 = gen_new_label();
4862
    TCGv t0 = tcg_temp_new();
4863
    TCGv t1 = tcg_temp_new();
4864
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4865
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4866
    tcg_gen_subfi_tl(t1, 32, t1);
4867
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4868
    tcg_gen_or_tl(t1, t0, t1);
4869
    gen_store_spr(SPR_MQ, t1);
4870
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4871
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4872
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4873
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4874
    gen_set_label(l1);
4875
    tcg_temp_free(t0);
4876
    tcg_temp_free(t1);
4877
    if (unlikely(Rc(ctx->opcode) != 0))
4878
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4879
}
4880

    
4881
/* sraiq - sraiq. */
4882
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4883
{
4884
    int sh = SH(ctx->opcode);
4885
    int l1 = gen_new_label();
4886
    TCGv t0 = tcg_temp_new();
4887
    TCGv t1 = tcg_temp_new();
4888
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4889
    tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4890
    tcg_gen_or_tl(t0, t0, t1);
4891
    gen_store_spr(SPR_MQ, t0);
4892
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4893
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4894
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4895
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4896
    gen_set_label(l1);
4897
    tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4898
    tcg_temp_free(t0);
4899
    tcg_temp_free(t1);
4900
    if (unlikely(Rc(ctx->opcode) != 0))
4901
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4902
}
4903

    
4904
/* sraq - sraq. */
4905
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4906
{
4907
    int l1 = gen_new_label();
4908
    int l2 = gen_new_label();
4909
    TCGv t0 = tcg_temp_new();
4910
    TCGv t1 = tcg_temp_local_new();
4911
    TCGv t2 = tcg_temp_local_new();
4912
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4913
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4914
    tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4915
    tcg_gen_subfi_tl(t2, 32, t2);
4916
    tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4917
    tcg_gen_or_tl(t0, t0, t2);
4918
    gen_store_spr(SPR_MQ, t0);
4919
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4920
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4921
    tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4922
    tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4923
    gen_set_label(l1);
4924
    tcg_temp_free(t0);
4925
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4926
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4927
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4928
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4929
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4930
    gen_set_label(l2);
4931
    tcg_temp_free(t1);
4932
    tcg_temp_free(t2);
4933
    if (unlikely(Rc(ctx->opcode) != 0))
4934
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4935
}
4936

    
4937
/* sre - sre. */
4938