Revision 21d2beaa

b/target-alpha/cpu.h
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uint64_t cpu_alpha_load_fpcr (CPUState *env);
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void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
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extern void swap_shadow_regs(CPUState *env);
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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                                        target_ulong *cs_base, int *flags)
b/target-alpha/helper.c
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    return 1;
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}
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#else
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void swap_shadow_regs(CPUState *env)
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{
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    uint64_t i0, i1, i2, i3, i4, i5, i6, i7;
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    i0 = env->ir[8];
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    i1 = env->ir[9];
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    i2 = env->ir[10];
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    i3 = env->ir[11];
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    i4 = env->ir[12];
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    i5 = env->ir[13];
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    i6 = env->ir[14];
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    i7 = env->ir[25];
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    env->ir[8]  = env->shadow[0];
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    env->ir[9]  = env->shadow[1];
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    env->ir[10] = env->shadow[2];
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    env->ir[11] = env->shadow[3];
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    env->ir[12] = env->shadow[4];
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    env->ir[13] = env->shadow[5];
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    env->ir[14] = env->shadow[6];
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    env->ir[25] = env->shadow[7];
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    env->shadow[0] = i0;
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    env->shadow[1] = i1;
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    env->shadow[2] = i2;
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    env->shadow[3] = i3;
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    env->shadow[4] = i4;
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    env->shadow[5] = i5;
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    env->shadow[6] = i6;
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    env->shadow[7] = i7;
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}
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target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
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{
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    return -1;
......
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    env->pc = env->palbr + i;
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    /* Switch to PALmode.  */
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    env->pal_mode = 1;
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    if (!env->pal_mode) {
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        env->pal_mode = 1;
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        swap_shadow_regs(env);
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    }
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#endif /* !USER_ONLY */
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}
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b/target-alpha/op_helper.c
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void helper_hw_ret (uint64_t a)
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{
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    env->pc = a & ~3;
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    env->pal_mode = a & 1;
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    env->intr_flag = 0;
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    env->lock_addr = -1;
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    if ((a & 1) == 0) {
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        env->pal_mode = 0;
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        swap_shadow_regs(env);
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    }
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}
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#endif
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