Archipelago » qemu

#define DPRINTF(fmt, args...) \

do { printf("ESP: " fmt , ##args); } while (0)

#else

#endif

#define ESP_REGS 16

    int32_t ti_size;

    uint32_t ti_rptr, ti_wptr;

    uint8_t ti_buf[TI_BUFSZ];

    SCSIDevice *scsi_dev[ESP_MAX_DEVS];

    SCSIDevice *current_dev;

    uint8_t cmdbuf[TI_BUFSZ];

    /* The amount of data left in the current DMA transfer.  */

    uint32_t dma_left;

    }

}

{

    uint32_t dmalen;

    int target;

    return ret;

}

                                             uint32_t pte)

{

    uint32_t tmppte;

            iommu_bad_addr(opaque, page, is_write);

            return;

        }

        if (is_write) {

            if (!(flags & IOPTE_WRITE)) {

                iommu_bad_addr(opaque, page, is_write);

static void slavio_misc_save(QEMUFile *f, void *opaque)

{

    MiscState *s = opaque;

    uint8_t tmp8;

    qemu_put_be32s(f, &tmp); /* ignored, was IRQ.  */

    qemu_put_8s(f, &s->config);

    qemu_put_8s(f, &s->aux1);

static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)

{

    MiscState *s = opaque;

    uint8_t tmp8;

    if (version_id != 1)

#define SERIAL_REGS 16

typedef struct ChannelState {

    qemu_irq irq;

    chn_id_t chn; // this channel, A (base+4) or B (base+0)

    chn_type_t type;

    struct ChannelState *otherchn;

static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)

{

    qemu_put_be32s(f, &tmp); /* unused, was IRQ.  */

    qemu_put_be32s(f, &s->reg);

    qemu_put_be32s(f, &s->rxint);

static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id)

{

    if (version_id > 2)

        return -EINVAL;

#define DPRINTF(fmt, args...) \

do { printf("TIMER: " fmt , ##args); } while (0)

#else

#endif

/*

    uint32_t count, counthigh, reached;

    uint64_t limit;

    // processor only

    struct SLAVIO_TIMERState *master;

    // system only

    struct SLAVIO_TIMERState *slave[MAX_CPUS];

    uint32_t slave_mode;

} SLAVIO_TIMERState;

static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,

                                            qemu_irq irq,

                                            SLAVIO_TIMERState *master,

{

    int slavio_timer_io_memory;

    SLAVIO_TIMERState *s;

#include "boards.h"

#include "firmware_abi.h"

#include "scsi.h"

//#define DEBUG_IRQ

    const char * const default_cpu_model;

};

int DMA_get_channel_mode (int nchan)

{

    return 0;

static void *slavio_intctl;

{

    if (slavio_intctl)

        slavio_pic_info(slavio_intctl);

}

{

    if (slavio_intctl)

        slavio_irq_info(slavio_intctl);

}

static unsigned long sun4m_load_kernel(const char *kernel_filename,

                                       const char *initrd_filename)

{

    int linux_boot;

    int ret;

    char buf[1024];

    BlockDriverState *fd[MAX_FD];

    /* init CPUs */

    if (!cpu_model)

    if (hwdef->fd_base != (target_phys_addr_t)-1) {

        /* there is zero or one floppy drive */

        memset(fd, 0, sizeof(fd));

        sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,

                          fdc_tc);

                        espdma, *espdma_irq, esp_reset);

    for (i = 0; i < ESP_MAX_DEVS; i++) {

            continue;

    }

    if (hwdef->cs_base != (target_phys_addr_t)-1)

        cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);

    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,

               boot_device, RAM_size, kernel_size, graphic_width,

    int ret;

    char buf[1024];

    BlockDriverState *fd[MAX_FD];

    /* init CPU */

    if (!cpu_model)

    if (hwdef->fd_base != (target_phys_addr_t)-1) {

        /* there is zero or one floppy drive */

        fd[1] = fd[0] = NULL;

        sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,

                          fdc_tc);

                        espdma, *espdma_irq, esp_reset);

    for (i = 0; i < ESP_MAX_DEVS; i++) {

            continue;

    }

    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,

               boot_device, RAM_size, kernel_size, graphic_width,

    unsigned long prom_offset, kernel_size;

    int ret;

    char buf[1024];

    /* init CPUs */

    if (!cpu_model)

                        espdma, *espdma_irq, esp_reset);

    for (i = 0; i < ESP_MAX_DEVS; i++) {

            continue;

    }

    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,

               boot_device, RAM_size, kernel_size, graphic_width,

/* sun4c_intctl.c */

void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,

                        qemu_irq *parent_irq);

/* slavio_timer.c */

void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,

#define NVRAM_SIZE           0x2000

#define MAX_IDE_BUS          2

int DMA_get_channel_mode (int nchan)

{

    return 0;

    return 0;

}

{

}

{

}

    ptimer_run(env->hstick, 0);

}

{

    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);

}

{

    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);

}

{

    CPUState *env = opaque;

static fdctrl_t *floppy_controller;

/* Sun4u hardware initialisation */

                       const char *boot_devices, DisplayState *ds,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

    PCIBus *pci_bus;

    QEMUBH *bh;

    qemu_irq *irq;

    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];

    BlockDriverState *fd[MAX_FD];

    main_cpu_reset(env);

    /* allocate RAM */

    cpu_register_physical_memory(PROM_ADDR,

                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,

                                 prom_offset | IO_MEM_ROM);

    }

    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);

    isa_mem_base = VGA_BASE;

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {

        if (serial_hds[i]) {

        exit(1);

    }

    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {

       else

           hd[i] = NULL;

    }

    /* FIXME: wire up interrupts.  */

    i8042_init(NULL/*1*/, NULL/*12*/, 0x60);

    for(i = 0; i < MAX_FD; i++) {

       else

           fd[i] = NULL;

    }

    floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);

    nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);

                         KERNEL_LOAD_ADDR, kernel_size,

                         kernel_cmdline,

                         INITRD_LOAD_ADDR, initrd_size,

    }

}

                              ram_addr_t cpage)

{

    int ret;

    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,

            page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {

            if (y_start < 0)

                y_start = y;

            if (page < page_min)

#define MMU_KERNEL_IDX 1

#define MMU_HYPV_IDX   2

{

#if defined(CONFIG_USER_ONLY)

    return MMU_USER_IDX;

#elif !defined(TARGET_SPARC64)

#else

        return MMU_USER_IDX;

        return MMU_KERNEL_IDX;

    else

        return MMU_HYPV_IDX;

#endif

}

{

#if defined(CONFIG_USER_ONLY)

    return 1;

#elif !defined(TARGET_SPARC64)

#else

#endif

}

#include "cpu.h"

#include "exec-all.h"

static inline void env_to_regs(void)

{

#if defined(reg_REGWPTR)

{

}

                               int mmu_idx, int is_softmmu);

        return 0;

        return 0;

    }

    return EXCP_HALTED;

#include "cpu.h"

#include "exec-all.h"

#include "qemu-common.h"

//#define DEBUG_MMU

//#define DEBUG_FEATURES

typedef struct sparc_def_t sparc_def_t;

struct sparc_def_t {

    target_ulong iu_version;

    uint32_t fpu_version;

    uint32_t mmu_version;

    uint32_t features;

};

/* Sparc MMU emulation */

#if defined(CONFIG_USER_ONLY)

                               int mmu_idx, int is_softmmu)

{

    if (rw & 2)

    else

    return 1;

}

 * UltraSparc IIi I/DMMUs

 */

static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,

{

    target_ulong mask;

    unsigned int i;

}

static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,

{

    target_ulong mask;

    unsigned int i;

    int is_user = mmu_idx == MMU_USER_IDX;

    if (rw == 2)

    else

}

/* Perform address translation */

    fprintf(stderr, "CPU feature %s not found\n", flagname);

}

{

    unsigned int i;

    const sparc_def_t *def = NULL;

#undef F_HELPER_SDQ_0_0

#undef VIS_HELPER

#undef VIS_CMPHELPER

#define DPRINTF_MMU(fmt, args...) \

do { printf("MMU: " fmt , ##args); } while (0)

#else

#endif

#ifdef DEBUG_MXCC

#define DPRINTF_MXCC(fmt, args...) \

do { printf("MXCC: " fmt , ##args); } while (0)

#else

#endif

#ifdef DEBUG_ASI

#define DPRINTF_ASI(fmt, args...) \

do { printf("ASI: " fmt , ##args); } while (0)

#else

#endif

void raise_exception(int tt)

    uint32_t features;

} DisasContext;

// This function uses non-native bit order

#define GET_FIELD(X, FROM, TO) \

  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))