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/*
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* QEMU Sun4m & Sun4d & Sun4c System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sun4m.h" |
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#include "nvram.h" |
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#include "sparc32_dma.h" |
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#include "fdc.h" |
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#include "sysemu.h" |
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#include "net.h" |
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#include "boards.h" |
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#include "firmware_abi.h" |
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#include "scsi.h" |
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#include "pc.h" |
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#include "isa.h" |
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//#define DEBUG_IRQ
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/*
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* Sun4m architecture was used in the following machines:
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*
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* SPARCserver 6xxMP/xx
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* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
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* SPARCstation LX/ZX (4/30)
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* SPARCstation Voyager
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* SPARCstation 10/xx, SPARCserver 10/xx
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* SPARCstation 5, SPARCserver 5
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* Sun4d architecture was used in the following machines:
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*
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* Sun4c architecture was used in the following machines:
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* SPARCstation 1/1+, SPARCserver 1/1+
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* SPARCstation SLC
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* SPARCstation IPC
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* SPARCstation ELC
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* SPARCstation IPX
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, args...) \
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do { printf("CPUIRQ: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00004000 |
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#define CMDLINE_ADDR 0x007ff000 |
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#define INITRD_LOAD_ADDR 0x00800000 |
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#define PROM_SIZE_MAX (512 * 1024) |
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#define PROM_VADDR 0xffd00000 |
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#define PROM_FILENAME "openbios-sparc32" |
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// Control plane, 8-bit and 24-bit planes
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#define TCX_SIZE (9 * 1024 * 1024) |
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#define MAX_CPUS 16 |
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#define MAX_PILS 16 |
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struct hwdef {
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target_phys_addr_t iommu_base, slavio_base; |
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base, fd_base; |
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
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target_phys_addr_t ecc_base; |
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uint32_t ecc_version; |
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target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; |
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller
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// register bit numbers
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int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
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int machine_id; // For NVRAM |
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uint32_t iommu_version; |
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uint32_t intbit_to_level[32];
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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#define MAX_IOUNITS 5 |
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struct sun4d_hwdef {
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target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
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target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base; |
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target_phys_addr_t espdma_base, esp_base; |
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target_phys_addr_t ledma_base, le_base; |
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target_phys_addr_t tcx_base; |
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target_phys_addr_t sbi_base; |
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unsigned long vram_size, nvram_size; |
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// IRQ numbers are not PIL ones, but SBI register bit numbers
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int esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, me_irq;
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int machine_id; // For NVRAM |
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uint32_t iounit_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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int DMA_get_channel_mode (int nchan) |
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{ |
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return 0; |
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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void DMA_hold_DREQ (int nchan) {} |
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void DMA_release_DREQ (int nchan) {} |
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void DMA_schedule(int nchan) {} |
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void DMA_run (void) {} |
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void DMA_init (int high_page_enable) {} |
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void DMA_register_channel (int nchan, |
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DMA_transfer_handler transfer_handler, |
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void *opaque)
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{ |
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} |
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extern int nographic; |
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static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
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const char *boot_devices, ram_addr_t RAM_size, |
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uint32_t kernel_size, |
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int width, int height, int depth, |
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int machine_id, const char *arch) |
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{ |
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unsigned int i; |
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uint32_t start, end; |
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uint8_t image[0x1ff0];
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ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
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struct sparc_arch_cfg *sparc_header;
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image)); |
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// Try to match PPC NVRAM
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strcpy(header->struct_ident, "QEMU_BIOS");
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header->struct_version = cpu_to_be32(3); /* structure v3 */ |
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header->nvram_size = cpu_to_be16(0x2000);
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header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
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strcpy(header->arch, arch); |
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header->nb_cpus = smp_cpus & 0xff;
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header->RAM0_base = 0;
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header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
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strcpy(header->boot_devices, boot_devices); |
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header->nboot_devices = strlen(boot_devices) & 0xff;
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header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR); |
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header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
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if (cmdline) {
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strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
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header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
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header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
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} |
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// XXX add initrd_image, initrd_size
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header->width = cpu_to_be16(width); |
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header->height = cpu_to_be16(height); |
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header->depth = cpu_to_be16(depth); |
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if (nographic)
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header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
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header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
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// Architecture specific header
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start = sizeof(ohwcfg_v3_t);
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sparc_header = (struct sparc_arch_cfg *)&image[start];
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sparc_header->valid = 0;
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start += sizeof(struct sparc_arch_cfg); |
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM; |
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strcpy(part_header->name, "system");
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end = start + sizeof(struct OpenBIOS_nvpart_v1); |
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for (i = 0; i < nb_prom_envs; i++) |
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end = OpenBIOS_set_var(image, end, prom_envs[i]); |
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15); |
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OpenBIOS_finish_partition(part_header, end - start); |
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// free partition
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start = end; |
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE; |
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strcpy(part_header->name, "free");
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start); |
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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} |
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static void *slavio_intctl; |
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void pic_info(void) |
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{ |
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if (slavio_intctl)
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slavio_pic_info(slavio_intctl); |
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} |
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void irq_info(void) |
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{ |
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if (slavio_intctl)
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slavio_irq_info(slavio_intctl); |
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} |
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void cpu_check_irqs(CPUState *env)
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{ |
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if (env->pil_in && (env->interrupt_index == 0 || |
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i; |
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for (i = 15; i > 0; i--) { |
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if (env->pil_in & (1 << i)) { |
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i; |
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if (old_interrupt != env->interrupt_index) {
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DPRINTF("Set CPU IRQ %d\n", i);
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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break;
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} |
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} |
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
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DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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static void cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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CPUState *env = opaque; |
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if (level) {
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DPRINTF("Raise CPU IRQ %d\n", irq);
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env->halted = 0;
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env->pil_in |= 1 << irq;
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cpu_check_irqs(env); |
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} else {
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DPRINTF("Lower CPU IRQ %d\n", irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env); |
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} |
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} |
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static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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} |
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static void *slavio_misc; |
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void qemu_system_powerdown(void) |
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{ |
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slavio_set_power_fail(slavio_misc, 1);
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} |
299 |
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static void main_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 0;
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} |
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static void secondary_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 1;
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} |
315 |
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static unsigned long sun4m_load_kernel(const char *kernel_filename, |
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const char *initrd_filename) |
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{ |
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int linux_boot;
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unsigned int i; |
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long initrd_size, kernel_size;
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
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NULL);
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if (kernel_size < 0) |
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kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
331 |
if (kernel_size < 0) |
332 |
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
333 |
if (kernel_size < 0) { |
334 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
338 |
|
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/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
343 |
if (initrd_size < 0) { |
344 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
346 |
exit(1);
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} |
348 |
} |
349 |
if (initrd_size > 0) { |
350 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
351 |
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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== 0x48647253) { // HdrS |
353 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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break;
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} |
357 |
} |
358 |
} |
359 |
} |
360 |
return kernel_size;
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} |
362 |
|
363 |
static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, |
364 |
const char *boot_device, |
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DisplayState *ds, const char *kernel_filename, |
366 |
const char *kernel_cmdline, |
367 |
const char *initrd_filename, const char *cpu_model) |
368 |
|
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{ |
370 |
CPUState *env, *envs[MAX_CPUS]; |
371 |
unsigned int i; |
372 |
void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
373 |
qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
374 |
*espdma_irq, *ledma_irq; |
375 |
qemu_irq *esp_reset, *le_reset; |
376 |
qemu_irq *fdc_tc; |
377 |
unsigned long prom_offset, kernel_size; |
378 |
int ret;
|
379 |
char buf[1024]; |
380 |
BlockDriverState *fd[MAX_FD]; |
381 |
int drive_index;
|
382 |
|
383 |
/* init CPUs */
|
384 |
if (!cpu_model)
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385 |
cpu_model = hwdef->default_cpu_model; |
386 |
|
387 |
for(i = 0; i < smp_cpus; i++) { |
388 |
env = cpu_init(cpu_model); |
389 |
if (!env) {
|
390 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
391 |
exit(1);
|
392 |
} |
393 |
cpu_sparc_set_id(env, i); |
394 |
envs[i] = env; |
395 |
if (i == 0) { |
396 |
qemu_register_reset(main_cpu_reset, env); |
397 |
} else {
|
398 |
qemu_register_reset(secondary_cpu_reset, env); |
399 |
env->halted = 1;
|
400 |
} |
401 |
register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
402 |
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
403 |
env->prom_addr = hwdef->slavio_base; |
404 |
} |
405 |
|
406 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
407 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
408 |
|
409 |
|
410 |
/* allocate RAM */
|
411 |
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
412 |
fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
|
413 |
(unsigned int)(RAM_size / (1024 * 1024)), |
414 |
(unsigned int)(hwdef->max_mem / (1024 * 1024))); |
415 |
exit(1);
|
416 |
} |
417 |
cpu_register_physical_memory(0, RAM_size, 0); |
418 |
|
419 |
/* load boot prom */
|
420 |
prom_offset = RAM_size + hwdef->vram_size; |
421 |
cpu_register_physical_memory(hwdef->slavio_base, |
422 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
423 |
TARGET_PAGE_MASK, |
424 |
prom_offset | IO_MEM_ROM); |
425 |
|
426 |
if (bios_name == NULL) |
427 |
bios_name = PROM_FILENAME; |
428 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
429 |
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
430 |
if (ret < 0 || ret > PROM_SIZE_MAX) |
431 |
ret = load_image(buf, phys_ram_base + prom_offset); |
432 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
433 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
434 |
buf); |
435 |
exit(1);
|
436 |
} |
437 |
prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
438 |
|
439 |
/* set up devices */
|
440 |
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
441 |
hwdef->intctl_base + 0x10000ULL,
|
442 |
&hwdef->intbit_to_level[0],
|
443 |
&slavio_irq, &slavio_cpu_irq, |
444 |
cpu_irqs, |
445 |
hwdef->clock_irq); |
446 |
|
447 |
if (hwdef->idreg_base != (target_phys_addr_t)-1) { |
448 |
stl_raw(phys_ram_base + prom_offset, 0xfe810103);
|
449 |
|
450 |
cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t),
|
451 |
prom_offset | IO_MEM_ROM); |
452 |
} |
453 |
|
454 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
455 |
slavio_irq[hwdef->me_irq]); |
456 |
|
457 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
458 |
iommu, &espdma_irq, &esp_reset); |
459 |
|
460 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
461 |
slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
462 |
&le_reset); |
463 |
|
464 |
if (graphic_depth != 8 && graphic_depth != 24) { |
465 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
466 |
exit (1);
|
467 |
} |
468 |
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
469 |
hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
470 |
|
471 |
if (nd_table[0].model == NULL |
472 |
|| strcmp(nd_table[0].model, "lance") == 0) { |
473 |
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
474 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
475 |
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
476 |
exit (1);
|
477 |
} else {
|
478 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
479 |
exit (1);
|
480 |
} |
481 |
|
482 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
483 |
hwdef->nvram_size, 8);
|
484 |
|
485 |
slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], |
486 |
slavio_cpu_irq, smp_cpus); |
487 |
|
488 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
489 |
nographic); |
490 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
491 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
492 |
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
493 |
serial_hds[1], serial_hds[0]); |
494 |
|
495 |
slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, |
496 |
hwdef->aux1_base, hwdef->aux2_base, |
497 |
slavio_irq[hwdef->me_irq], envs[0],
|
498 |
&fdc_tc); |
499 |
|
500 |
if (hwdef->fd_base != (target_phys_addr_t)-1) { |
501 |
/* there is zero or one floppy drive */
|
502 |
memset(fd, 0, sizeof(fd)); |
503 |
drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
504 |
if (drive_index != -1) |
505 |
fd[0] = drives_table[drive_index].bdrv;
|
506 |
|
507 |
sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
508 |
fdc_tc); |
509 |
} |
510 |
|
511 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
512 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
513 |
exit(1);
|
514 |
} |
515 |
|
516 |
main_esp = esp_init(hwdef->esp_base, 2,
|
517 |
espdma_memory_read, espdma_memory_write, |
518 |
espdma, *espdma_irq, esp_reset); |
519 |
|
520 |
for (i = 0; i < ESP_MAX_DEVS; i++) { |
521 |
drive_index = drive_get_index(IF_SCSI, 0, i);
|
522 |
if (drive_index == -1) |
523 |
continue;
|
524 |
esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
525 |
} |
526 |
|
527 |
if (hwdef->cs_base != (target_phys_addr_t)-1) |
528 |
cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
529 |
|
530 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename); |
531 |
|
532 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
533 |
boot_device, RAM_size, kernel_size, graphic_width, |
534 |
graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
|
535 |
|
536 |
if (hwdef->ecc_base != (target_phys_addr_t)-1) |
537 |
ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
538 |
hwdef->ecc_version); |
539 |
} |
540 |
|
541 |
static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size, |
542 |
const char *boot_device, |
543 |
DisplayState *ds, const char *kernel_filename, |
544 |
const char *kernel_cmdline, |
545 |
const char *initrd_filename, const char *cpu_model) |
546 |
{ |
547 |
CPUState *env; |
548 |
unsigned int i; |
549 |
void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
550 |
qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; |
551 |
qemu_irq *esp_reset, *le_reset; |
552 |
qemu_irq *fdc_tc; |
553 |
unsigned long prom_offset, kernel_size; |
554 |
int ret;
|
555 |
char buf[1024]; |
556 |
BlockDriverState *fd[MAX_FD]; |
557 |
int drive_index;
|
558 |
|
559 |
/* init CPU */
|
560 |
if (!cpu_model)
|
561 |
cpu_model = hwdef->default_cpu_model; |
562 |
|
563 |
env = cpu_init(cpu_model); |
564 |
if (!env) {
|
565 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
566 |
exit(1);
|
567 |
} |
568 |
|
569 |
cpu_sparc_set_id(env, 0);
|
570 |
|
571 |
qemu_register_reset(main_cpu_reset, env); |
572 |
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
573 |
cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
574 |
env->prom_addr = hwdef->slavio_base; |
575 |
|
576 |
/* allocate RAM */
|
577 |
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
578 |
fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
|
579 |
(unsigned int)(RAM_size / (1024 * 1024)), |
580 |
(unsigned int)(hwdef->max_mem / (1024 * 1024))); |
581 |
exit(1);
|
582 |
} |
583 |
cpu_register_physical_memory(0, RAM_size, 0); |
584 |
|
585 |
/* load boot prom */
|
586 |
prom_offset = RAM_size + hwdef->vram_size; |
587 |
cpu_register_physical_memory(hwdef->slavio_base, |
588 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
589 |
TARGET_PAGE_MASK, |
590 |
prom_offset | IO_MEM_ROM); |
591 |
|
592 |
if (bios_name == NULL) |
593 |
bios_name = PROM_FILENAME; |
594 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
595 |
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
596 |
if (ret < 0 || ret > PROM_SIZE_MAX) |
597 |
ret = load_image(buf, phys_ram_base + prom_offset); |
598 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
599 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
600 |
buf); |
601 |
exit(1);
|
602 |
} |
603 |
prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
604 |
|
605 |
/* set up devices */
|
606 |
slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base, |
607 |
&slavio_irq, cpu_irqs); |
608 |
|
609 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
610 |
slavio_irq[hwdef->me_irq]); |
611 |
|
612 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
613 |
iommu, &espdma_irq, &esp_reset); |
614 |
|
615 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
616 |
slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
617 |
&le_reset); |
618 |
|
619 |
if (graphic_depth != 8 && graphic_depth != 24) { |
620 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
621 |
exit (1);
|
622 |
} |
623 |
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
624 |
hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
625 |
|
626 |
if (nd_table[0].model == NULL |
627 |
|| strcmp(nd_table[0].model, "lance") == 0) { |
628 |
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
629 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
630 |
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
631 |
exit (1);
|
632 |
} else {
|
633 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
634 |
exit (1);
|
635 |
} |
636 |
|
637 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
638 |
hwdef->nvram_size, 2);
|
639 |
|
640 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
641 |
nographic); |
642 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
643 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
644 |
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
645 |
serial_hds[1], serial_hds[0]); |
646 |
|
647 |
slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
|
648 |
hwdef->aux1_base, hwdef->aux2_base, |
649 |
slavio_irq[hwdef->me_irq], env, &fdc_tc); |
650 |
|
651 |
if (hwdef->fd_base != (target_phys_addr_t)-1) { |
652 |
/* there is zero or one floppy drive */
|
653 |
fd[1] = fd[0] = NULL; |
654 |
drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
655 |
if (drive_index != -1) |
656 |
fd[0] = drives_table[drive_index].bdrv;
|
657 |
|
658 |
sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
659 |
fdc_tc); |
660 |
} |
661 |
|
662 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
663 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
664 |
exit(1);
|
665 |
} |
666 |
|
667 |
main_esp = esp_init(hwdef->esp_base, 2,
|
668 |
espdma_memory_read, espdma_memory_write, |
669 |
espdma, *espdma_irq, esp_reset); |
670 |
|
671 |
for (i = 0; i < ESP_MAX_DEVS; i++) { |
672 |
drive_index = drive_get_index(IF_SCSI, 0, i);
|
673 |
if (drive_index == -1) |
674 |
continue;
|
675 |
esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
676 |
} |
677 |
|
678 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename); |
679 |
|
680 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
681 |
boot_device, RAM_size, kernel_size, graphic_width, |
682 |
graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
|
683 |
} |
684 |
|
685 |
static const struct hwdef hwdefs[] = { |
686 |
/* SS-5 */
|
687 |
{ |
688 |
.iommu_base = 0x10000000,
|
689 |
.tcx_base = 0x50000000,
|
690 |
.cs_base = 0x6c000000,
|
691 |
.slavio_base = 0x70000000,
|
692 |
.ms_kb_base = 0x71000000,
|
693 |
.serial_base = 0x71100000,
|
694 |
.nvram_base = 0x71200000,
|
695 |
.fd_base = 0x71400000,
|
696 |
.counter_base = 0x71d00000,
|
697 |
.intctl_base = 0x71e00000,
|
698 |
.idreg_base = 0x78000000,
|
699 |
.dma_base = 0x78400000,
|
700 |
.esp_base = 0x78800000,
|
701 |
.le_base = 0x78c00000,
|
702 |
.apc_base = 0x6a000000,
|
703 |
.aux1_base = 0x71900000,
|
704 |
.aux2_base = 0x71910000,
|
705 |
.ecc_base = -1,
|
706 |
.sun4c_intctl_base = -1,
|
707 |
.sun4c_counter_base = -1,
|
708 |
.vram_size = 0x00100000,
|
709 |
.nvram_size = 0x2000,
|
710 |
.esp_irq = 18,
|
711 |
.le_irq = 16,
|
712 |
.clock_irq = 7,
|
713 |
.clock1_irq = 19,
|
714 |
.ms_kb_irq = 14,
|
715 |
.ser_irq = 15,
|
716 |
.fd_irq = 22,
|
717 |
.me_irq = 30,
|
718 |
.cs_irq = 5,
|
719 |
.machine_id = 0x80,
|
720 |
.iommu_version = 0x05000000,
|
721 |
.intbit_to_level = { |
722 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
723 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
724 |
}, |
725 |
.max_mem = 0x10000000,
|
726 |
.default_cpu_model = "Fujitsu MB86904",
|
727 |
}, |
728 |
/* SS-10 */
|
729 |
{ |
730 |
.iommu_base = 0xfe0000000ULL,
|
731 |
.tcx_base = 0xe20000000ULL,
|
732 |
.cs_base = -1,
|
733 |
.slavio_base = 0xff0000000ULL,
|
734 |
.ms_kb_base = 0xff1000000ULL,
|
735 |
.serial_base = 0xff1100000ULL,
|
736 |
.nvram_base = 0xff1200000ULL,
|
737 |
.fd_base = 0xff1700000ULL,
|
738 |
.counter_base = 0xff1300000ULL,
|
739 |
.intctl_base = 0xff1400000ULL,
|
740 |
.idreg_base = 0xef0000000ULL,
|
741 |
.dma_base = 0xef0400000ULL,
|
742 |
.esp_base = 0xef0800000ULL,
|
743 |
.le_base = 0xef0c00000ULL,
|
744 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
745 |
.aux1_base = 0xff1800000ULL,
|
746 |
.aux2_base = 0xff1a01000ULL,
|
747 |
.ecc_base = 0xf00000000ULL,
|
748 |
.ecc_version = 0x10000000, // version 0, implementation 1 |
749 |
.sun4c_intctl_base = -1,
|
750 |
.sun4c_counter_base = -1,
|
751 |
.vram_size = 0x00100000,
|
752 |
.nvram_size = 0x2000,
|
753 |
.esp_irq = 18,
|
754 |
.le_irq = 16,
|
755 |
.clock_irq = 7,
|
756 |
.clock1_irq = 19,
|
757 |
.ms_kb_irq = 14,
|
758 |
.ser_irq = 15,
|
759 |
.fd_irq = 22,
|
760 |
.me_irq = 30,
|
761 |
.cs_irq = -1,
|
762 |
.ecc_irq = 28,
|
763 |
.machine_id = 0x72,
|
764 |
.iommu_version = 0x03000000,
|
765 |
.intbit_to_level = { |
766 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
767 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
768 |
}, |
769 |
.max_mem = 0xf00000000ULL,
|
770 |
.default_cpu_model = "TI SuperSparc II",
|
771 |
}, |
772 |
/* SS-600MP */
|
773 |
{ |
774 |
.iommu_base = 0xfe0000000ULL,
|
775 |
.tcx_base = 0xe20000000ULL,
|
776 |
.cs_base = -1,
|
777 |
.slavio_base = 0xff0000000ULL,
|
778 |
.ms_kb_base = 0xff1000000ULL,
|
779 |
.serial_base = 0xff1100000ULL,
|
780 |
.nvram_base = 0xff1200000ULL,
|
781 |
.fd_base = -1,
|
782 |
.counter_base = 0xff1300000ULL,
|
783 |
.intctl_base = 0xff1400000ULL,
|
784 |
.idreg_base = -1,
|
785 |
.dma_base = 0xef0081000ULL,
|
786 |
.esp_base = 0xef0080000ULL,
|
787 |
.le_base = 0xef0060000ULL,
|
788 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
789 |
.aux1_base = 0xff1800000ULL,
|
790 |
.aux2_base = 0xff1a01000ULL, // XXX should not exist |
791 |
.ecc_base = 0xf00000000ULL,
|
792 |
.ecc_version = 0x00000000, // version 0, implementation 0 |
793 |
.sun4c_intctl_base = -1,
|
794 |
.sun4c_counter_base = -1,
|
795 |
.vram_size = 0x00100000,
|
796 |
.nvram_size = 0x2000,
|
797 |
.esp_irq = 18,
|
798 |
.le_irq = 16,
|
799 |
.clock_irq = 7,
|
800 |
.clock1_irq = 19,
|
801 |
.ms_kb_irq = 14,
|
802 |
.ser_irq = 15,
|
803 |
.fd_irq = 22,
|
804 |
.me_irq = 30,
|
805 |
.cs_irq = -1,
|
806 |
.ecc_irq = 28,
|
807 |
.machine_id = 0x71,
|
808 |
.iommu_version = 0x01000000,
|
809 |
.intbit_to_level = { |
810 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
811 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
812 |
}, |
813 |
.max_mem = 0xf00000000ULL,
|
814 |
.default_cpu_model = "TI SuperSparc II",
|
815 |
}, |
816 |
/* SS-20 */
|
817 |
{ |
818 |
.iommu_base = 0xfe0000000ULL,
|
819 |
.tcx_base = 0xe20000000ULL,
|
820 |
.cs_base = -1,
|
821 |
.slavio_base = 0xff0000000ULL,
|
822 |
.ms_kb_base = 0xff1000000ULL,
|
823 |
.serial_base = 0xff1100000ULL,
|
824 |
.nvram_base = 0xff1200000ULL,
|
825 |
.fd_base = 0xff1700000ULL,
|
826 |
.counter_base = 0xff1300000ULL,
|
827 |
.intctl_base = 0xff1400000ULL,
|
828 |
.idreg_base = 0xef0000000ULL,
|
829 |
.dma_base = 0xef0400000ULL,
|
830 |
.esp_base = 0xef0800000ULL,
|
831 |
.le_base = 0xef0c00000ULL,
|
832 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
833 |
.aux1_base = 0xff1800000ULL,
|
834 |
.aux2_base = 0xff1a01000ULL,
|
835 |
.ecc_base = 0xf00000000ULL,
|
836 |
.ecc_version = 0x20000000, // version 0, implementation 2 |
837 |
.sun4c_intctl_base = -1,
|
838 |
.sun4c_counter_base = -1,
|
839 |
.vram_size = 0x00100000,
|
840 |
.nvram_size = 0x2000,
|
841 |
.esp_irq = 18,
|
842 |
.le_irq = 16,
|
843 |
.clock_irq = 7,
|
844 |
.clock1_irq = 19,
|
845 |
.ms_kb_irq = 14,
|
846 |
.ser_irq = 15,
|
847 |
.fd_irq = 22,
|
848 |
.me_irq = 30,
|
849 |
.cs_irq = -1,
|
850 |
.ecc_irq = 28,
|
851 |
.machine_id = 0x72,
|
852 |
.iommu_version = 0x13000000,
|
853 |
.intbit_to_level = { |
854 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
855 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
856 |
}, |
857 |
.max_mem = 0xf00000000ULL,
|
858 |
.default_cpu_model = "TI SuperSparc II",
|
859 |
}, |
860 |
/* SS-2 */
|
861 |
{ |
862 |
.iommu_base = 0xf8000000,
|
863 |
.tcx_base = 0xfe000000,
|
864 |
.cs_base = -1,
|
865 |
.slavio_base = 0xf6000000,
|
866 |
.ms_kb_base = 0xf0000000,
|
867 |
.serial_base = 0xf1000000,
|
868 |
.nvram_base = 0xf2000000,
|
869 |
.fd_base = 0xf7200000,
|
870 |
.counter_base = -1,
|
871 |
.intctl_base = -1,
|
872 |
.dma_base = 0xf8400000,
|
873 |
.esp_base = 0xf8800000,
|
874 |
.le_base = 0xf8c00000,
|
875 |
.apc_base = -1,
|
876 |
.aux1_base = 0xf7400003,
|
877 |
.aux2_base = -1,
|
878 |
.sun4c_intctl_base = 0xf5000000,
|
879 |
.sun4c_counter_base = 0xf3000000,
|
880 |
.vram_size = 0x00100000,
|
881 |
.nvram_size = 0x800,
|
882 |
.esp_irq = 2,
|
883 |
.le_irq = 3,
|
884 |
.clock_irq = 5,
|
885 |
.clock1_irq = 7,
|
886 |
.ms_kb_irq = 1,
|
887 |
.ser_irq = 1,
|
888 |
.fd_irq = 1,
|
889 |
.me_irq = 1,
|
890 |
.cs_irq = -1,
|
891 |
.machine_id = 0x55,
|
892 |
.max_mem = 0x10000000,
|
893 |
.default_cpu_model = "Cypress CY7C601",
|
894 |
}, |
895 |
/* Voyager */
|
896 |
{ |
897 |
.iommu_base = 0x10000000,
|
898 |
.tcx_base = 0x50000000,
|
899 |
.cs_base = -1,
|
900 |
.slavio_base = 0x70000000,
|
901 |
.ms_kb_base = 0x71000000,
|
902 |
.serial_base = 0x71100000,
|
903 |
.nvram_base = 0x71200000,
|
904 |
.fd_base = 0x71400000,
|
905 |
.counter_base = 0x71d00000,
|
906 |
.intctl_base = 0x71e00000,
|
907 |
.idreg_base = 0x78000000,
|
908 |
.dma_base = 0x78400000,
|
909 |
.esp_base = 0x78800000,
|
910 |
.le_base = 0x78c00000,
|
911 |
.apc_base = 0x71300000, // pmc |
912 |
.aux1_base = 0x71900000,
|
913 |
.aux2_base = 0x71910000,
|
914 |
.ecc_base = -1,
|
915 |
.sun4c_intctl_base = -1,
|
916 |
.sun4c_counter_base = -1,
|
917 |
.vram_size = 0x00100000,
|
918 |
.nvram_size = 0x2000,
|
919 |
.esp_irq = 18,
|
920 |
.le_irq = 16,
|
921 |
.clock_irq = 7,
|
922 |
.clock1_irq = 19,
|
923 |
.ms_kb_irq = 14,
|
924 |
.ser_irq = 15,
|
925 |
.fd_irq = 22,
|
926 |
.me_irq = 30,
|
927 |
.cs_irq = -1,
|
928 |
.machine_id = 0x80,
|
929 |
.iommu_version = 0x05000000,
|
930 |
.intbit_to_level = { |
931 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
932 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
933 |
}, |
934 |
.max_mem = 0x10000000,
|
935 |
.default_cpu_model = "Fujitsu MB86904",
|
936 |
}, |
937 |
/* LX */
|
938 |
{ |
939 |
.iommu_base = 0x10000000,
|
940 |
.tcx_base = 0x50000000,
|
941 |
.cs_base = -1,
|
942 |
.slavio_base = 0x70000000,
|
943 |
.ms_kb_base = 0x71000000,
|
944 |
.serial_base = 0x71100000,
|
945 |
.nvram_base = 0x71200000,
|
946 |
.fd_base = 0x71400000,
|
947 |
.counter_base = 0x71d00000,
|
948 |
.intctl_base = 0x71e00000,
|
949 |
.idreg_base = 0x78000000,
|
950 |
.dma_base = 0x78400000,
|
951 |
.esp_base = 0x78800000,
|
952 |
.le_base = 0x78c00000,
|
953 |
.apc_base = -1,
|
954 |
.aux1_base = 0x71900000,
|
955 |
.aux2_base = 0x71910000,
|
956 |
.ecc_base = -1,
|
957 |
.sun4c_intctl_base = -1,
|
958 |
.sun4c_counter_base = -1,
|
959 |
.vram_size = 0x00100000,
|
960 |
.nvram_size = 0x2000,
|
961 |
.esp_irq = 18,
|
962 |
.le_irq = 16,
|
963 |
.clock_irq = 7,
|
964 |
.clock1_irq = 19,
|
965 |
.ms_kb_irq = 14,
|
966 |
.ser_irq = 15,
|
967 |
.fd_irq = 22,
|
968 |
.me_irq = 30,
|
969 |
.cs_irq = -1,
|
970 |
.machine_id = 0x80,
|
971 |
.iommu_version = 0x04000000,
|
972 |
.intbit_to_level = { |
973 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
974 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
975 |
}, |
976 |
.max_mem = 0x10000000,
|
977 |
.default_cpu_model = "TI MicroSparc I",
|
978 |
}, |
979 |
/* SS-4 */
|
980 |
{ |
981 |
.iommu_base = 0x10000000,
|
982 |
.tcx_base = 0x50000000,
|
983 |
.cs_base = 0x6c000000,
|
984 |
.slavio_base = 0x70000000,
|
985 |
.ms_kb_base = 0x71000000,
|
986 |
.serial_base = 0x71100000,
|
987 |
.nvram_base = 0x71200000,
|
988 |
.fd_base = 0x71400000,
|
989 |
.counter_base = 0x71d00000,
|
990 |
.intctl_base = 0x71e00000,
|
991 |
.idreg_base = 0x78000000,
|
992 |
.dma_base = 0x78400000,
|
993 |
.esp_base = 0x78800000,
|
994 |
.le_base = 0x78c00000,
|
995 |
.apc_base = 0x6a000000,
|
996 |
.aux1_base = 0x71900000,
|
997 |
.aux2_base = 0x71910000,
|
998 |
.ecc_base = -1,
|
999 |
.sun4c_intctl_base = -1,
|
1000 |
.sun4c_counter_base = -1,
|
1001 |
.vram_size = 0x00100000,
|
1002 |
.nvram_size = 0x2000,
|
1003 |
.esp_irq = 18,
|
1004 |
.le_irq = 16,
|
1005 |
.clock_irq = 7,
|
1006 |
.clock1_irq = 19,
|
1007 |
.ms_kb_irq = 14,
|
1008 |
.ser_irq = 15,
|
1009 |
.fd_irq = 22,
|
1010 |
.me_irq = 30,
|
1011 |
.cs_irq = 5,
|
1012 |
.machine_id = 0x80,
|
1013 |
.iommu_version = 0x05000000,
|
1014 |
.intbit_to_level = { |
1015 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1016 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1017 |
}, |
1018 |
.max_mem = 0x10000000,
|
1019 |
.default_cpu_model = "Fujitsu MB86904",
|
1020 |
}, |
1021 |
/* SPARCClassic */
|
1022 |
{ |
1023 |
.iommu_base = 0x10000000,
|
1024 |
.tcx_base = 0x50000000,
|
1025 |
.cs_base = -1,
|
1026 |
.slavio_base = 0x70000000,
|
1027 |
.ms_kb_base = 0x71000000,
|
1028 |
.serial_base = 0x71100000,
|
1029 |
.nvram_base = 0x71200000,
|
1030 |
.fd_base = 0x71400000,
|
1031 |
.counter_base = 0x71d00000,
|
1032 |
.intctl_base = 0x71e00000,
|
1033 |
.idreg_base = 0x78000000,
|
1034 |
.dma_base = 0x78400000,
|
1035 |
.esp_base = 0x78800000,
|
1036 |
.le_base = 0x78c00000,
|
1037 |
.apc_base = 0x6a000000,
|
1038 |
.aux1_base = 0x71900000,
|
1039 |
.aux2_base = 0x71910000,
|
1040 |
.ecc_base = -1,
|
1041 |
.sun4c_intctl_base = -1,
|
1042 |
.sun4c_counter_base = -1,
|
1043 |
.vram_size = 0x00100000,
|
1044 |
.nvram_size = 0x2000,
|
1045 |
.esp_irq = 18,
|
1046 |
.le_irq = 16,
|
1047 |
.clock_irq = 7,
|
1048 |
.clock1_irq = 19,
|
1049 |
.ms_kb_irq = 14,
|
1050 |
.ser_irq = 15,
|
1051 |
.fd_irq = 22,
|
1052 |
.me_irq = 30,
|
1053 |
.cs_irq = -1,
|
1054 |
.machine_id = 0x80,
|
1055 |
.iommu_version = 0x05000000,
|
1056 |
.intbit_to_level = { |
1057 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1058 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1059 |
}, |
1060 |
.max_mem = 0x10000000,
|
1061 |
.default_cpu_model = "TI MicroSparc I",
|
1062 |
}, |
1063 |
/* SPARCbook */
|
1064 |
{ |
1065 |
.iommu_base = 0x10000000,
|
1066 |
.tcx_base = 0x50000000, // XXX |
1067 |
.cs_base = -1,
|
1068 |
.slavio_base = 0x70000000,
|
1069 |
.ms_kb_base = 0x71000000,
|
1070 |
.serial_base = 0x71100000,
|
1071 |
.nvram_base = 0x71200000,
|
1072 |
.fd_base = 0x71400000,
|
1073 |
.counter_base = 0x71d00000,
|
1074 |
.intctl_base = 0x71e00000,
|
1075 |
.idreg_base = 0x78000000,
|
1076 |
.dma_base = 0x78400000,
|
1077 |
.esp_base = 0x78800000,
|
1078 |
.le_base = 0x78c00000,
|
1079 |
.apc_base = 0x6a000000,
|
1080 |
.aux1_base = 0x71900000,
|
1081 |
.aux2_base = 0x71910000,
|
1082 |
.ecc_base = -1,
|
1083 |
.sun4c_intctl_base = -1,
|
1084 |
.sun4c_counter_base = -1,
|
1085 |
.vram_size = 0x00100000,
|
1086 |
.nvram_size = 0x2000,
|
1087 |
.esp_irq = 18,
|
1088 |
.le_irq = 16,
|
1089 |
.clock_irq = 7,
|
1090 |
.clock1_irq = 19,
|
1091 |
.ms_kb_irq = 14,
|
1092 |
.ser_irq = 15,
|
1093 |
.fd_irq = 22,
|
1094 |
.me_irq = 30,
|
1095 |
.cs_irq = -1,
|
1096 |
.machine_id = 0x80,
|
1097 |
.iommu_version = 0x05000000,
|
1098 |
.intbit_to_level = { |
1099 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1100 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1101 |
}, |
1102 |
.max_mem = 0x10000000,
|
1103 |
.default_cpu_model = "TI MicroSparc I",
|
1104 |
}, |
1105 |
}; |
1106 |
|
1107 |
/* SPARCstation 5 hardware initialisation */
|
1108 |
static void ss5_init(ram_addr_t RAM_size, int vga_ram_size, |
1109 |
const char *boot_device, DisplayState *ds, |
1110 |
const char *kernel_filename, const char *kernel_cmdline, |
1111 |
const char *initrd_filename, const char *cpu_model) |
1112 |
{ |
1113 |
sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
1114 |
kernel_cmdline, initrd_filename, cpu_model); |
1115 |
} |
1116 |
|
1117 |
/* SPARCstation 10 hardware initialisation */
|
1118 |
static void ss10_init(ram_addr_t RAM_size, int vga_ram_size, |
1119 |
const char *boot_device, DisplayState *ds, |
1120 |
const char *kernel_filename, const char *kernel_cmdline, |
1121 |
const char *initrd_filename, const char *cpu_model) |
1122 |
{ |
1123 |
sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
1124 |
kernel_cmdline, initrd_filename, cpu_model); |
1125 |
} |
1126 |
|
1127 |
/* SPARCserver 600MP hardware initialisation */
|
1128 |
static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size, |
1129 |
const char *boot_device, DisplayState *ds, |
1130 |
const char *kernel_filename, const char *kernel_cmdline, |
1131 |
const char *initrd_filename, const char *cpu_model) |
1132 |
{ |
1133 |
sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
|
1134 |
kernel_cmdline, initrd_filename, cpu_model); |
1135 |
} |
1136 |
|
1137 |
/* SPARCstation 20 hardware initialisation */
|
1138 |
static void ss20_init(ram_addr_t RAM_size, int vga_ram_size, |
1139 |
const char *boot_device, DisplayState *ds, |
1140 |
const char *kernel_filename, const char *kernel_cmdline, |
1141 |
const char *initrd_filename, const char *cpu_model) |
1142 |
{ |
1143 |
sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
|
1144 |
kernel_cmdline, initrd_filename, cpu_model); |
1145 |
} |
1146 |
|
1147 |
/* SPARCstation 2 hardware initialisation */
|
1148 |
static void ss2_init(ram_addr_t RAM_size, int vga_ram_size, |
1149 |
const char *boot_device, DisplayState *ds, |
1150 |
const char *kernel_filename, const char *kernel_cmdline, |
1151 |
const char *initrd_filename, const char *cpu_model) |
1152 |
{ |
1153 |
sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
|
1154 |
kernel_cmdline, initrd_filename, cpu_model); |
1155 |
} |
1156 |
|
1157 |
/* SPARCstation Voyager hardware initialisation */
|
1158 |
static void vger_init(ram_addr_t RAM_size, int vga_ram_size, |
1159 |
const char *boot_device, DisplayState *ds, |
1160 |
const char *kernel_filename, const char *kernel_cmdline, |
1161 |
const char *initrd_filename, const char *cpu_model) |
1162 |
{ |
1163 |
sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
|
1164 |
kernel_cmdline, initrd_filename, cpu_model); |
1165 |
} |
1166 |
|
1167 |
/* SPARCstation LX hardware initialisation */
|
1168 |
static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size, |
1169 |
const char *boot_device, DisplayState *ds, |
1170 |
const char *kernel_filename, const char *kernel_cmdline, |
1171 |
const char *initrd_filename, const char *cpu_model) |
1172 |
{ |
1173 |
sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
|
1174 |
kernel_cmdline, initrd_filename, cpu_model); |
1175 |
} |
1176 |
|
1177 |
/* SPARCstation 4 hardware initialisation */
|
1178 |
static void ss4_init(ram_addr_t RAM_size, int vga_ram_size, |
1179 |
const char *boot_device, DisplayState *ds, |
1180 |
const char *kernel_filename, const char *kernel_cmdline, |
1181 |
const char *initrd_filename, const char *cpu_model) |
1182 |
{ |
1183 |
sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
|
1184 |
kernel_cmdline, initrd_filename, cpu_model); |
1185 |
} |
1186 |
|
1187 |
/* SPARCClassic hardware initialisation */
|
1188 |
static void scls_init(ram_addr_t RAM_size, int vga_ram_size, |
1189 |
const char *boot_device, DisplayState *ds, |
1190 |
const char *kernel_filename, const char *kernel_cmdline, |
1191 |
const char *initrd_filename, const char *cpu_model) |
1192 |
{ |
1193 |
sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
|
1194 |
kernel_cmdline, initrd_filename, cpu_model); |
1195 |
} |
1196 |
|
1197 |
/* SPARCbook hardware initialisation */
|
1198 |
static void sbook_init(ram_addr_t RAM_size, int vga_ram_size, |
1199 |
const char *boot_device, DisplayState *ds, |
1200 |
const char *kernel_filename, const char *kernel_cmdline, |
1201 |
const char *initrd_filename, const char *cpu_model) |
1202 |
{ |
1203 |
sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
|
1204 |
kernel_cmdline, initrd_filename, cpu_model); |
1205 |
} |
1206 |
|
1207 |
QEMUMachine ss5_machine = { |
1208 |
"SS-5",
|
1209 |
"Sun4m platform, SPARCstation 5",
|
1210 |
ss5_init, |
1211 |
PROM_SIZE_MAX + TCX_SIZE, |
1212 |
}; |
1213 |
|
1214 |
QEMUMachine ss10_machine = { |
1215 |
"SS-10",
|
1216 |
"Sun4m platform, SPARCstation 10",
|
1217 |
ss10_init, |
1218 |
PROM_SIZE_MAX + TCX_SIZE, |
1219 |
}; |
1220 |
|
1221 |
QEMUMachine ss600mp_machine = { |
1222 |
"SS-600MP",
|
1223 |
"Sun4m platform, SPARCserver 600MP",
|
1224 |
ss600mp_init, |
1225 |
PROM_SIZE_MAX + TCX_SIZE, |
1226 |
}; |
1227 |
|
1228 |
QEMUMachine ss20_machine = { |
1229 |
"SS-20",
|
1230 |
"Sun4m platform, SPARCstation 20",
|
1231 |
ss20_init, |
1232 |
PROM_SIZE_MAX + TCX_SIZE, |
1233 |
}; |
1234 |
|
1235 |
QEMUMachine ss2_machine = { |
1236 |
"SS-2",
|
1237 |
"Sun4c platform, SPARCstation 2",
|
1238 |
ss2_init, |
1239 |
PROM_SIZE_MAX + TCX_SIZE, |
1240 |
}; |
1241 |
|
1242 |
QEMUMachine voyager_machine = { |
1243 |
"Voyager",
|
1244 |
"Sun4m platform, SPARCstation Voyager",
|
1245 |
vger_init, |
1246 |
PROM_SIZE_MAX + TCX_SIZE, |
1247 |
}; |
1248 |
|
1249 |
QEMUMachine ss_lx_machine = { |
1250 |
"LX",
|
1251 |
"Sun4m platform, SPARCstation LX",
|
1252 |
ss_lx_init, |
1253 |
PROM_SIZE_MAX + TCX_SIZE, |
1254 |
}; |
1255 |
|
1256 |
QEMUMachine ss4_machine = { |
1257 |
"SS-4",
|
1258 |
"Sun4m platform, SPARCstation 4",
|
1259 |
ss4_init, |
1260 |
PROM_SIZE_MAX + TCX_SIZE, |
1261 |
}; |
1262 |
|
1263 |
QEMUMachine scls_machine = { |
1264 |
"SPARCClassic",
|
1265 |
"Sun4m platform, SPARCClassic",
|
1266 |
scls_init, |
1267 |
PROM_SIZE_MAX + TCX_SIZE, |
1268 |
}; |
1269 |
|
1270 |
QEMUMachine sbook_machine = { |
1271 |
"SPARCbook",
|
1272 |
"Sun4m platform, SPARCbook",
|
1273 |
sbook_init, |
1274 |
PROM_SIZE_MAX + TCX_SIZE, |
1275 |
}; |
1276 |
|
1277 |
static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1278 |
/* SS-1000 */
|
1279 |
{ |
1280 |
.iounit_bases = { |
1281 |
0xfe0200000ULL,
|
1282 |
0xfe1200000ULL,
|
1283 |
0xfe2200000ULL,
|
1284 |
0xfe3200000ULL,
|
1285 |
-1,
|
1286 |
}, |
1287 |
.tcx_base = 0x820000000ULL,
|
1288 |
.slavio_base = 0xf00000000ULL,
|
1289 |
.ms_kb_base = 0xf00240000ULL,
|
1290 |
.serial_base = 0xf00200000ULL,
|
1291 |
.nvram_base = 0xf00280000ULL,
|
1292 |
.counter_base = 0xf00300000ULL,
|
1293 |
.espdma_base = 0x800081000ULL,
|
1294 |
.esp_base = 0x800080000ULL,
|
1295 |
.ledma_base = 0x800040000ULL,
|
1296 |
.le_base = 0x800060000ULL,
|
1297 |
.sbi_base = 0xf02800000ULL,
|
1298 |
.vram_size = 0x00100000,
|
1299 |
.nvram_size = 0x2000,
|
1300 |
.esp_irq = 3,
|
1301 |
.le_irq = 4,
|
1302 |
.clock_irq = 14,
|
1303 |
.clock1_irq = 10,
|
1304 |
.ms_kb_irq = 12,
|
1305 |
.ser_irq = 12,
|
1306 |
.machine_id = 0x80,
|
1307 |
.iounit_version = 0x03000000,
|
1308 |
.max_mem = 0xf00000000ULL,
|
1309 |
.default_cpu_model = "TI SuperSparc II",
|
1310 |
}, |
1311 |
/* SS-2000 */
|
1312 |
{ |
1313 |
.iounit_bases = { |
1314 |
0xfe0200000ULL,
|
1315 |
0xfe1200000ULL,
|
1316 |
0xfe2200000ULL,
|
1317 |
0xfe3200000ULL,
|
1318 |
0xfe4200000ULL,
|
1319 |
}, |
1320 |
.tcx_base = 0x820000000ULL,
|
1321 |
.slavio_base = 0xf00000000ULL,
|
1322 |
.ms_kb_base = 0xf00240000ULL,
|
1323 |
.serial_base = 0xf00200000ULL,
|
1324 |
.nvram_base = 0xf00280000ULL,
|
1325 |
.counter_base = 0xf00300000ULL,
|
1326 |
.espdma_base = 0x800081000ULL,
|
1327 |
.esp_base = 0x800080000ULL,
|
1328 |
.ledma_base = 0x800040000ULL,
|
1329 |
.le_base = 0x800060000ULL,
|
1330 |
.sbi_base = 0xf02800000ULL,
|
1331 |
.vram_size = 0x00100000,
|
1332 |
.nvram_size = 0x2000,
|
1333 |
.esp_irq = 3,
|
1334 |
.le_irq = 4,
|
1335 |
.clock_irq = 14,
|
1336 |
.clock1_irq = 10,
|
1337 |
.ms_kb_irq = 12,
|
1338 |
.ser_irq = 12,
|
1339 |
.machine_id = 0x80,
|
1340 |
.iounit_version = 0x03000000,
|
1341 |
.max_mem = 0xf00000000ULL,
|
1342 |
.default_cpu_model = "TI SuperSparc II",
|
1343 |
}, |
1344 |
}; |
1345 |
|
1346 |
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1347 |
const char *boot_device, |
1348 |
DisplayState *ds, const char *kernel_filename, |
1349 |
const char *kernel_cmdline, |
1350 |
const char *initrd_filename, const char *cpu_model) |
1351 |
{ |
1352 |
CPUState *env, *envs[MAX_CPUS]; |
1353 |
unsigned int i; |
1354 |
void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
|
1355 |
qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, |
1356 |
*espdma_irq, *ledma_irq; |
1357 |
qemu_irq *esp_reset, *le_reset; |
1358 |
unsigned long prom_offset, kernel_size; |
1359 |
int ret;
|
1360 |
char buf[1024]; |
1361 |
int drive_index;
|
1362 |
|
1363 |
/* init CPUs */
|
1364 |
if (!cpu_model)
|
1365 |
cpu_model = hwdef->default_cpu_model; |
1366 |
|
1367 |
for (i = 0; i < smp_cpus; i++) { |
1368 |
env = cpu_init(cpu_model); |
1369 |
if (!env) {
|
1370 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
1371 |
exit(1);
|
1372 |
} |
1373 |
cpu_sparc_set_id(env, i); |
1374 |
envs[i] = env; |
1375 |
if (i == 0) { |
1376 |
qemu_register_reset(main_cpu_reset, env); |
1377 |
} else {
|
1378 |
qemu_register_reset(secondary_cpu_reset, env); |
1379 |
env->halted = 1;
|
1380 |
} |
1381 |
register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
1382 |
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
1383 |
env->prom_addr = hwdef->slavio_base; |
1384 |
} |
1385 |
|
1386 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
1387 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1388 |
|
1389 |
/* allocate RAM */
|
1390 |
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
1391 |
fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
|
1392 |
(unsigned int)(RAM_size / (1024 * 1024)), |
1393 |
(unsigned int)(hwdef->max_mem / (1024 * 1024))); |
1394 |
exit(1);
|
1395 |
} |
1396 |
cpu_register_physical_memory(0, RAM_size, 0); |
1397 |
|
1398 |
/* load boot prom */
|
1399 |
prom_offset = RAM_size + hwdef->vram_size; |
1400 |
cpu_register_physical_memory(hwdef->slavio_base, |
1401 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
1402 |
TARGET_PAGE_MASK, |
1403 |
prom_offset | IO_MEM_ROM); |
1404 |
|
1405 |
if (bios_name == NULL) |
1406 |
bios_name = PROM_FILENAME; |
1407 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
1408 |
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
1409 |
if (ret < 0 || ret > PROM_SIZE_MAX) |
1410 |
ret = load_image(buf, phys_ram_base + prom_offset); |
1411 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
1412 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
1413 |
buf); |
1414 |
exit(1);
|
1415 |
} |
1416 |
|
1417 |
/* set up devices */
|
1418 |
sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); |
1419 |
|
1420 |
for (i = 0; i < MAX_IOUNITS; i++) |
1421 |
if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1422 |
iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1423 |
hwdef->iounit_version, |
1424 |
sbi_irq[hwdef->me_irq]); |
1425 |
|
1426 |
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], |
1427 |
iounits[0], &espdma_irq, &esp_reset);
|
1428 |
|
1429 |
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], |
1430 |
iounits[0], &ledma_irq, &le_reset);
|
1431 |
|
1432 |
if (graphic_depth != 8 && graphic_depth != 24) { |
1433 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1434 |
exit (1);
|
1435 |
} |
1436 |
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
1437 |
hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
1438 |
|
1439 |
if (nd_table[0].model == NULL |
1440 |
|| strcmp(nd_table[0].model, "lance") == 0) { |
1441 |
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
1442 |
} else if (strcmp(nd_table[0].model, "?") == 0) { |
1443 |
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
1444 |
exit (1);
|
1445 |
} else {
|
1446 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
1447 |
exit (1);
|
1448 |
} |
1449 |
|
1450 |
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, |
1451 |
hwdef->nvram_size, 8);
|
1452 |
|
1453 |
slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], |
1454 |
sbi_cpu_irq, smp_cpus); |
1455 |
|
1456 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], |
1457 |
nographic); |
1458 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1459 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1460 |
slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], |
1461 |
serial_hds[1], serial_hds[0]); |
1462 |
|
1463 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
1464 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
1465 |
exit(1);
|
1466 |
} |
1467 |
|
1468 |
main_esp = esp_init(hwdef->esp_base, 2,
|
1469 |
espdma_memory_read, espdma_memory_write, |
1470 |
espdma, *espdma_irq, esp_reset); |
1471 |
|
1472 |
for (i = 0; i < ESP_MAX_DEVS; i++) { |
1473 |
drive_index = drive_get_index(IF_SCSI, 0, i);
|
1474 |
if (drive_index == -1) |
1475 |
continue;
|
1476 |
esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
1477 |
} |
1478 |
|
1479 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename); |
1480 |
|
1481 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1482 |
boot_device, RAM_size, kernel_size, graphic_width, |
1483 |
graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
|
1484 |
} |
1485 |
|
1486 |
/* SPARCserver 1000 hardware initialisation */
|
1487 |
static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size, |
1488 |
const char *boot_device, DisplayState *ds, |
1489 |
const char *kernel_filename, const char *kernel_cmdline, |
1490 |
const char *initrd_filename, const char *cpu_model) |
1491 |
{ |
1492 |
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
1493 |
kernel_cmdline, initrd_filename, cpu_model); |
1494 |
} |
1495 |
|
1496 |
/* SPARCcenter 2000 hardware initialisation */
|
1497 |
static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size, |
1498 |
const char *boot_device, DisplayState *ds, |
1499 |
const char *kernel_filename, const char *kernel_cmdline, |
1500 |
const char *initrd_filename, const char *cpu_model) |
1501 |
{ |
1502 |
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
1503 |
kernel_cmdline, initrd_filename, cpu_model); |
1504 |
} |
1505 |
|
1506 |
QEMUMachine ss1000_machine = { |
1507 |
"SS-1000",
|
1508 |
"Sun4d platform, SPARCserver 1000",
|
1509 |
ss1000_init, |
1510 |
PROM_SIZE_MAX + TCX_SIZE, |
1511 |
}; |
1512 |
|
1513 |
QEMUMachine ss2000_machine = { |
1514 |
"SS-2000",
|
1515 |
"Sun4d platform, SPARCcenter 2000",
|
1516 |
ss2000_init, |
1517 |
PROM_SIZE_MAX + TCX_SIZE, |
1518 |
}; |