root / include / hw / pci / pci.h @ 22773d60
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#ifndef QEMU_PCI_H
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#define QEMU_PCI_H
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#include "qemu-common.h" |
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#include "hw/qdev.h" |
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#include "exec/memory.h" |
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#include "sysemu/dma.h" |
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/* PCI includes legacy ISA access. */
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#include "hw/isa/isa.h" |
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#include "hw/pci/pcie.h" |
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/* PCI bus */
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
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#define PCI_FUNC(devfn) ((devfn) & 0x07) |
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#define PCI_SLOT_MAX 32 |
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#define PCI_FUNC_MAX 8 |
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/* Class, Vendor and Device IDs from Linux's pci_ids.h */
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#include "hw/pci/pci_ids.h" |
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/* QEMU-specific Vendor and Device ID definitions */
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/* IBM (0x1014) */
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#define PCI_DEVICE_ID_IBM_440GX 0x027f |
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#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
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/* Hitachi (0x1054) */
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#define PCI_VENDOR_ID_HITACHI 0x1054 |
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#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
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/* Apple (0x106b) */
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#define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
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#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
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#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
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#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
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#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
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/* Realtek (0x10ec) */
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#define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
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/* Xilinx (0x10ee) */
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#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
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/* Marvell (0x11ab) */
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#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
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/* QEMU/Bochs VGA (0x1234) */
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#define PCI_VENDOR_ID_QEMU 0x1234 |
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#define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
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/* VMWare (0x15ad) */
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#define PCI_VENDOR_ID_VMWARE 0x15ad |
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#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
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#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
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#define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
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#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
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#define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
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#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 |
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/* Intel (0x8086) */
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#define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
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#define PCI_DEVICE_ID_INTEL_82557 0x1229 |
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#define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
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/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
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#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
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#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
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#define PCI_SUBDEVICE_ID_QEMU 0x1100 |
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#define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
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#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
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#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
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#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
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#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
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#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 |
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#define PCI_DEVICE_ID_VIRTIO_9P 0x1009 |
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#define PCI_VENDOR_ID_REDHAT 0x1b36 |
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#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 |
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#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 |
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#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 |
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#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 |
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#define PCI_DEVICE_ID_REDHAT_TEST 0x0005 |
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#define PCI_DEVICE_ID_REDHAT_QXL 0x0100 |
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#define FMT_PCIBUS PRIx64
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typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
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uint32_t address, uint32_t data, int len);
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typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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uint32_t address, int len);
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typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
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pcibus_t addr, pcibus_t size, int type);
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typedef void PCIUnregisterFunc(PCIDevice *pci_dev); |
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typedef struct PCIIORegion { |
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pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
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#define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
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pcibus_t size; |
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uint8_t type; |
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MemoryRegion *memory; |
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MemoryRegion *address_space; |
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} PCIIORegion; |
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#define PCI_ROM_SLOT 6 |
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#define PCI_NUM_REGIONS 7 |
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enum {
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QEMU_PCI_VGA_MEM, |
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QEMU_PCI_VGA_IO_LO, |
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QEMU_PCI_VGA_IO_HI, |
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QEMU_PCI_VGA_NUM_REGIONS, |
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}; |
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#define QEMU_PCI_VGA_MEM_BASE 0xa0000 |
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#define QEMU_PCI_VGA_MEM_SIZE 0x20000 |
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#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 |
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#define QEMU_PCI_VGA_IO_LO_SIZE 0xc |
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#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 |
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#define QEMU_PCI_VGA_IO_HI_SIZE 0x20 |
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#include "hw/pci/pci_regs.h" |
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/* PCI HEADER_TYPE */
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#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
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/* Size of the standard PCI config header */
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#define PCI_CONFIG_HEADER_SIZE 0x40 |
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/* Size of the standard PCI config space */
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#define PCI_CONFIG_SPACE_SIZE 0x100 |
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/* Size of the standart PCIe config space: 4KB */
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#define PCIE_CONFIG_SPACE_SIZE 0x1000 |
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#define PCI_NUM_PINS 4 /* A-D */ |
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/* Bits in cap_present field. */
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enum {
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QEMU_PCI_CAP_MSI = 0x1,
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QEMU_PCI_CAP_MSIX = 0x2,
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QEMU_PCI_CAP_EXPRESS = 0x4,
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/* multifunction capable device */
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#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
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QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
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/* command register SERR bit enabled */
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#define QEMU_PCI_CAP_SERR_BITNR 4 |
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QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
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/* Standard hot plug controller. */
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#define QEMU_PCI_SHPC_BITNR 5 |
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QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
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#define QEMU_PCI_SLOTID_BITNR 6 |
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QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
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}; |
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#define TYPE_PCI_DEVICE "pci-device" |
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#define PCI_DEVICE(obj) \
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OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) |
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#define PCI_DEVICE_CLASS(klass) \
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OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) |
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#define PCI_DEVICE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) |
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typedef struct PCIINTxRoute { |
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enum {
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PCI_INTX_ENABLED, |
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PCI_INTX_INVERTED, |
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PCI_INTX_DISABLED, |
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} mode; |
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int irq;
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} PCIINTxRoute; |
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typedef struct PCIDeviceClass { |
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DeviceClass parent_class; |
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int (*init)(PCIDevice *dev);
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PCIUnregisterFunc *exit; |
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PCIConfigReadFunc *config_read; |
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PCIConfigWriteFunc *config_write; |
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uint16_t vendor_id; |
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uint16_t device_id; |
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uint8_t revision; |
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uint16_t class_id; |
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uint16_t subsystem_vendor_id; /* only for header type = 0 */
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uint16_t subsystem_id; /* only for header type = 0 */
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/*
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* pci-to-pci bridge or normal device.
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* This doesn't mean pci host switch.
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* When card bus bridge is supported, this would be enhanced.
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*/
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int is_bridge;
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/* pcie stuff */
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int is_express; /* is this device pci express? */ |
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/* device isn't hot-pluggable */
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int no_hotplug;
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/* rom bar */
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const char *romfile; |
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} PCIDeviceClass; |
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typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); |
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typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
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MSIMessage msg); |
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typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); |
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typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, |
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unsigned int vector_start, |
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unsigned int vector_end); |
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struct PCIDevice {
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DeviceState qdev; |
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/* PCI config space */
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uint8_t *config; |
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/* Used to enable config checks on load. Note that writable bits are
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* never checked even if set in cmask. */
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uint8_t *cmask; |
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/* Used to implement R/W bytes */
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uint8_t *wmask; |
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/* Used to implement RW1C(Write 1 to Clear) bytes */
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uint8_t *w1cmask; |
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/* Used to allocate config space for capabilities. */
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uint8_t *used; |
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|
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/* the following fields are read only */
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PCIBus *bus; |
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int32_t devfn; |
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char name[64]; |
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PCIIORegion io_regions[PCI_NUM_REGIONS]; |
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AddressSpace bus_master_as; |
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MemoryRegion bus_master_enable_region; |
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DMAContext *dma; |
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|
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/* do not access the following fields */
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PCIConfigReadFunc *config_read; |
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PCIConfigWriteFunc *config_write; |
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/* IRQ objects for the INTA-INTD pins. */
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qemu_irq *irq; |
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|
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/* Legacy PCI VGA regions */
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MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; |
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bool has_vga;
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/* Current IRQ levels. Used internally by the generic PCI code. */
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uint8_t irq_state; |
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/* Capability bits */
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uint32_t cap_present; |
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/* Offset of MSI-X capability in config space */
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uint8_t msix_cap; |
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|
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/* MSI-X entries */
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int msix_entries_nr;
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|
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/* Space to store MSIX table & pending bit array */
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uint8_t *msix_table; |
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uint8_t *msix_pba; |
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/* MemoryRegion container for msix exclusive BAR setup */
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MemoryRegion msix_exclusive_bar; |
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/* Memory Regions for MSIX table and pending bit entries. */
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MemoryRegion msix_table_mmio; |
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MemoryRegion msix_pba_mmio; |
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/* Reference-count for entries actually in use by driver. */
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unsigned *msix_entry_used;
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/* MSIX function mask set or MSIX disabled */
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bool msix_function_masked;
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/* Version id needed for VMState */
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int32_t version_id; |
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|
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/* Offset of MSI capability in config space */
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uint8_t msi_cap; |
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|
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/* PCI Express */
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PCIExpressDevice exp; |
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/* SHPC */
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SHPCDevice *shpc; |
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|
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/* Location of option rom */
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char *romfile;
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bool has_rom;
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MemoryRegion rom; |
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uint32_t rom_bar; |
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|
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/* INTx routing notifier */
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PCIINTxRoutingNotifier intx_routing_notifier; |
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|
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/* MSI-X notifiers */
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MSIVectorUseNotifier msix_vector_use_notifier; |
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MSIVectorReleaseNotifier msix_vector_release_notifier; |
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MSIVectorPollNotifier msix_vector_poll_notifier; |
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}; |
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|
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void pci_register_bar(PCIDevice *pci_dev, int region_num, |
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uint8_t attr, MemoryRegion *memory); |
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void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
|
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MemoryRegion *io_lo, MemoryRegion *io_hi); |
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void pci_unregister_vga(PCIDevice *pci_dev);
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pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
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|
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int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
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uint8_t offset, uint8_t size); |
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|
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void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
|
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|
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uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
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|
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|
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uint32_t pci_default_read_config(PCIDevice *d, |
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uint32_t address, int len);
|
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len);
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void pci_device_save(PCIDevice *s, QEMUFile *f);
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int pci_device_load(PCIDevice *s, QEMUFile *f);
|
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MemoryRegion *pci_address_space(PCIDevice *dev); |
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MemoryRegion *pci_address_space_io(PCIDevice *dev); |
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|
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typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
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typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
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typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); |
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|
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typedef enum { |
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PCI_HOTPLUG_DISABLED, |
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PCI_HOTPLUG_ENABLED, |
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PCI_COLDPLUG_ENABLED, |
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} PCIHotplugState; |
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|
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typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, |
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PCIHotplugState state); |
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|
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#define TYPE_PCI_BUS "PCI" |
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#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
|
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#define TYPE_PCIE_BUS "PCIE" |
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|
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bool pci_bus_is_express(PCIBus *bus);
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bool pci_bus_is_root(PCIBus *bus);
|
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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
|
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const char *name, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, const char *typename); |
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, const char *typename); |
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
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void *irq_opaque, int nirq); |
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int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
|
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/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
|
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int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); |
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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void *irq_opaque,
|
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, int nirq, const char *typename); |
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void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
|
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PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
|
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bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
|
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void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
|
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void pci_device_set_intx_routing_notifier(PCIDevice *dev,
|
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PCIINTxRoutingNotifier notifier); |
378 |
void pci_device_reset(PCIDevice *dev);
|
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void pci_bus_reset(PCIBus *bus);
|
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|
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PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
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const char *default_devaddr); |
383 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
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const char *default_devaddr); |
385 |
|
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PCIDevice *pci_vga_init(PCIBus *bus); |
387 |
|
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int pci_bus_num(PCIBus *s);
|
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void pci_for_each_device(PCIBus *bus, int bus_num, |
390 |
void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), |
391 |
void *opaque);
|
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PCIBus *pci_find_root_bus(int domain);
|
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int pci_find_domain(const PCIBus *bus); |
394 |
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
|
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int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
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PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
397 |
|
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int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
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unsigned *slotp);
|
400 |
|
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void pci_device_deassert_intx(PCIDevice *dev);
|
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|
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typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int); |
404 |
|
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void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque); |
406 |
|
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static inline void |
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pci_set_byte(uint8_t *config, uint8_t val) |
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{ |
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*config = val; |
411 |
} |
412 |
|
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static inline uint8_t |
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pci_get_byte(const uint8_t *config)
|
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{ |
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return *config;
|
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} |
418 |
|
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static inline void |
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pci_set_word(uint8_t *config, uint16_t val) |
421 |
{ |
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cpu_to_le16wu((uint16_t *)config, val); |
423 |
} |
424 |
|
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static inline uint16_t |
426 |
pci_get_word(const uint8_t *config)
|
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{ |
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return le16_to_cpupu((const uint16_t *)config); |
429 |
} |
430 |
|
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static inline void |
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pci_set_long(uint8_t *config, uint32_t val) |
433 |
{ |
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cpu_to_le32wu((uint32_t *)config, val); |
435 |
} |
436 |
|
437 |
static inline uint32_t |
438 |
pci_get_long(const uint8_t *config)
|
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{ |
440 |
return le32_to_cpupu((const uint32_t *)config); |
441 |
} |
442 |
|
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static inline void |
444 |
pci_set_quad(uint8_t *config, uint64_t val) |
445 |
{ |
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cpu_to_le64w((uint64_t *)config, val); |
447 |
} |
448 |
|
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static inline uint64_t |
450 |
pci_get_quad(const uint8_t *config)
|
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{ |
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return le64_to_cpup((const uint64_t *)config); |
453 |
} |
454 |
|
455 |
static inline void |
456 |
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
457 |
{ |
458 |
pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
459 |
} |
460 |
|
461 |
static inline void |
462 |
pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
463 |
{ |
464 |
pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
465 |
} |
466 |
|
467 |
static inline void |
468 |
pci_config_set_revision(uint8_t *pci_config, uint8_t val) |
469 |
{ |
470 |
pci_set_byte(&pci_config[PCI_REVISION_ID], val); |
471 |
} |
472 |
|
473 |
static inline void |
474 |
pci_config_set_class(uint8_t *pci_config, uint16_t val) |
475 |
{ |
476 |
pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
477 |
} |
478 |
|
479 |
static inline void |
480 |
pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) |
481 |
{ |
482 |
pci_set_byte(&pci_config[PCI_CLASS_PROG], val); |
483 |
} |
484 |
|
485 |
static inline void |
486 |
pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) |
487 |
{ |
488 |
pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); |
489 |
} |
490 |
|
491 |
/*
|
492 |
* helper functions to do bit mask operation on configuration space.
|
493 |
* Just to set bit, use test-and-set and discard returned value.
|
494 |
* Just to clear bit, use test-and-clear and discard returned value.
|
495 |
* NOTE: They aren't atomic.
|
496 |
*/
|
497 |
static inline uint8_t |
498 |
pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) |
499 |
{ |
500 |
uint8_t val = pci_get_byte(config); |
501 |
pci_set_byte(config, val & ~mask); |
502 |
return val & mask;
|
503 |
} |
504 |
|
505 |
static inline uint8_t |
506 |
pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) |
507 |
{ |
508 |
uint8_t val = pci_get_byte(config); |
509 |
pci_set_byte(config, val | mask); |
510 |
return val & mask;
|
511 |
} |
512 |
|
513 |
static inline uint16_t |
514 |
pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) |
515 |
{ |
516 |
uint16_t val = pci_get_word(config); |
517 |
pci_set_word(config, val & ~mask); |
518 |
return val & mask;
|
519 |
} |
520 |
|
521 |
static inline uint16_t |
522 |
pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) |
523 |
{ |
524 |
uint16_t val = pci_get_word(config); |
525 |
pci_set_word(config, val | mask); |
526 |
return val & mask;
|
527 |
} |
528 |
|
529 |
static inline uint32_t |
530 |
pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) |
531 |
{ |
532 |
uint32_t val = pci_get_long(config); |
533 |
pci_set_long(config, val & ~mask); |
534 |
return val & mask;
|
535 |
} |
536 |
|
537 |
static inline uint32_t |
538 |
pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) |
539 |
{ |
540 |
uint32_t val = pci_get_long(config); |
541 |
pci_set_long(config, val | mask); |
542 |
return val & mask;
|
543 |
} |
544 |
|
545 |
static inline uint64_t |
546 |
pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) |
547 |
{ |
548 |
uint64_t val = pci_get_quad(config); |
549 |
pci_set_quad(config, val & ~mask); |
550 |
return val & mask;
|
551 |
} |
552 |
|
553 |
static inline uint64_t |
554 |
pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) |
555 |
{ |
556 |
uint64_t val = pci_get_quad(config); |
557 |
pci_set_quad(config, val | mask); |
558 |
return val & mask;
|
559 |
} |
560 |
|
561 |
/* Access a register specified by a mask */
|
562 |
static inline void |
563 |
pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) |
564 |
{ |
565 |
uint8_t val = pci_get_byte(config); |
566 |
uint8_t rval = reg << (ffs(mask) - 1);
|
567 |
pci_set_byte(config, (~mask & val) | (mask & rval)); |
568 |
} |
569 |
|
570 |
static inline uint8_t |
571 |
pci_get_byte_by_mask(uint8_t *config, uint8_t mask) |
572 |
{ |
573 |
uint8_t val = pci_get_byte(config); |
574 |
return (val & mask) >> (ffs(mask) - 1); |
575 |
} |
576 |
|
577 |
static inline void |
578 |
pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) |
579 |
{ |
580 |
uint16_t val = pci_get_word(config); |
581 |
uint16_t rval = reg << (ffs(mask) - 1);
|
582 |
pci_set_word(config, (~mask & val) | (mask & rval)); |
583 |
} |
584 |
|
585 |
static inline uint16_t |
586 |
pci_get_word_by_mask(uint8_t *config, uint16_t mask) |
587 |
{ |
588 |
uint16_t val = pci_get_word(config); |
589 |
return (val & mask) >> (ffs(mask) - 1); |
590 |
} |
591 |
|
592 |
static inline void |
593 |
pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) |
594 |
{ |
595 |
uint32_t val = pci_get_long(config); |
596 |
uint32_t rval = reg << (ffs(mask) - 1);
|
597 |
pci_set_long(config, (~mask & val) | (mask & rval)); |
598 |
} |
599 |
|
600 |
static inline uint32_t |
601 |
pci_get_long_by_mask(uint8_t *config, uint32_t mask) |
602 |
{ |
603 |
uint32_t val = pci_get_long(config); |
604 |
return (val & mask) >> (ffs(mask) - 1); |
605 |
} |
606 |
|
607 |
static inline void |
608 |
pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) |
609 |
{ |
610 |
uint64_t val = pci_get_quad(config); |
611 |
uint64_t rval = reg << (ffs(mask) - 1);
|
612 |
pci_set_quad(config, (~mask & val) | (mask & rval)); |
613 |
} |
614 |
|
615 |
static inline uint64_t |
616 |
pci_get_quad_by_mask(uint8_t *config, uint64_t mask) |
617 |
{ |
618 |
uint64_t val = pci_get_quad(config); |
619 |
return (val & mask) >> (ffs(mask) - 1); |
620 |
} |
621 |
|
622 |
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
623 |
const char *name); |
624 |
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
625 |
bool multifunction,
|
626 |
const char *name); |
627 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
628 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
629 |
|
630 |
static inline int pci_is_express(const PCIDevice *d) |
631 |
{ |
632 |
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
|
633 |
} |
634 |
|
635 |
static inline uint32_t pci_config_size(const PCIDevice *d) |
636 |
{ |
637 |
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
638 |
} |
639 |
|
640 |
/* DMA access functions */
|
641 |
static inline DMAContext *pci_dma_context(PCIDevice *dev) |
642 |
{ |
643 |
return dev->dma;
|
644 |
} |
645 |
|
646 |
static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
647 |
void *buf, dma_addr_t len, DMADirection dir)
|
648 |
{ |
649 |
dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir); |
650 |
return 0; |
651 |
} |
652 |
|
653 |
static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, |
654 |
void *buf, dma_addr_t len)
|
655 |
{ |
656 |
return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
|
657 |
} |
658 |
|
659 |
static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, |
660 |
const void *buf, dma_addr_t len) |
661 |
{ |
662 |
return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); |
663 |
} |
664 |
|
665 |
#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
|
666 |
static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ |
667 |
dma_addr_t addr) \ |
668 |
{ \ |
669 |
return ld##_l##_dma(pci_dma_context(dev), addr); \ |
670 |
} \ |
671 |
static inline void st##_s##_pci_dma(PCIDevice *dev, \ |
672 |
dma_addr_t addr, uint##_bits##_t val) \ |
673 |
{ \ |
674 |
st##_s##_dma(pci_dma_context(dev), addr, val); \ |
675 |
} |
676 |
|
677 |
PCI_DMA_DEFINE_LDST(ub, b, 8);
|
678 |
PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
|
679 |
PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
|
680 |
PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
|
681 |
PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
|
682 |
PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
|
683 |
PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
|
684 |
|
685 |
#undef PCI_DMA_DEFINE_LDST
|
686 |
|
687 |
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, |
688 |
dma_addr_t *plen, DMADirection dir) |
689 |
{ |
690 |
void *buf;
|
691 |
|
692 |
buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir); |
693 |
return buf;
|
694 |
} |
695 |
|
696 |
static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, |
697 |
DMADirection dir, dma_addr_t access_len) |
698 |
{ |
699 |
dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len); |
700 |
} |
701 |
|
702 |
static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, |
703 |
int alloc_hint)
|
704 |
{ |
705 |
qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev)); |
706 |
} |
707 |
|
708 |
extern const VMStateDescription vmstate_pci_device; |
709 |
|
710 |
#define VMSTATE_PCI_DEVICE(_field, _state) { \
|
711 |
.name = (stringify(_field)), \ |
712 |
.size = sizeof(PCIDevice), \
|
713 |
.vmsd = &vmstate_pci_device, \ |
714 |
.flags = VMS_STRUCT, \ |
715 |
.offset = vmstate_offset_value(_state, _field, PCIDevice), \ |
716 |
} |
717 |
|
718 |
#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
|
719 |
.name = (stringify(_field)), \ |
720 |
.size = sizeof(PCIDevice), \
|
721 |
.vmsd = &vmstate_pci_device, \ |
722 |
.flags = VMS_STRUCT|VMS_POINTER, \ |
723 |
.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ |
724 |
} |
725 |
|
726 |
#endif
|