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arm: remove dead assignments, spotted by clang analyzer
Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: fix neon vmon/vmvn with modified immediate
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com>Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: resource leak fixes for iwmmxt disassemble
This patch fixes few resource leaks in the iwmmxt disassemble.
Signed-off-by: Lars Munch <lars@segv.dk>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix handling of AL condition in IT instruction
Do not try to insert a conditional jump over next instruction when thecondition code is AL as this will trigger an internal error.
Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: make RFE usable with any register
The rfe instruction can be used with any register, not just sp. Adjust thecondition check accordingly.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix missing 'return' in SRS handling.
There's a return missing in the srs handling which leads to srs always beingtreated an an invalid op.
target-arm: neon vshll instruction fix
implementation only widened the 32bit source vector elements into a64bit destination vector but forgot to perform the actual shiftingoperation.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Riku Voipio <riku.voipio@nokia.com>...
target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN
The rounding/truncating options were inverted. truncatingwas done when rounding was meant and vice verse.
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
ARM CP15 tls fix
Fix temporary handling in cp15 tls register load/store.
Signed-off-by: Paul Brook <paul@codesourcery.com>
target-arm: implement Thumb-2 exception return
Support the "subs pc, lr" Thumb-2 exception return instruction.
Signed-off-by: Rabin Vincent <rabin@rab.in>Signed-off-by: Paul Brook <paul@codesourcery.com>
target-arm: fix thumb CPS
The Thumb CPS currently does not work correctly: CPSID touches more bitsthan the instruction wants to, and CPSIE does nothing. Fix it bypassing the correct mask (the "affect" bits) and value.
Signed-off-by: Rabin Vincent <rabin@rab.in>
target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of witha slow helper. If the the cp15 read/write was not TLS register access,fall back to the cp15 helper.
This makes accessing __thread variables in linux-user when apps are compiled...
target-arm: fix strexd
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.
ARM FP16 support
Implement the ARM VFP half precision floating point extensions.
target-arm: use native tcg-ops for ror/bic/vorn
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix neon vshrn/vrshrn ops
In the existing code shift value is clobbered during the pass loop.This patch changes the code so that it stores the intermediateresult in the target neon register directly and eliminates the needto use a temporary to hold the intermediate value thus leaving the...
target-arm: add support for neon vld1.64/vst1.64 instructions
Add support for NEON vld1.64 and vst1.64 instructions. This patch isrevised to follow more closely the specification and raisesundefined exception if 64bit element size is used for vld2/vst2 or...
target-arm: allow modifying vfp fpexc en bit only
All other bits except for the EN in the VFP FPEXC register are definedas subarchitecture specific and real functionality for any of theother bits has not been implemented in QEMU. However, current codeallows modifying all bits in the VFP FPEXC register leading to...
target-arm: fix neon vsri, vshl and vsli ops
Shift by immediate value is incorrectly overwritten by a temporaryvariable in the processing of NEON vsri, vshl and vsli instructions.This patch has been revised to also include a fix for the specialcase where the code would previously try to shift an integer value...
target-arm: fix incorrect temporary variable freeing
tmp4 and tmp5 temporary variables are allocated using tcg_const_i32but incorrectly released using dead_tmp which will cause resourceleak tracking to report false leaks.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>...
target-arm: optimize thumb 32-bit multiply
Current implementation of thumb mul instruction is implemented as a32x32->64 multiply which then uses only 32 least significant bits ofthe result. Replace that with a simple 32x32->32 multiply.
target-arm: cleanup internal resource leaks
Revised patch for getting rid of tcg temporary variable leaks intarget-arm/translate.c. This version also includes the leak patch forgen_set_cpsr macro, now converted as a static inline function, which Isent earlier as a separate patch on top of this patch....
target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330ed
Use load_reg_var() instead of accessing cpu_R[rn] directly to generatecorrect code when rn = 15.
target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7
target-arm: remove cpu_T for ARM once and for all
Signed-off-by: Filip Navara <filip.navara@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: convert gen_lookup_tb not to use cpu_T
target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16helpers used fixed registers to return values. This patch replaces that withTCG code, so T0/T1 is no longer directly used by the helper functions....
target-arm: fix TANDC and TORC instructions
Uninitialized register was used instead of proper TCG variable.
target-arm: replace thumb usage of cpu_T registers by proper register allocations
The goal is eventually to get rid of all cpu_T register usage and to usejust short-lived tmp/tmp2 registers. This patch converts all the places wherecpu_T was used in the Thumb code and replaces it with explicit TCG register...
target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T
target-arm: convert disas_neon_data_insn and helpers not to use cpu_T
target-arm: convert disas_neon_ls_insn not to use cpu_T
target-arm: convert disas_dsp_insn not use cpu_T
target-arm: convert disas_iwmmxt_insn not to use cpu_T
target-arm: convert VFP not to use cpu_T
target-arm: use tcg_global_mem_new_i32 to allocate registers
Currently each read/write of ARM register involves a LD/ST TCG operation. Thispatch uses TCG memory-backed registers to represent the ARM register set. Withmemory-backed registers the LD/ST operations are transparently generated by TCG...
target-arm: get rid of temporary variable cache
The temporary variable cache in no longer need since tcg_temp_free was introduced.
target-arm: remove useless line that sets register that is never used again
target-arm: remove unused gen_movl_T2_reg function
target-arm: fix SRS/RFE instructions
The encoding of 'IA' and 'DB' conditions was swapped.SRS instruction must store banked SPSR instead of CPSR at the specific address.Missing 'return' statement at the end of RFE handling.Fixed write-back code to reference correct registers....
target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Update to a hopefully more future proof FSF address
Remove unused gen_bx_T0 function.
Signed-off-by: Filip Navara <filip.navara@gmail.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
fix ARMv7 data processing instructions
ARMv7 defines a new behavior for ARM data processing instructionscompared to earlier architecture revisions; when the destinationregister is R15, a Branch and Exchange operation is executed ratherthan a simple Branch to the target address. This patch corrects the...
Modernize parts of target-arm/translate.c in preparation for themodifications in the subsequent patch in this patch set. This is donein order to avoid writing new code to target-arm/translate.c thatwould use deprecated methods and/or variables....
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
Fix ARM quadword VDUP (core register).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Implement (very) basic Thumb2-EE support. This doesn't actually implementEE state, just the associated system coprocessor registers. It is sufficientto keep OS setup and context switching code happy.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
Fix VFP fixed point conversion routines.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
ARM: fix smmul and smmla/smmls usage of registers (Mans Rullgard).
This fixes the destination and accumulator registers for the smmuland smmla instructions.
Signed-off-by: Mans Rullgard <mans@mansr.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
ARM: fix usad8 and usada8 usage of registers (Mans Rullgard).
This fixes the destination and accumulator registers for the usad8and usada8 instructions.
Signed-off-by: Mans Rullgard <mans@mansr.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>...
Patch holes in ARM translation (Laurent Desnogues).
- gen_set_CF_bit31: use the right value to set carry flag - shifter_out_im: remove a spurious semi-colon - add a break for VSHRN, VRSHRN, VQSHRN, VQRSHRN size 2 case - sbfx, ubfx are v6t2 instructions...
ARM: cosmetics (Laurent Desnogues).
- remove macros that are not used - remove disass structure is_mem field which value is never used - correct a typo in a comment.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>...
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying thecode and also fixing a use after release issue incpu_break/watchpoint_remove_all.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Remove premature memop TB terminations (Jan Kiszka)
Now that we can properly restore the pc on watchpoint hits, there is nomore need for prematurely terminating TBs if watchpoints are present.Remove all related bits.
Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow thesucceeding enhancements this series comes with.
First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switchingto dynamically allocated data structures that are kept in linked lists....
TCG variable type checking.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
VFP fnmsc negative zero fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5610 c046a42c-6fe2-441c-8c8c-71466251a162
Fix undeclared symbol warnings from sparse
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
Additional exclusive load/store instruction are v6K, not v6T2.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5518 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARMv6t2 strex instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5517 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM NEON vdup and vtbl bugs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5286 c046a42c-6fe2-441c-8c8c-71466251a162
Fix neon encoding comment.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5285 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
Fix QADD / QSUB decoding on ARM (Torbjörn Andersson).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5273 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
ARM: fix CPS masks (Vincent Palatin).
According to ARM Reference Manual (DDI0100 A4.1.16),bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction maskshould be 0x0ff10020 not 0x0ff10010.Besides, mmod flag is bit 17 (b14 is SBZ)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).
helper.c - copy reference c0_c2 to runtime c0_c2 and not c0_c1
op_helper.c - remove old code (PARAM1, probably some left over from old dyngen) that broke do_[us]sat
translate.c...
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
Terminate TB immediately after v7-M exception return.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4868 c046a42c-6fe2-441c-8c8c-71466251a162
Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
Silence compiler warning.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4839 c046a42c-6fe2-441c-8c8c-71466251a162
Spelling fixes, spotted by Stuart Brady.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4809 c046a42c-6fe2-441c-8c8c-71466251a162
Suppress bogus compiler warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4803 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
Mark a dead_tmp as such in ARM msr.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4648 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ARM magic kernel page and TLS register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4610 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM conditional branch bug.Add tcg_gen_brcondi.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
Remove arm's local not_i32 tcg op now that there's one in tcg.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4475 c046a42c-6fe2-441c-8c8c-71466251a162
Add TCG native negation op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
Add zero extension (pseudo-)ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
Factorize code in translate.c
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
Remove an unused field and fix some non-code typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
Correct more ARM VFP 32/64 and signed/unsigned typos.
Fixes unreadable fonts in Maemo guest.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4221 c046a42c-6fe2-441c-8c8c-71466251a162
Save the exact SWI return address in Thumb mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4217 c046a42c-6fe2-441c-8c8c-71466251a162
Correctly restore pc after an exception occured in Thumb mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4211 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM VFP related segfaults.
The fconst change is partly a guess.VFP_OP1 is still unused.An ARMv6 target still won't boot.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4210 c046a42c-6fe2-441c-8c8c-71466251a162
Fix the offset in Thumb bl instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4204 c046a42c-6fe2-441c-8c8c-71466251a162
Set an unset label in ARM strex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4203 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM and Thumb ldlex/stlex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4202 c046a42c-6fe2-441c-8c8c-71466251a162
Store the right TCG temp (typo).
Stops ARMv6 target from segfaulting early.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4201 c046a42c-6fe2-441c-8c8c-71466251a162
ARM N=Z=1 flag fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 15/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4152 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 14/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162