Revision 24056690
b/Makefile.target | ||
---|---|---|
242 | 242 |
obj-sparc-y += mc146818rtc.o |
243 | 243 |
obj-sparc-y += cirrus_vga.o |
244 | 244 |
else |
245 |
obj-sparc-y = sun4m.o lance.o tcx.o iommu.o slavio_intctl.o |
|
245 |
obj-sparc-y = sun4m.o lance.o tcx.o sun4m_iommu.o slavio_intctl.o
|
|
246 | 246 |
obj-sparc-y += slavio_timer.o slavio_misc.o sparc32_dma.o |
247 | 247 |
obj-sparc-y += cs4231.o eccmemctl.o sbi.o sun4c_intctl.o |
248 | 248 |
endif |
/dev/null | ||
---|---|---|
1 |
/* |
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* QEMU SPARC iommu emulation |
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3 |
* |
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* Copyright (c) 2003-2005 Fabrice Bellard |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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|
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#include "sun4m.h" |
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#include "sysbus.h" |
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|
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/* debug iommu */ |
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//#define DEBUG_IOMMU |
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|
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#ifdef DEBUG_IOMMU |
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#define DPRINTF(fmt, ...) \ |
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do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) |
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#else |
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#define DPRINTF(fmt, ...) |
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#endif |
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|
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#define IOMMU_NREGS (4*4096/4) |
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#define IOMMU_CTRL (0x0000 >> 2) |
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#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
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#define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
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42 |
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
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#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
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#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
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#define IOMMU_CTRL_MASK 0x0000001d |
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|
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#define IOMMU_BASE (0x0004 >> 2) |
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#define IOMMU_BASE_MASK 0x07fffc00 |
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|
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#define IOMMU_TLBFLUSH (0x0014 >> 2) |
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#define IOMMU_TLBFLUSH_MASK 0xffffffff |
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|
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#define IOMMU_PGFLUSH (0x0018 >> 2) |
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#define IOMMU_PGFLUSH_MASK 0xffffffff |
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|
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#define IOMMU_AFSR (0x1000 >> 2) |
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#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ |
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#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after |
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transaction */ |
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#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than |
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12.8 us. */ |
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#define IOMMU_AFSR_BE 0x10000000 /* Write access received error |
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acknowledge */ |
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#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ |
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#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ |
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#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by |
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hardware */ |
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#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ |
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#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ |
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#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ |
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#define IOMMU_AFSR_MASK 0xff0fffff |
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|
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#define IOMMU_AFAR (0x1004 >> 2) |
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|
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#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ |
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#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ |
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#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ |
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#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ |
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#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ |
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#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ |
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#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ |
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#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ |
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#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ |
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#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ |
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#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ |
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#define IOMMU_AER_MASK 0x801f000f |
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|
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#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when |
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bypass enabled */ |
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#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
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produced by this device as pure |
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physical. */ |
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#define IOMMU_SBCFG_MASK 0x00010003 |
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|
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#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
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#define IOMMU_ARBEN_MASK 0x001f0000 |
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#define IOMMU_MID 0x00000008 |
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|
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#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ |
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#define IOMMU_MASK_ID_MASK 0x00ffffff |
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|
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#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ |
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#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ |
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117 |
|
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/* The format of an iopte in the page tables */ |
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#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ |
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#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or |
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Viking/MXCC) */ |
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#define IOPTE_WRITE 0x00000004 /* Writeable */ |
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#define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
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#define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
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125 |
|
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#define IOMMU_PAGE_SHIFT 12 |
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#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) |
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#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) |
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|
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typedef struct IOMMUState { |
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SysBusDevice busdev; |
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uint32_t regs[IOMMU_NREGS]; |
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target_phys_addr_t iostart; |
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uint32_t version; |
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qemu_irq irq; |
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} IOMMUState; |
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137 |
|
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static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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IOMMUState *s = opaque; |
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target_phys_addr_t saddr; |
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uint32_t ret; |
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143 |
|
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saddr = addr >> 2; |
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switch (saddr) { |
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default: |
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ret = s->regs[saddr]; |
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break; |
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case IOMMU_AFAR: |
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case IOMMU_AFSR: |
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ret = s->regs[saddr]; |
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qemu_irq_lower(s->irq); |
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break; |
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} |
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DPRINTF("read reg[%d] = %x\n", (int)saddr, ret); |
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return ret; |
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} |
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158 |
|
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static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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IOMMUState *s = opaque; |
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target_phys_addr_t saddr; |
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|
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saddr = addr >> 2; |
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DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
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switch (saddr) { |
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case IOMMU_CTRL: |
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switch (val & IOMMU_CTRL_RNGE) { |
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case IOMMU_RNGE_16MB: |
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s->iostart = 0xffffffffff000000ULL; |
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break; |
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case IOMMU_RNGE_32MB: |
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s->iostart = 0xfffffffffe000000ULL; |
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break; |
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case IOMMU_RNGE_64MB: |
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s->iostart = 0xfffffffffc000000ULL; |
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break; |
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case IOMMU_RNGE_128MB: |
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s->iostart = 0xfffffffff8000000ULL; |
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break; |
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case IOMMU_RNGE_256MB: |
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s->iostart = 0xfffffffff0000000ULL; |
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break; |
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case IOMMU_RNGE_512MB: |
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s->iostart = 0xffffffffe0000000ULL; |
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break; |
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case IOMMU_RNGE_1GB: |
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s->iostart = 0xffffffffc0000000ULL; |
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break; |
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default: |
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case IOMMU_RNGE_2GB: |
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s->iostart = 0xffffffff80000000ULL; |
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break; |
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} |
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DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); |
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s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); |
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break; |
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case IOMMU_BASE: |
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s->regs[saddr] = val & IOMMU_BASE_MASK; |
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break; |
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case IOMMU_TLBFLUSH: |
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DPRINTF("tlb flush %x\n", val); |
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s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
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break; |
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case IOMMU_PGFLUSH: |
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DPRINTF("page flush %x\n", val); |
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s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
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break; |
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case IOMMU_AFAR: |
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s->regs[saddr] = val; |
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qemu_irq_lower(s->irq); |
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break; |
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case IOMMU_AER: |
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s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; |
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break; |
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case IOMMU_AFSR: |
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s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; |
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qemu_irq_lower(s->irq); |
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break; |
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case IOMMU_SBCFG0: |
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case IOMMU_SBCFG1: |
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case IOMMU_SBCFG2: |
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case IOMMU_SBCFG3: |
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s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
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break; |
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case IOMMU_ARBEN: |
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// XXX implement SBus probing: fault when reading unmapped |
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// addresses, fault cause and address stored to MMU/IOMMU |
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s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
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break; |
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232 |
case IOMMU_MASK_ID: |
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s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; |
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break; |
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default: |
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s->regs[saddr] = val; |
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break; |
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} |
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} |
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240 |
|
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static CPUReadMemoryFunc * const iommu_mem_read[3] = { |
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NULL, |
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NULL, |
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iommu_mem_readl, |
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}; |
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246 |
|
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static CPUWriteMemoryFunc * const iommu_mem_write[3] = { |
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NULL, |
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NULL, |
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iommu_mem_writel, |
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}; |
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252 |
|
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static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) |
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{ |
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uint32_t ret; |
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target_phys_addr_t iopte; |
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#ifdef DEBUG_IOMMU |
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target_phys_addr_t pa = addr; |
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#endif |
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260 |
|
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261 |
iopte = s->regs[IOMMU_BASE] << 4; |
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addr &= ~s->iostart; |
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iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; |
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cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4); |
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265 |
tswap32s(&ret); |
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266 |
DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx |
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267 |
", *pte = %x\n", pa, iopte, ret); |
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268 |
|
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269 |
return ret; |
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} |
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271 |
|
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272 |
static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr, |
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uint32_t pte) |
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274 |
{ |
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275 |
target_phys_addr_t pa; |
|
276 |
|
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277 |
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); |
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278 |
DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx |
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279 |
" (iopte = %x)\n", addr, pa, pte); |
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280 |
|
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281 |
return pa; |
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282 |
} |
|
283 |
|
|
284 |
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, |
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int is_write) |
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{ |
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287 |
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); |
|
288 |
s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | |
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289 |
IOMMU_AFSR_FAV; |
|
290 |
if (!is_write) |
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291 |
s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; |
|
292 |
s->regs[IOMMU_AFAR] = addr; |
|
293 |
qemu_irq_raise(s->irq); |
|
294 |
} |
|
295 |
|
|
296 |
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
|
297 |
uint8_t *buf, int len, int is_write) |
|
298 |
{ |
|
299 |
int l; |
|
300 |
uint32_t flags; |
|
301 |
target_phys_addr_t page, phys_addr; |
|
302 |
|
|
303 |
while (len > 0) { |
|
304 |
page = addr & IOMMU_PAGE_MASK; |
|
305 |
l = (page + IOMMU_PAGE_SIZE) - addr; |
|
306 |
if (l > len) |
|
307 |
l = len; |
|
308 |
flags = iommu_page_get_flags(opaque, page); |
|
309 |
if (!(flags & IOPTE_VALID)) { |
|
310 |
iommu_bad_addr(opaque, page, is_write); |
|
311 |
return; |
|
312 |
} |
|
313 |
phys_addr = iommu_translate_pa(addr, flags); |
|
314 |
if (is_write) { |
|
315 |
if (!(flags & IOPTE_WRITE)) { |
|
316 |
iommu_bad_addr(opaque, page, is_write); |
|
317 |
return; |
|
318 |
} |
|
319 |
cpu_physical_memory_write(phys_addr, buf, l); |
|
320 |
} else { |
|
321 |
cpu_physical_memory_read(phys_addr, buf, l); |
|
322 |
} |
|
323 |
len -= l; |
|
324 |
buf += l; |
|
325 |
addr += l; |
|
326 |
} |
|
327 |
} |
|
328 |
|
|
329 |
static const VMStateDescription vmstate_iommu = { |
|
330 |
.name ="iommu", |
|
331 |
.version_id = 2, |
|
332 |
.minimum_version_id = 2, |
|
333 |
.minimum_version_id_old = 2, |
|
334 |
.fields = (VMStateField []) { |
|
335 |
VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS), |
|
336 |
VMSTATE_UINT64(iostart, IOMMUState), |
|
337 |
VMSTATE_END_OF_LIST() |
|
338 |
} |
|
339 |
}; |
|
340 |
|
|
341 |
static void iommu_reset(DeviceState *d) |
|
342 |
{ |
|
343 |
IOMMUState *s = container_of(d, IOMMUState, busdev.qdev); |
|
344 |
|
|
345 |
memset(s->regs, 0, IOMMU_NREGS * 4); |
|
346 |
s->iostart = 0; |
|
347 |
s->regs[IOMMU_CTRL] = s->version; |
|
348 |
s->regs[IOMMU_ARBEN] = IOMMU_MID; |
|
349 |
s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
|
350 |
s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; |
|
351 |
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
|
352 |
} |
|
353 |
|
|
354 |
static int iommu_init1(SysBusDevice *dev) |
|
355 |
{ |
|
356 |
IOMMUState *s = FROM_SYSBUS(IOMMUState, dev); |
|
357 |
int io; |
|
358 |
|
|
359 |
sysbus_init_irq(dev, &s->irq); |
|
360 |
|
|
361 |
io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s); |
|
362 |
sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io); |
|
363 |
|
|
364 |
return 0; |
|
365 |
} |
|
366 |
|
|
367 |
static SysBusDeviceInfo iommu_info = { |
|
368 |
.init = iommu_init1, |
|
369 |
.qdev.name = "iommu", |
|
370 |
.qdev.size = sizeof(IOMMUState), |
|
371 |
.qdev.vmsd = &vmstate_iommu, |
|
372 |
.qdev.reset = iommu_reset, |
|
373 |
.qdev.props = (Property[]) { |
|
374 |
DEFINE_PROP_HEX32("version", IOMMUState, version, 0), |
|
375 |
DEFINE_PROP_END_OF_LIST(), |
|
376 |
} |
|
377 |
}; |
|
378 |
|
|
379 |
static void iommu_register_devices(void) |
|
380 |
{ |
|
381 |
sysbus_register_withprop(&iommu_info); |
|
382 |
} |
|
383 |
|
|
384 |
device_init(iommu_register_devices) |
b/hw/sun4m_iommu.c | ||
---|---|---|
1 |
/* |
|
2 |
* QEMU SPARC iommu emulation |
|
3 |
* |
|
4 |
* Copyright (c) 2003-2005 Fabrice Bellard |
|
5 |
* |
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
|
7 |
* of this software and associated documentation files (the "Software"), to deal |
|
8 |
* in the Software without restriction, including without limitation the rights |
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
|
10 |
* copies of the Software, and to permit persons to whom the Software is |
|
11 |
* furnished to do so, subject to the following conditions: |
|
12 |
* |
|
13 |
* The above copyright notice and this permission notice shall be included in |
|
14 |
* all copies or substantial portions of the Software. |
|
15 |
* |
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
|
22 |
* THE SOFTWARE. |
|
23 |
*/ |
|
24 |
|
|
25 |
#include "sun4m.h" |
|
26 |
#include "sysbus.h" |
|
27 |
|
|
28 |
/* debug iommu */ |
|
29 |
//#define DEBUG_IOMMU |
|
30 |
|
|
31 |
#ifdef DEBUG_IOMMU |
|
32 |
#define DPRINTF(fmt, ...) \ |
|
33 |
do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) |
|
34 |
#else |
|
35 |
#define DPRINTF(fmt, ...) |
|
36 |
#endif |
|
37 |
|
|
38 |
#define IOMMU_NREGS (4*4096/4) |
|
39 |
#define IOMMU_CTRL (0x0000 >> 2) |
|
40 |
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
|
41 |
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
|
42 |
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
|
43 |
#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
|
44 |
#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
|
45 |
#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
|
46 |
#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
|
47 |
#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
|
48 |
#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
|
49 |
#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
|
50 |
#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
|
51 |
#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
|
52 |
#define IOMMU_CTRL_MASK 0x0000001d |
|
53 |
|
|
54 |
#define IOMMU_BASE (0x0004 >> 2) |
|
55 |
#define IOMMU_BASE_MASK 0x07fffc00 |
|
56 |
|
|
57 |
#define IOMMU_TLBFLUSH (0x0014 >> 2) |
|
58 |
#define IOMMU_TLBFLUSH_MASK 0xffffffff |
|
59 |
|
|
60 |
#define IOMMU_PGFLUSH (0x0018 >> 2) |
|
61 |
#define IOMMU_PGFLUSH_MASK 0xffffffff |
|
62 |
|
|
63 |
#define IOMMU_AFSR (0x1000 >> 2) |
|
64 |
#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ |
|
65 |
#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after |
|
66 |
transaction */ |
|
67 |
#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than |
|
68 |
12.8 us. */ |
|
69 |
#define IOMMU_AFSR_BE 0x10000000 /* Write access received error |
|
70 |
acknowledge */ |
|
71 |
#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ |
|
72 |
#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ |
|
73 |
#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by |
|
74 |
hardware */ |
|
75 |
#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ |
|
76 |
#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ |
|
77 |
#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ |
|
78 |
#define IOMMU_AFSR_MASK 0xff0fffff |
|
79 |
|
|
80 |
#define IOMMU_AFAR (0x1004 >> 2) |
|
81 |
|
|
82 |
#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ |
|
83 |
#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ |
|
84 |
#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ |
|
85 |
#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ |
|
86 |
#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ |
|
87 |
#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ |
|
88 |
#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ |
|
89 |
#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ |
|
90 |
#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ |
|
91 |
#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ |
|
92 |
#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ |
|
93 |
#define IOMMU_AER_MASK 0x801f000f |
|
94 |
|
|
95 |
#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
|
96 |
#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
|
97 |
#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
|
98 |
#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
|
99 |
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when |
|
100 |
bypass enabled */ |
|
101 |
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
|
102 |
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
|
103 |
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
|
104 |
produced by this device as pure |
|
105 |
physical. */ |
|
106 |
#define IOMMU_SBCFG_MASK 0x00010003 |
|
107 |
|
|
108 |
#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
|
109 |
#define IOMMU_ARBEN_MASK 0x001f0000 |
|
110 |
#define IOMMU_MID 0x00000008 |
|
111 |
|
|
112 |
#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ |
|
113 |
#define IOMMU_MASK_ID_MASK 0x00ffffff |
|
114 |
|
|
115 |
#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ |
|
116 |
#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ |
|
117 |
|
|
118 |
/* The format of an iopte in the page tables */ |
|
119 |
#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ |
|
120 |
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or |
|
121 |
Viking/MXCC) */ |
|
122 |
#define IOPTE_WRITE 0x00000004 /* Writeable */ |
|
123 |
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
|
124 |
#define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
|
125 |
|
|
126 |
#define IOMMU_PAGE_SHIFT 12 |
|
127 |
#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) |
|
128 |
#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) |
|
129 |
|
|
130 |
typedef struct IOMMUState { |
|
131 |
SysBusDevice busdev; |
|
132 |
uint32_t regs[IOMMU_NREGS]; |
|
133 |
target_phys_addr_t iostart; |
|
134 |
uint32_t version; |
|
135 |
qemu_irq irq; |
|
136 |
} IOMMUState; |
|
137 |
|
|
138 |
static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) |
|
139 |
{ |
|
140 |
IOMMUState *s = opaque; |
|
141 |
target_phys_addr_t saddr; |
|
142 |
uint32_t ret; |
|
143 |
|
|
144 |
saddr = addr >> 2; |
|
145 |
switch (saddr) { |
|
146 |
default: |
|
147 |
ret = s->regs[saddr]; |
|
148 |
break; |
|
149 |
case IOMMU_AFAR: |
|
150 |
case IOMMU_AFSR: |
|
151 |
ret = s->regs[saddr]; |
|
152 |
qemu_irq_lower(s->irq); |
|
153 |
break; |
|
154 |
} |
|
155 |
DPRINTF("read reg[%d] = %x\n", (int)saddr, ret); |
|
156 |
return ret; |
|
157 |
} |
|
158 |
|
|
159 |
static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, |
|
160 |
uint32_t val) |
|
161 |
{ |
|
162 |
IOMMUState *s = opaque; |
|
163 |
target_phys_addr_t saddr; |
|
164 |
|
|
165 |
saddr = addr >> 2; |
|
166 |
DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
|
167 |
switch (saddr) { |
|
168 |
case IOMMU_CTRL: |
|
169 |
switch (val & IOMMU_CTRL_RNGE) { |
|
170 |
case IOMMU_RNGE_16MB: |
|
171 |
s->iostart = 0xffffffffff000000ULL; |
|
172 |
break; |
|
173 |
case IOMMU_RNGE_32MB: |
|
174 |
s->iostart = 0xfffffffffe000000ULL; |
|
175 |
break; |
|
176 |
case IOMMU_RNGE_64MB: |
|
177 |
s->iostart = 0xfffffffffc000000ULL; |
|
178 |
break; |
|
179 |
case IOMMU_RNGE_128MB: |
|
180 |
s->iostart = 0xfffffffff8000000ULL; |
|
181 |
break; |
|
182 |
case IOMMU_RNGE_256MB: |
|
183 |
s->iostart = 0xfffffffff0000000ULL; |
|
184 |
break; |
|
185 |
case IOMMU_RNGE_512MB: |
|
186 |
s->iostart = 0xffffffffe0000000ULL; |
|
187 |
break; |
|
188 |
case IOMMU_RNGE_1GB: |
|
189 |
s->iostart = 0xffffffffc0000000ULL; |
|
190 |
break; |
|
191 |
default: |
|
192 |
case IOMMU_RNGE_2GB: |
|
193 |
s->iostart = 0xffffffff80000000ULL; |
|
194 |
break; |
|
195 |
} |
|
196 |
DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); |
|
197 |
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); |
|
198 |
break; |
|
199 |
case IOMMU_BASE: |
|
200 |
s->regs[saddr] = val & IOMMU_BASE_MASK; |
|
201 |
break; |
|
202 |
case IOMMU_TLBFLUSH: |
|
203 |
DPRINTF("tlb flush %x\n", val); |
|
204 |
s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
|
205 |
break; |
|
206 |
case IOMMU_PGFLUSH: |
|
207 |
DPRINTF("page flush %x\n", val); |
|
208 |
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
|
209 |
break; |
|
210 |
case IOMMU_AFAR: |
|
211 |
s->regs[saddr] = val; |
|
212 |
qemu_irq_lower(s->irq); |
|
213 |
break; |
|
214 |
case IOMMU_AER: |
|
215 |
s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; |
|
216 |
break; |
|
217 |
case IOMMU_AFSR: |
|
218 |
s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; |
|
219 |
qemu_irq_lower(s->irq); |
|
220 |
break; |
|
221 |
case IOMMU_SBCFG0: |
|
222 |
case IOMMU_SBCFG1: |
|
223 |
case IOMMU_SBCFG2: |
|
224 |
case IOMMU_SBCFG3: |
|
225 |
s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
|
226 |
break; |
|
227 |
case IOMMU_ARBEN: |
|
228 |
// XXX implement SBus probing: fault when reading unmapped |
|
229 |
// addresses, fault cause and address stored to MMU/IOMMU |
|
230 |
s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
|
231 |
break; |
|
232 |
case IOMMU_MASK_ID: |
|
233 |
s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; |
|
234 |
break; |
|
235 |
default: |
|
236 |
s->regs[saddr] = val; |
|
237 |
break; |
|
238 |
} |
|
239 |
} |
|
240 |
|
|
241 |
static CPUReadMemoryFunc * const iommu_mem_read[3] = { |
|
242 |
NULL, |
|
243 |
NULL, |
|
244 |
iommu_mem_readl, |
|
245 |
}; |
|
246 |
|
|
247 |
static CPUWriteMemoryFunc * const iommu_mem_write[3] = { |
|
248 |
NULL, |
|
249 |
NULL, |
|
250 |
iommu_mem_writel, |
|
251 |
}; |
|
252 |
|
|
253 |
static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) |
|
254 |
{ |
|
255 |
uint32_t ret; |
|
256 |
target_phys_addr_t iopte; |
|
257 |
#ifdef DEBUG_IOMMU |
|
258 |
target_phys_addr_t pa = addr; |
|
259 |
#endif |
|
260 |
|
|
261 |
iopte = s->regs[IOMMU_BASE] << 4; |
|
262 |
addr &= ~s->iostart; |
|
263 |
iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; |
|
264 |
cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4); |
|
265 |
tswap32s(&ret); |
|
266 |
DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx |
|
267 |
", *pte = %x\n", pa, iopte, ret); |
|
268 |
|
|
269 |
return ret; |
|
270 |
} |
|
271 |
|
|
272 |
static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr, |
|
273 |
uint32_t pte) |
|
274 |
{ |
|
275 |
target_phys_addr_t pa; |
|
276 |
|
|
277 |
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); |
|
278 |
DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx |
|
279 |
" (iopte = %x)\n", addr, pa, pte); |
|
280 |
|
|
281 |
return pa; |
|
282 |
} |
|
283 |
|
|
284 |
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, |
|
285 |
int is_write) |
|
286 |
{ |
|
287 |
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); |
|
288 |
s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | |
|
289 |
IOMMU_AFSR_FAV; |
|
290 |
if (!is_write) |
|
291 |
s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; |
|
292 |
s->regs[IOMMU_AFAR] = addr; |
|
293 |
qemu_irq_raise(s->irq); |
|
294 |
} |
|
295 |
|
|
296 |
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
|
297 |
uint8_t *buf, int len, int is_write) |
|
298 |
{ |
|
299 |
int l; |
|
300 |
uint32_t flags; |
|
301 |
target_phys_addr_t page, phys_addr; |
|
302 |
|
|
303 |
while (len > 0) { |
|
304 |
page = addr & IOMMU_PAGE_MASK; |
|
305 |
l = (page + IOMMU_PAGE_SIZE) - addr; |
|
306 |
if (l > len) |
|
307 |
l = len; |
|
308 |
flags = iommu_page_get_flags(opaque, page); |
|
309 |
if (!(flags & IOPTE_VALID)) { |
|
310 |
iommu_bad_addr(opaque, page, is_write); |
|
311 |
return; |
|
312 |
} |
|
313 |
phys_addr = iommu_translate_pa(addr, flags); |
|
314 |
if (is_write) { |
|
315 |
if (!(flags & IOPTE_WRITE)) { |
|
316 |
iommu_bad_addr(opaque, page, is_write); |
|
317 |
return; |
|
318 |
} |
|
319 |
cpu_physical_memory_write(phys_addr, buf, l); |
|
320 |
} else { |
|
321 |
cpu_physical_memory_read(phys_addr, buf, l); |
|
322 |
} |
|
323 |
len -= l; |
|
324 |
buf += l; |
|
325 |
addr += l; |
|
326 |
} |
|
327 |
} |
|
328 |
|
|
329 |
static const VMStateDescription vmstate_iommu = { |
|
330 |
.name ="iommu", |
|
331 |
.version_id = 2, |
|
332 |
.minimum_version_id = 2, |
|
333 |
.minimum_version_id_old = 2, |
|
334 |
.fields = (VMStateField []) { |
|
335 |
VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS), |
|
336 |
VMSTATE_UINT64(iostart, IOMMUState), |
|
337 |
VMSTATE_END_OF_LIST() |
|
338 |
} |
|
339 |
}; |
|
340 |
|
|
341 |
static void iommu_reset(DeviceState *d) |
|
342 |
{ |
|
343 |
IOMMUState *s = container_of(d, IOMMUState, busdev.qdev); |
|
344 |
|
|
345 |
memset(s->regs, 0, IOMMU_NREGS * 4); |
|
346 |
s->iostart = 0; |
|
347 |
s->regs[IOMMU_CTRL] = s->version; |
|
348 |
s->regs[IOMMU_ARBEN] = IOMMU_MID; |
|
349 |
s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
|
350 |
s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; |
|
351 |
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
|
352 |
} |
|
353 |
|
|
354 |
static int iommu_init1(SysBusDevice *dev) |
|
355 |
{ |
|
356 |
IOMMUState *s = FROM_SYSBUS(IOMMUState, dev); |
|
357 |
int io; |
|
358 |
|
|
359 |
sysbus_init_irq(dev, &s->irq); |
|
360 |
|
|
361 |
io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s); |
|
362 |
sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io); |
|
363 |
|
|
364 |
return 0; |
|
365 |
} |
|
366 |
|
|
367 |
static SysBusDeviceInfo iommu_info = { |
|
368 |
.init = iommu_init1, |
|
369 |
.qdev.name = "iommu", |
|
370 |
.qdev.size = sizeof(IOMMUState), |
|
371 |
.qdev.vmsd = &vmstate_iommu, |
|
372 |
.qdev.reset = iommu_reset, |
|
373 |
.qdev.props = (Property[]) { |
|
374 |
DEFINE_PROP_HEX32("version", IOMMUState, version, 0), |
|
375 |
DEFINE_PROP_END_OF_LIST(), |
|
376 |
} |
|
377 |
}; |
|
378 |
|
|
379 |
static void iommu_register_devices(void) |
|
380 |
{ |
|
381 |
sysbus_register_withprop(&iommu_info); |
|
382 |
} |
|
383 |
|
|
384 |
device_init(iommu_register_devices) |
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