Revision 241cbed4
b/tcg/tcg-op.h | ||
---|---|---|
1650 | 1650 |
|
1651 | 1651 |
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1652 | 1652 |
{ |
1653 |
#ifdef TCG_TARGET_HAS_andc_i32 |
|
1654 |
tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); |
|
1655 |
#else |
|
1653 | 1656 |
TCGv_i32 t0; |
1654 | 1657 |
t0 = tcg_temp_new_i32(); |
1655 | 1658 |
tcg_gen_not_i32(t0, arg2); |
1656 | 1659 |
tcg_gen_and_i32(ret, arg1, t0); |
1657 | 1660 |
tcg_temp_free_i32(t0); |
1661 |
#endif |
|
1658 | 1662 |
} |
1659 | 1663 |
|
1660 | 1664 |
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1661 | 1665 |
{ |
1666 |
#ifdef TCG_TARGET_HAS_andc_i64 |
|
1667 |
tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); |
|
1668 |
#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 |
|
1669 |
tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
|
1670 |
tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
|
1671 |
#else |
|
1662 | 1672 |
TCGv_i64 t0; |
1663 | 1673 |
t0 = tcg_temp_new_i64(); |
1664 | 1674 |
tcg_gen_not_i64(t0, arg2); |
1665 | 1675 |
tcg_gen_and_i64(ret, arg1, t0); |
1666 | 1676 |
tcg_temp_free_i64(t0); |
1677 |
#endif |
|
1667 | 1678 |
} |
1668 | 1679 |
|
1669 | 1680 |
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
b/tcg/tcg-opc.h | ||
---|---|---|
109 | 109 |
#ifdef TCG_TARGET_HAS_neg_i32 |
110 | 110 |
DEF2(neg_i32, 1, 1, 0, 0) |
111 | 111 |
#endif |
112 |
#ifdef TCG_TARGET_HAS_andc_i32 |
|
113 |
DEF2(andc_i32, 1, 2, 0, 0) |
|
114 |
#endif |
|
112 | 115 |
|
113 | 116 |
#if TCG_TARGET_REG_BITS == 64 |
114 | 117 |
DEF2(mov_i64, 1, 1, 0, 0) |
... | ... | |
185 | 188 |
#ifdef TCG_TARGET_HAS_neg_i64 |
186 | 189 |
DEF2(neg_i64, 1, 1, 0, 0) |
187 | 190 |
#endif |
191 |
#ifdef TCG_TARGET_HAS_andc_i64 |
|
192 |
DEF2(andc_i64, 1, 2, 0, 0) |
|
193 |
#endif |
|
188 | 194 |
#endif |
189 | 195 |
|
190 | 196 |
/* QEMU specific */ |
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