Revision 2423f660 target-mips/translate.c

b/target-mips/translate.c
1761 1761
    case 0:
1762 1762
        switch (sel) {
1763 1763
        case 0:
1764
           gen_op_mfc0_index();
1764
            gen_op_mfc0_index();
1765 1765
            rn = "Index";
1766 1766
            break;
1767 1767
        case 1:
1768
//         gen_op_mfc0_mvpcontrol(); /* MT ASE */
1768
//            gen_op_mfc0_mvpcontrol(); /* MT ASE */
1769 1769
            rn = "MVPControl";
1770
//         break;
1770
//            break;
1771 1771
        case 2:
1772
//         gen_op_mfc0_mvpconf0(); /* MT ASE */
1772
//            gen_op_mfc0_mvpconf0(); /* MT ASE */
1773 1773
            rn = "MVPConf0";
1774
//         break;
1774
//            break;
1775 1775
        case 3:
1776
//         gen_op_mfc0_mvpconf1(); /* MT ASE */
1776
//            gen_op_mfc0_mvpconf1(); /* MT ASE */
1777 1777
            rn = "MVPConf1";
1778
//         break;
1778
//            break;
1779 1779
        default:
1780 1780
            goto die;
1781 1781
        }
......
1785 1785
        case 0:
1786 1786
            gen_op_mfc0_random();
1787 1787
            rn = "Random";
1788
           break;
1788
            break;
1789 1789
        case 1:
1790
//         gen_op_mfc0_vpecontrol(); /* MT ASE */
1790
//            gen_op_mfc0_vpecontrol(); /* MT ASE */
1791 1791
            rn = "VPEControl";
1792
//         break;
1792
//            break;
1793 1793
        case 2:
1794
//         gen_op_mfc0_vpeconf0(); /* MT ASE */
1794
//            gen_op_mfc0_vpeconf0(); /* MT ASE */
1795 1795
            rn = "VPEConf0";
1796
//         break;
1796
//            break;
1797 1797
        case 3:
1798
//         gen_op_mfc0_vpeconf1(); /* MT ASE */
1798
//            gen_op_mfc0_vpeconf1(); /* MT ASE */
1799 1799
            rn = "VPEConf1";
1800
//         break;
1800
//            break;
1801 1801
        case 4:
1802
//         gen_op_mfc0_YQMask(); /* MT ASE */
1802
//            gen_op_mfc0_YQMask(); /* MT ASE */
1803 1803
            rn = "YQMask";
1804
//         break;
1804
//            break;
1805 1805
        case 5:
1806
//         gen_op_mfc0_vpeschedule(); /* MT ASE */
1806
//            gen_op_mfc0_vpeschedule(); /* MT ASE */
1807 1807
            rn = "VPESchedule";
1808
//         break;
1808
//            break;
1809 1809
        case 6:
1810
//         gen_op_mfc0_vpeschefback(); /* MT ASE */
1810
//            gen_op_mfc0_vpeschefback(); /* MT ASE */
1811 1811
            rn = "VPEScheFBack";
1812
//         break;
1812
//            break;
1813 1813
        case 7:
1814
//         gen_op_mfc0_vpeopt(); /* MT ASE */
1814
//            gen_op_mfc0_vpeopt(); /* MT ASE */
1815 1815
            rn = "VPEOpt";
1816
//         break;
1816
//            break;
1817 1817
        default:
1818 1818
            goto die;
1819 1819
        }
......
1821 1821
    case 2:
1822 1822
        switch (sel) {
1823 1823
        case 0:
1824
           gen_op_mfc0_entrylo0();
1825
           rn = "EntryLo0";
1826
           break;
1824
            gen_op_mfc0_entrylo0();
1825
            rn = "EntryLo0";
1826
            break;
1827 1827
        case 1:
1828
//         gen_op_mfc0_tcstatus(); /* MT ASE */
1829
           rn = "TCStatus";
1830
//         break;
1828
//            gen_op_mfc0_tcstatus(); /* MT ASE */
1829
            rn = "TCStatus";
1830
//            break;
1831 1831
        case 2:
1832
//         gen_op_mfc0_tcbind(); /* MT ASE */
1833
           rn = "TCBind";
1834
//         break;
1832
//            gen_op_mfc0_tcbind(); /* MT ASE */
1833
            rn = "TCBind";
1834
//            break;
1835 1835
        case 3:
1836
//         gen_op_mfc0_tcrestart(); /* MT ASE */
1837
           rn = "TCRestart";
1838
//         break;
1836
//            gen_op_mfc0_tcrestart(); /* MT ASE */
1837
            rn = "TCRestart";
1838
//            break;
1839 1839
        case 4:
1840
//         gen_op_mfc0_tchalt(); /* MT ASE */
1841
           rn = "TCHalt";
1842
//         break;
1840
//            gen_op_mfc0_tchalt(); /* MT ASE */
1841
            rn = "TCHalt";
1842
//            break;
1843 1843
        case 5:
1844
//         gen_op_mfc0_tccontext(); /* MT ASE */
1845
           rn = "TCContext";
1846
//         break;
1844
//            gen_op_mfc0_tccontext(); /* MT ASE */
1845
            rn = "TCContext";
1846
//            break;
1847 1847
        case 6:
1848
//         gen_op_mfc0_tcschedule(); /* MT ASE */
1849
           rn = "TCSchedule";
1850
//         break;
1848
//            gen_op_mfc0_tcschedule(); /* MT ASE */
1849
            rn = "TCSchedule";
1850
//            break;
1851 1851
        case 7:
1852
//         gen_op_mfc0_tcschefback(); /* MT ASE */
1853
           rn = "TCScheFBack";
1854
//         break;
1852
//            gen_op_mfc0_tcschefback(); /* MT ASE */
1853
            rn = "TCScheFBack";
1854
//            break;
1855 1855
        default:
1856 1856
            goto die;
1857 1857
        }
......
1859 1859
    case 3:
1860 1860
        switch (sel) {
1861 1861
        case 0:
1862
           gen_op_mfc0_entrylo1();
1863
           rn = "EntryLo1";
1864
           break;
1862
            gen_op_mfc0_entrylo1();
1863
            rn = "EntryLo1";
1864
            break;
1865 1865
        default:
1866 1866
            goto die;
1867 1867
        }
......
1869 1869
    case 4:
1870 1870
        switch (sel) {
1871 1871
        case 0:
1872
           gen_op_mfc0_context();
1873
           rn = "Context";
1874
           break;
1872
            gen_op_mfc0_context();
1873
            rn = "Context";
1874
            break;
1875 1875
        case 1:
1876
//         gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
1877
           rn = "ContextConfig";
1878
//         break;
1876
//            gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
1877
            rn = "ContextConfig";
1878
//            break;
1879 1879
        default:
1880 1880
            goto die;
1881 1881
        }
......
1883 1883
    case 5:
1884 1884
        switch (sel) {
1885 1885
        case 0:
1886
           gen_op_mfc0_pagemask();
1887
           rn = "PageMask";
1888
           break;
1886
            gen_op_mfc0_pagemask();
1887
            rn = "PageMask";
1888
            break;
1889 1889
        case 1:
1890
           gen_op_mfc0_pagegrain();
1891
           rn = "PageGrain";
1892
           break;
1890
            gen_op_mfc0_pagegrain();
1891
            rn = "PageGrain";
1892
            break;
1893 1893
        default:
1894 1894
            goto die;
1895 1895
        }
......
1897 1897
    case 6:
1898 1898
        switch (sel) {
1899 1899
        case 0:
1900
           gen_op_mfc0_wired();
1901
           rn = "Wired";
1902
           break;
1900
            gen_op_mfc0_wired();
1901
            rn = "Wired";
1902
            break;
1903 1903
        case 1:
1904
//         gen_op_mfc0_srsconf0(); /* shadow registers */
1905
           rn = "SRSConf0";
1906
//         break;
1904
//            gen_op_mfc0_srsconf0(); /* shadow registers */
1905
            rn = "SRSConf0";
1906
//            break;
1907 1907
        case 2:
1908
//         gen_op_mfc0_srsconf1(); /* shadow registers */
1909
           rn = "SRSConf1";
1910
//         break;
1908
//            gen_op_mfc0_srsconf1(); /* shadow registers */
1909
            rn = "SRSConf1";
1910
//            break;
1911 1911
        case 3:
1912
//         gen_op_mfc0_srsconf2(); /* shadow registers */
1913
           rn = "SRSConf2";
1914
//         break;
1912
//            gen_op_mfc0_srsconf2(); /* shadow registers */
1913
            rn = "SRSConf2";
1914
//            break;
1915 1915
        case 4:
1916
//         gen_op_mfc0_srsconf3(); /* shadow registers */
1917
           rn = "SRSConf3";
1918
//         break;
1916
//            gen_op_mfc0_srsconf3(); /* shadow registers */
1917
            rn = "SRSConf3";
1918
//            break;
1919 1919
        case 5:
1920
//         gen_op_mfc0_srsconf4(); /* shadow registers */
1921
           rn = "SRSConf4";
1922
//         break;
1920
//            gen_op_mfc0_srsconf4(); /* shadow registers */
1921
            rn = "SRSConf4";
1922
//            break;
1923 1923
        default:
1924 1924
            goto die;
1925 1925
        }
......
1927 1927
    case 7:
1928 1928
        switch (sel) {
1929 1929
        case 0:
1930
           gen_op_mfc0_hwrena();
1931
           rn = "HWREna";
1932
           break;
1930
            gen_op_mfc0_hwrena();
1931
            rn = "HWREna";
1932
            break;
1933 1933
        default:
1934 1934
            goto die;
1935 1935
        }
......
1937 1937
    case 8:
1938 1938
        switch (sel) {
1939 1939
        case 0:
1940
           gen_op_mfc0_badvaddr();
1941
           rn = "BadVaddr";
1942
           break;
1940
            gen_op_mfc0_badvaddr();
1941
            rn = "BadVaddr";
1942
            break;
1943 1943
        default:
1944 1944
            goto die;
1945 1945
       }
......
1947 1947
    case 9:
1948 1948
        switch (sel) {
1949 1949
        case 0:
1950
           gen_op_mfc0_count();
1951
           rn = "Count";
1952
           break;
1953
       /* 6,7 are implementation dependent */
1950
            gen_op_mfc0_count();
1951
            rn = "Count";
1952
            break;
1953
        /* 6,7 are implementation dependent */
1954 1954
        default:
1955 1955
            goto die;
1956
       }
1956
        }
1957 1957
        break;
1958 1958
    case 10:
1959 1959
        switch (sel) {
1960 1960
        case 0:
1961
           gen_op_mfc0_entryhi();
1962
           rn = "EntryHi";
1963
           break;
1961
            gen_op_mfc0_entryhi();
1962
            rn = "EntryHi";
1963
            break;
1964 1964
        default:
1965 1965
            goto die;
1966 1966
        }
......
1968 1968
    case 11:
1969 1969
        switch (sel) {
1970 1970
        case 0:
1971
           gen_op_mfc0_compare();
1972
           rn = "Compare";
1973
           break;
1974
       /* 6,7 are implementation dependent */
1971
            gen_op_mfc0_compare();
1972
            rn = "Compare";
1973
            break;
1974
        /* 6,7 are implementation dependent */
1975 1975
        default:
1976 1976
            goto die;
1977
       }
1977
        }
1978 1978
        break;
1979 1979
    case 12:
1980 1980
        switch (sel) {
1981 1981
        case 0:
1982
           gen_op_mfc0_status();
1983
           rn = "Status";
1984
           break;
1982
            gen_op_mfc0_status();
1983
            rn = "Status";
1984
            break;
1985 1985
        case 1:
1986
           gen_op_mfc0_intctl();
1987
           rn = "IntCtl";
1988
           break;
1986
            gen_op_mfc0_intctl();
1987
            rn = "IntCtl";
1988
            break;
1989 1989
        case 2:
1990
           gen_op_mfc0_srsctl();
1991
           rn = "SRSCtl";
1992
           break;
1990
            gen_op_mfc0_srsctl();
1991
            rn = "SRSCtl";
1992
            break;
1993 1993
        case 3:
1994
//         gen_op_mfc0_srsmap(); /* shadow registers */
1995
           rn = "SRSMap";
1996
//         break;
1994
//            gen_op_mfc0_srsmap(); /* shadow registers */
1995
            rn = "SRSMap";
1996
//            break;
1997 1997
        default:
1998 1998
            goto die;
1999 1999
       }
......
2001 2001
    case 13:
2002 2002
        switch (sel) {
2003 2003
        case 0:
2004
           gen_op_mfc0_cause();
2005
           rn = "Cause";
2006
           break;
2004
            gen_op_mfc0_cause();
2005
            rn = "Cause";
2006
            break;
2007 2007
        default:
2008 2008
            goto die;
2009 2009
       }
......
2011 2011
    case 14:
2012 2012
        switch (sel) {
2013 2013
        case 0:
2014
           gen_op_mfc0_epc();
2015
           rn = "EPC";
2016
           break;
2014
            gen_op_mfc0_epc();
2015
            rn = "EPC";
2016
            break;
2017 2017
        default:
2018 2018
            goto die;
2019 2019
        }
......
2021 2021
    case 15:
2022 2022
        switch (sel) {
2023 2023
        case 0:
2024
           gen_op_mfc0_prid();
2025
           rn = "PRid";
2026
           break;
2024
            gen_op_mfc0_prid();
2025
            rn = "PRid";
2026
            break;
2027 2027
        case 1:
2028
           gen_op_mfc0_ebase();
2029
           rn = "EBase";
2030
           break;
2028
            gen_op_mfc0_ebase();
2029
            rn = "EBase";
2030
            break;
2031 2031
        default:
2032 2032
            goto die;
2033 2033
       }
......
2067 2067
    case 17:
2068 2068
        switch (sel) {
2069 2069
        case 0:
2070
           gen_op_mfc0_lladdr();
2071
           rn = "LLAddr";
2072
           break;
2070
            gen_op_mfc0_lladdr();
2071
            rn = "LLAddr";
2072
            break;
2073 2073
        default:
2074 2074
            goto die;
2075 2075
        }
......
2077 2077
    case 18:
2078 2078
        switch (sel) {
2079 2079
        case 0:
2080
           gen_op_mfc0_watchlo0();
2081
           rn = "WatchLo";
2082
           break;
2080
            gen_op_mfc0_watchlo0();
2081
            rn = "WatchLo";
2082
            break;
2083 2083
        case 1:
2084
//         gen_op_mfc0_watchlo1();
2085
           rn = "WatchLo1";
2086
//         break;
2084
//            gen_op_mfc0_watchlo1();
2085
            rn = "WatchLo1";
2086
//            break;
2087 2087
        case 2:
2088
//         gen_op_mfc0_watchlo2();
2089
           rn = "WatchLo2";
2090
//         break;
2088
//            gen_op_mfc0_watchlo2();
2089
            rn = "WatchLo2";
2090
//            break;
2091 2091
        case 3:
2092
//         gen_op_mfc0_watchlo3();
2093
           rn = "WatchLo3";
2094
//         break;
2092
//            gen_op_mfc0_watchlo3();
2093
            rn = "WatchLo3";
2094
//            break;
2095 2095
        case 4:
2096
//         gen_op_mfc0_watchlo4();
2097
           rn = "WatchLo4";
2098
//         break;
2096
//            gen_op_mfc0_watchlo4();
2097
            rn = "WatchLo4";
2098
//            break;
2099 2099
        case 5:
2100
//         gen_op_mfc0_watchlo5();
2101
           rn = "WatchLo5";
2102
//         break;
2100
//            gen_op_mfc0_watchlo5();
2101
            rn = "WatchLo5";
2102
//            break;
2103 2103
        case 6:
2104
//         gen_op_mfc0_watchlo6();
2105
           rn = "WatchLo6";
2106
//         break;
2104
//            gen_op_mfc0_watchlo6();
2105
            rn = "WatchLo6";
2106
//            break;
2107 2107
        case 7:
2108
//         gen_op_mfc0_watchlo7();
2109
           rn = "WatchLo7";
2110
//         break;
2108
//            gen_op_mfc0_watchlo7();
2109
            rn = "WatchLo7";
2110
//            break;
2111 2111
        default:
2112 2112
            goto die;
2113 2113
        }
......
2115 2115
    case 19:
2116 2116
        switch (sel) {
2117 2117
        case 0:
2118
           gen_op_mfc0_watchhi0();
2119
           rn = "WatchHi";
2120
           break;
2118
            gen_op_mfc0_watchhi0();
2119
            rn = "WatchHi";
2120
            break;
2121 2121
        case 1:
2122
//         gen_op_mfc0_watchhi1();
2123
           rn = "WatchHi1";
2124
//         break;
2122
//            gen_op_mfc0_watchhi1();
2123
            rn = "WatchHi1";
2124
//            break;
2125 2125
        case 2:
2126
//         gen_op_mfc0_watchhi2();
2127
           rn = "WatchHi2";
2128
//         break;
2126
//            gen_op_mfc0_watchhi2();
2127
            rn = "WatchHi2";
2128
//            break;
2129 2129
        case 3:
2130
//         gen_op_mfc0_watchhi3();
2131
           rn = "WatchHi3";
2132
//         break;
2130
//            gen_op_mfc0_watchhi3();
2131
            rn = "WatchHi3";
2132
//            break;
2133 2133
        case 4:
2134
//         gen_op_mfc0_watchhi4();
2135
           rn = "WatchHi4";
2136
//         break;
2134
//            gen_op_mfc0_watchhi4();
2135
            rn = "WatchHi4";
2136
//            break;
2137 2137
        case 5:
2138
//         gen_op_mfc0_watchhi5();
2139
           rn = "WatchHi5";
2140
//         break;
2138
//            gen_op_mfc0_watchhi5();
2139
            rn = "WatchHi5";
2140
//            break;
2141 2141
        case 6:
2142
//         gen_op_mfc0_watchhi6();
2143
           rn = "WatchHi6";
2144
//         break;
2142
//            gen_op_mfc0_watchhi6();
2143
            rn = "WatchHi6";
2144
//            break;
2145 2145
        case 7:
2146
//         gen_op_mfc0_watchhi7();
2147
           rn = "WatchHi7";
2148
//         break;
2146
//            gen_op_mfc0_watchhi7();
2147
            rn = "WatchHi7";
2148
//            break;
2149 2149
        default:
2150 2150
            goto die;
2151 2151
        }
......
2153 2153
    case 20:
2154 2154
        switch (sel) {
2155 2155
        case 0:
2156
           /* 64 bit MMU only */
2157
           gen_op_mfc0_xcontext();
2158
           rn = "XContext";
2159
           break;
2156
            /* 64 bit MMU only */
2157
            gen_op_mfc0_xcontext();
2158
            rn = "XContext";
2159
            break;
2160 2160
        default:
2161 2161
            goto die;
2162 2162
        }
......
2165 2165
       /* Officially reserved, but sel 0 is used for R1x000 framemask */
2166 2166
        switch (sel) {
2167 2167
        case 0:
2168
           gen_op_mfc0_framemask();
2169
           rn = "Framemask";
2170
           break;
2168
            gen_op_mfc0_framemask();
2169
            rn = "Framemask";
2170
            break;
2171 2171
        default:
2172 2172
            goto die;
2173 2173
        }
2174 2174
        break;
2175 2175
    case 22:
2176
       /* ignored */
2177
       rn = "'Diagnostic"; /* implementation dependent */
2178
       break;
2176
        /* ignored */
2177
        rn = "'Diagnostic"; /* implementation dependent */
2178
        break;
2179 2179
    case 23:
2180 2180
        switch (sel) {
2181 2181
        case 0:
2182
           gen_op_mfc0_debug(); /* EJTAG support */
2183
           rn = "Debug";
2184
           break;
2182
            gen_op_mfc0_debug(); /* EJTAG support */
2183
            rn = "Debug";
2184
            break;
2185 2185
        case 1:
2186
//         gen_op_mfc0_tracecontrol(); /* PDtrace support */
2187
           rn = "TraceControl";
2188
//         break;
2186
//            gen_op_mfc0_tracecontrol(); /* PDtrace support */
2187
            rn = "TraceControl";
2188
//            break;
2189 2189
        case 2:
2190
//         gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2191
           rn = "TraceControl2";
2192
//         break;
2190
//            gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2191
            rn = "TraceControl2";
2192
//            break;
2193 2193
        case 3:
2194
//         gen_op_mfc0_usertracedata(); /* PDtrace support */
2195
           rn = "UserTraceData";
2196
//         break;
2194
//            gen_op_mfc0_usertracedata(); /* PDtrace support */
2195
            rn = "UserTraceData";
2196
//            break;
2197 2197
        case 4:
2198
//         gen_op_mfc0_debug(); /* PDtrace support */
2199
           rn = "TraceBPC";
2200
//         break;
2198
//            gen_op_mfc0_debug(); /* PDtrace support */
2199
            rn = "TraceBPC";
2200
//            break;
2201 2201
        default:
2202 2202
            goto die;
2203 2203
        }
......
2205 2205
    case 24:
2206 2206
        switch (sel) {
2207 2207
        case 0:
2208
           gen_op_mfc0_depc(); /* EJTAG support */
2209
           rn = "DEPC";
2210
           break;
2208
            gen_op_mfc0_depc(); /* EJTAG support */
2209
            rn = "DEPC";
2210
            break;
2211 2211
        default:
2212 2212
            goto die;
2213 2213
        }
......
2215 2215
    case 25:
2216 2216
        switch (sel) {
2217 2217
        case 0:
2218
           gen_op_mfc0_performance0();
2219
           rn = "Performance0";
2218
            gen_op_mfc0_performance0();
2219
            rn = "Performance0";
2220 2220
            break;
2221 2221
        case 1:
2222
//         gen_op_mfc0_performance1();
2223
           rn = "Performance1";
2224
//         break;
2222
//            gen_op_mfc0_performance1();
2223
            rn = "Performance1";
2224
//            break;
2225 2225
        case 2:
2226
//         gen_op_mfc0_performance2();
2227
           rn = "Performance2";
2228
//         break;
2226
//            gen_op_mfc0_performance2();
2227
            rn = "Performance2";
2228
//            break;
2229 2229
        case 3:
2230
//         gen_op_mfc0_performance3();
2231
           rn = "Performance3";
2232
//         break;
2230
//            gen_op_mfc0_performance3();
2231
            rn = "Performance3";
2232
//            break;
2233 2233
        case 4:
2234
//         gen_op_mfc0_performance4();
2235
           rn = "Performance4";
2236
//         break;
2234
//            gen_op_mfc0_performance4();
2235
            rn = "Performance4";
2236
//            break;
2237 2237
        case 5:
2238
//         gen_op_mfc0_performance5();
2239
           rn = "Performance5";
2240
//         break;
2238
//            gen_op_mfc0_performance5();
2239
            rn = "Performance5";
2240
//            break;
2241 2241
        case 6:
2242
//         gen_op_mfc0_performance6();
2243
           rn = "Performance6";
2244
//         break;
2242
//            gen_op_mfc0_performance6();
2243
            rn = "Performance6";
2244
//            break;
2245 2245
        case 7:
2246
//         gen_op_mfc0_performance7();
2247
           rn = "Performance7";
2248
//         break;
2246
//            gen_op_mfc0_performance7();
2247
            rn = "Performance7";
2248
//            break;
2249 2249
        default:
2250 2250
            goto die;
2251 2251
        }
......
2257 2257
        switch (sel) {
2258 2258
        /* ignored */
2259 2259
        case 0 ... 3:
2260
           rn = "CacheErr";
2261
           break;
2260
            rn = "CacheErr";
2261
            break;
2262 2262
        default:
2263 2263
            goto die;
2264 2264
        }
......
2306 2306
    case 30:
2307 2307
        switch (sel) {
2308 2308
        case 0:
2309
           gen_op_mfc0_errorepc();
2310
           rn = "ErrorEPC";
2311
           break;
2309
            gen_op_mfc0_errorepc();
2310
            rn = "ErrorEPC";
2311
            break;
2312 2312
        default:
2313 2313
            goto die;
2314 2314
        }
......
2316 2316
    case 31:
2317 2317
        switch (sel) {
2318 2318
        case 0:
2319
           gen_op_mfc0_desave(); /* EJTAG support */
2320
           rn = "DESAVE";
2321
           break;
2319
            gen_op_mfc0_desave(); /* EJTAG support */
2320
            rn = "DESAVE";
2321
            break;
2322 2322
        default:
2323 2323
            goto die;
2324 2324
        }
......
2356 2356
            rn = "Index";
2357 2357
            break;
2358 2358
        case 1:
2359
//         gen_op_mtc0_mvpcontrol(); /* MT ASE */
2359
//            gen_op_mtc0_mvpcontrol(); /* MT ASE */
2360 2360
            rn = "MVPControl";
2361
//         break;
2361
//            break;
2362 2362
        case 2:
2363
//         gen_op_mtc0_mvpconf0(); /* MT ASE */
2363
//            gen_op_mtc0_mvpconf0(); /* MT ASE */
2364 2364
            rn = "MVPConf0";
2365
//         break;
2365
//            break;
2366 2366
        case 3:
2367
//         gen_op_mtc0_mvpconf1(); /* MT ASE */
2367
//            gen_op_mtc0_mvpconf1(); /* MT ASE */
2368 2368
            rn = "MVPConf1";
2369
//         break;
2369
//            break;
2370 2370
        default:
2371 2371
            goto die;
2372 2372
        }
......
2374 2374
    case 1:
2375 2375
        switch (sel) {
2376 2376
        case 0:
2377
           /* ignored */
2377
            /* ignored */
2378 2378
            rn = "Random";
2379
           break;
2379
            break;
2380 2380
        case 1:
2381
//         gen_op_mtc0_vpecontrol(); /* MT ASE */
2381
//            gen_op_mtc0_vpecontrol(); /* MT ASE */
2382 2382
            rn = "VPEControl";
2383
//         break;
2383
//            break;
2384 2384
        case 2:
2385
//         gen_op_mtc0_vpeconf0(); /* MT ASE */
2385
//            gen_op_mtc0_vpeconf0(); /* MT ASE */
2386 2386
            rn = "VPEConf0";
2387
//         break;
2387
//            break;
2388 2388
        case 3:
2389
//         gen_op_mtc0_vpeconf1(); /* MT ASE */
2389
//            gen_op_mtc0_vpeconf1(); /* MT ASE */
2390 2390
            rn = "VPEConf1";
2391
//         break;
2391
//            break;
2392 2392
        case 4:
2393
//         gen_op_mtc0_YQMask(); /* MT ASE */
2393
//            gen_op_mtc0_YQMask(); /* MT ASE */
2394 2394
            rn = "YQMask";
2395
//         break;
2395
//            break;
2396 2396
        case 5:
2397
//         gen_op_mtc0_vpeschedule(); /* MT ASE */
2397
//            gen_op_mtc0_vpeschedule(); /* MT ASE */
2398 2398
            rn = "VPESchedule";
2399
//         break;
2399
//            break;
2400 2400
        case 6:
2401
//         gen_op_mtc0_vpeschefback(); /* MT ASE */
2401
//            gen_op_mtc0_vpeschefback(); /* MT ASE */
2402 2402
            rn = "VPEScheFBack";
2403
//         break;
2403
//            break;
2404 2404
        case 7:
2405
//         gen_op_mtc0_vpeopt(); /* MT ASE */
2405
//            gen_op_mtc0_vpeopt(); /* MT ASE */
2406 2406
            rn = "VPEOpt";
2407
//         break;
2407
//            break;
2408 2408
        default:
2409 2409
            goto die;
2410 2410
        }
......
2412 2412
    case 2:
2413 2413
        switch (sel) {
2414 2414
        case 0:
2415
           gen_op_mtc0_entrylo0();
2416
           rn = "EntryLo0";
2417
           break;
2415
            gen_op_mtc0_entrylo0();
2416
            rn = "EntryLo0";
2417
            break;
2418 2418
        case 1:
2419
//         gen_op_mtc0_tcstatus(); /* MT ASE */
2420
           rn = "TCStatus";
2421
//         break;
2419
//            gen_op_mtc0_tcstatus(); /* MT ASE */
2420
            rn = "TCStatus";
2421
//            break;
2422 2422
        case 2:
2423
//         gen_op_mtc0_tcbind(); /* MT ASE */
2424
           rn = "TCBind";
2425
//         break;
2423
//            gen_op_mtc0_tcbind(); /* MT ASE */
2424
            rn = "TCBind";
2425
//            break;
2426 2426
        case 3:
2427
//         gen_op_mtc0_tcrestart(); /* MT ASE */
2428
           rn = "TCRestart";
2429
//         break;
2427
//            gen_op_mtc0_tcrestart(); /* MT ASE */
2428
            rn = "TCRestart";
2429
//            break;
2430 2430
        case 4:
2431
//         gen_op_mtc0_tchalt(); /* MT ASE */
2432
           rn = "TCHalt";
2433
//         break;
2431
//            gen_op_mtc0_tchalt(); /* MT ASE */
2432
            rn = "TCHalt";
2433
//            break;
2434 2434
        case 5:
2435
//         gen_op_mtc0_tccontext(); /* MT ASE */
2436
           rn = "TCContext";
2437
//         break;
2435
//            gen_op_mtc0_tccontext(); /* MT ASE */
2436
            rn = "TCContext";
2437
//            break;
2438 2438
        case 6:
2439
//         gen_op_mtc0_tcschedule(); /* MT ASE */
2440
           rn = "TCSchedule";
2441
//         break;
2439
//            gen_op_mtc0_tcschedule(); /* MT ASE */
2440
            rn = "TCSchedule";
2441
//            break;
2442 2442
        case 7:
2443
//         gen_op_mtc0_tcschefback(); /* MT ASE */
2444
           rn = "TCScheFBack";
2445
//         break;
2443
//            gen_op_mtc0_tcschefback(); /* MT ASE */
2444
            rn = "TCScheFBack";
2445
//            break;
2446 2446
        default:
2447 2447
            goto die;
2448 2448
        }
......
2450 2450
    case 3:
2451 2451
        switch (sel) {
2452 2452
        case 0:
2453
           gen_op_mtc0_entrylo1();
2454
           rn = "EntryLo1";
2455
           break;
2453
            gen_op_mtc0_entrylo1();
2454
            rn = "EntryLo1";
2455
            break;
2456 2456
        default:
2457 2457
            goto die;
2458 2458
        }
......
2460 2460
    case 4:
2461 2461
        switch (sel) {
2462 2462
        case 0:
2463
           gen_op_mtc0_context();
2464
           rn = "Context";
2465
           break;
2463
            gen_op_mtc0_context();
2464
            rn = "Context";
2465
            break;
2466 2466
        case 1:
2467
//         gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2468
           rn = "ContextConfig";
2469
//         break;
2467
//            gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2468
            rn = "ContextConfig";
2469
//            break;
2470 2470
        default:
2471 2471
            goto die;
2472 2472
        }
......
2474 2474
    case 5:
2475 2475
        switch (sel) {
2476 2476
        case 0:
2477
           gen_op_mtc0_pagemask();
2478
           rn = "PageMask";
2479
           break;
2477
            gen_op_mtc0_pagemask();
2478
            rn = "PageMask";
2479
            break;
2480 2480
        case 1:
2481
           gen_op_mtc0_pagegrain();
2482
           rn = "PageGrain";
2483
           break;
2481
            gen_op_mtc0_pagegrain();
2482
            rn = "PageGrain";
2483
            break;
2484 2484
        default:
2485 2485
            goto die;
2486 2486
        }
......
2488 2488
    case 6:
2489 2489
        switch (sel) {
2490 2490
        case 0:
2491
           gen_op_mtc0_wired();
2492
           rn = "Wired";
2493
           break;
2491
            gen_op_mtc0_wired();
2492
            rn = "Wired";
2493
            break;
2494 2494
        case 1:
2495
//         gen_op_mtc0_srsconf0(); /* shadow registers */
2496
           rn = "SRSConf0";
2497
//         break;
2495
//            gen_op_mtc0_srsconf0(); /* shadow registers */
2496
            rn = "SRSConf0";
2497
//            break;
2498 2498
        case 2:
2499
//         gen_op_mtc0_srsconf1(); /* shadow registers */
2500
           rn = "SRSConf1";
2501
//         break;
2499
//            gen_op_mtc0_srsconf1(); /* shadow registers */
2500
            rn = "SRSConf1";
2501
//            break;
2502 2502
        case 3:
2503
//         gen_op_mtc0_srsconf2(); /* shadow registers */
2504
           rn = "SRSConf2";
2505
//         break;
2503
//            gen_op_mtc0_srsconf2(); /* shadow registers */
2504
            rn = "SRSConf2";
2505
//            break;
2506 2506
        case 4:
2507
//         gen_op_mtc0_srsconf3(); /* shadow registers */
2508
           rn = "SRSConf3";
2509
//         break;
2507
//            gen_op_mtc0_srsconf3(); /* shadow registers */
2508
            rn = "SRSConf3";
2509
//            break;
2510 2510
        case 5:
2511
//         gen_op_mtc0_srsconf4(); /* shadow registers */
2512
           rn = "SRSConf4";
2513
//         break;
2511
//            gen_op_mtc0_srsconf4(); /* shadow registers */
2512
            rn = "SRSConf4";
2513
//            break;
2514 2514
        default:
2515 2515
            goto die;
2516 2516
        }
......
2518 2518
    case 7:
2519 2519
        switch (sel) {
2520 2520
        case 0:
2521
           gen_op_mtc0_hwrena();
2522
           rn = "HWREna";
2523
           break;
2521
            gen_op_mtc0_hwrena();
2522
            rn = "HWREna";
2523
            break;
2524 2524
        default:
2525 2525
            goto die;
2526 2526
        }
......
2532 2532
    case 9:
2533 2533
        switch (sel) {
2534 2534
        case 0:
2535
           gen_op_mtc0_count();
2536
           rn = "Count";
2537
           break;
2535
            gen_op_mtc0_count();
2536
            rn = "Count";
2537
            break;
2538 2538
        /* 6,7 are implementation dependent */
2539 2539
        default:
2540 2540
            goto die;
......
2545 2545
    case 10:
2546 2546
        switch (sel) {
2547 2547
        case 0:
2548
           gen_op_mtc0_entryhi();
2549
           rn = "EntryHi";
2550
           break;
2548
            gen_op_mtc0_entryhi();
2549
            rn = "EntryHi";
2550
            break;
2551 2551
        default:
2552 2552
            goto die;
2553 2553
        }
......
2555 2555
    case 11:
2556 2556
        switch (sel) {
2557 2557
        case 0:
2558
           gen_op_mtc0_compare();
2559
           rn = "Compare";
2560
           break;
2561
       /* 6,7 are implementation dependent */
2558
            gen_op_mtc0_compare();
2559
            rn = "Compare";
2560
            break;
2561
        /* 6,7 are implementation dependent */
2562 2562
        default:
2563 2563
            goto die;
2564 2564
        }
......
2568 2568
    case 12:
2569 2569
        switch (sel) {
2570 2570
        case 0:
2571
           gen_op_mtc0_status();
2572
           rn = "Status";
2573
           break;
2571
            gen_op_mtc0_status();
2572
            rn = "Status";
2573
            break;
2574 2574
        case 1:
2575
           gen_op_mtc0_intctl();
2576
           rn = "IntCtl";
2577
           break;
2575
            gen_op_mtc0_intctl();
2576
            rn = "IntCtl";
2577
            break;
2578 2578
        case 2:
2579
           gen_op_mtc0_srsctl();
2580
           rn = "SRSCtl";
2581
           break;
2579
            gen_op_mtc0_srsctl();
2580
            rn = "SRSCtl";
2581
            break;
2582 2582
        case 3:
2583
//         gen_op_mtc0_srsmap(); /* shadow registers */
2584
           rn = "SRSMap";
2585
//         break;
2583
//            gen_op_mtc0_srsmap(); /* shadow registers */
2584
            rn = "SRSMap";
2585
//            break;
2586 2586
        default:
2587 2587
            goto die;
2588 2588
        }
......
2592 2592
    case 13:
2593 2593
        switch (sel) {
2594 2594
        case 0:
2595
           gen_op_mtc0_cause();
2596
           rn = "Cause";
2597
           break;
2595
            gen_op_mtc0_cause();
2596
            rn = "Cause";
2597
            break;
2598 2598
        default:
2599 2599
            goto die;
2600 2600
        }
......
2604 2604
    case 14:
2605 2605
        switch (sel) {
2606 2606
        case 0:
2607
           gen_op_mtc0_epc();
2608
           rn = "EPC";
2609
           break;
2607
            gen_op_mtc0_epc();
2608
            rn = "EPC";
2609
            break;
2610 2610
        default:
2611 2611
            goto die;
2612 2612
        }
......
2614 2614
    case 15:
2615 2615
        switch (sel) {
2616 2616
        case 0:
2617
           /* ignored */
2618
           rn = "PRid";
2619
           break;
2617
            /* ignored */
2618
            rn = "PRid";
2619
            break;
2620 2620
        case 1:
2621
           gen_op_mtc0_ebase();
2622
           rn = "EBase";
2623
           break;
2621
            gen_op_mtc0_ebase();
2622
            rn = "EBase";
2623
            break;
2624 2624
        default:
2625 2625
            goto die;
2626 2626
        }
......
2630 2630
        case 0:
2631 2631
            gen_op_mtc0_config0();
2632 2632
            rn = "Config";
2633
            /* Stop translation as we may have switched the execution mode */
2634
            ctx->bstate = BS_STOP;
2633 2635
            break;
2634 2636
        case 1:
2635 2637
            /* ignored, read only */
......
2638 2640
        case 2:
2639 2641
            gen_op_mtc0_config2();
2640 2642
            rn = "Config2";
2643
            /* Stop translation as we may have switched the execution mode */
2644
            ctx->bstate = BS_STOP;
2641 2645
            break;
2642 2646
        case 3:
2643 2647
            /* ignored, read only */
......
2657 2661
            rn = "Invalid config selector";
2658 2662
            goto die;
2659 2663
        }
2660
        /* Stop translation as we may have switched the execution mode */
2661
        ctx->bstate = BS_STOP;
2662 2664
        break;
2663 2665
    case 17:
2664 2666
        switch (sel) {
2665 2667
        case 0:
2666
           /* ignored */
2667
           rn = "LLAddr";
2668
           break;
2668
            /* ignored */
2669
            rn = "LLAddr";
2670
            break;
2669 2671
        default:
2670 2672
            goto die;
2671 2673
        }
......
2673 2675
    case 18:
2674 2676
        switch (sel) {
2675 2677
        case 0:
2676
           gen_op_mtc0_watchlo0();
2677
           rn = "WatchLo";
2678
           break;
2678
            gen_op_mtc0_watchlo0();
2679
            rn = "WatchLo";
2680
            break;
2679 2681
        case 1:
2680
//         gen_op_mtc0_watchlo1();
2681
           rn = "WatchLo1";
2682
//         break;
2682
//            gen_op_mtc0_watchlo1();
2683
            rn = "WatchLo1";
2684
//            break;
2683 2685
        case 2:
2684
//         gen_op_mtc0_watchlo2();
2685
           rn = "WatchLo2";
2686
//         break;
2686
//            gen_op_mtc0_watchlo2();
2687
            rn = "WatchLo2";
2688
//            break;
2687 2689
        case 3:
2688
//         gen_op_mtc0_watchlo3();
2689
           rn = "WatchLo3";
2690
//         break;
2690
//            gen_op_mtc0_watchlo3();
2691
            rn = "WatchLo3";
2692
//            break;
2691 2693
        case 4:
2692
//         gen_op_mtc0_watchlo4();
2693
           rn = "WatchLo4";
2694
//         break;
2694
//            gen_op_mtc0_watchlo4();
2695
            rn = "WatchLo4";
2696
//            break;
2695 2697
        case 5:
2696
//         gen_op_mtc0_watchlo5();
2697
           rn = "WatchLo5";
2698
//         break;
2698
//            gen_op_mtc0_watchlo5();
2699
            rn = "WatchLo5";
2700
//            break;
2699 2701
        case 6:
2700
//         gen_op_mtc0_watchlo6();
2701
           rn = "WatchLo6";
2702
//         break;
2702
//            gen_op_mtc0_watchlo6();
2703
            rn = "WatchLo6";
2704
//            break;
2703 2705
        case 7:
2704
//         gen_op_mtc0_watchlo7();
2705
           rn = "WatchLo7";
2706
//         break;
2706
//            gen_op_mtc0_watchlo7();
2707
            rn = "WatchLo7";
2708
//            break;
2707 2709
        default:
2708 2710
            goto die;
2709 2711
        }
......
2711 2713
    case 19:
2712 2714
        switch (sel) {
2713 2715
        case 0:
2714
           gen_op_mtc0_watchhi0();
2715
           rn = "WatchHi";
2716
           break;
2716
            gen_op_mtc0_watchhi0();
2717
            rn = "WatchHi";
2718
            break;
2717 2719
        case 1:
2718
//         gen_op_mtc0_watchhi1();
2719
           rn = "WatchHi1";
2720
//         break;
2720
//            gen_op_mtc0_watchhi1();
2721
            rn = "WatchHi1";
2722
//            break;
2721 2723
        case 2:
2722
//         gen_op_mtc0_watchhi2();
2723
           rn = "WatchHi2";
2724
//         break;
2724
//            gen_op_mtc0_watchhi2();
2725
            rn = "WatchHi2";
2726
//            break;
2725 2727
        case 3:
2726
//         gen_op_mtc0_watchhi3();
2727
           rn = "WatchHi3";
2728
//         break;
2728
//            gen_op_mtc0_watchhi3();
2729
            rn = "WatchHi3";
2730
//            break;
2729 2731
        case 4:
2730
//         gen_op_mtc0_watchhi4();
2731
           rn = "WatchHi4";
2732
//         break;
2732
//            gen_op_mtc0_watchhi4();
2733
            rn = "WatchHi4";
2734
//            break;
2733 2735
        case 5:
2734
//         gen_op_mtc0_watchhi5();
2735
           rn = "WatchHi5";
2736
//         break;
2736
//            gen_op_mtc0_watchhi5();
2737
            rn = "WatchHi5";
2738
//            break;
2737 2739
        case 6:
2738
//         gen_op_mtc0_watchhi6();
2739
           rn = "WatchHi6";
2740
//         break;
2740
//            gen_op_mtc0_watchhi6();
2741
            rn = "WatchHi6";
2742
//            break;
2741 2743
        case 7:
2742
//         gen_op_mtc0_watchhi7();
2743
           rn = "WatchHi7";
2744
//         break;
2744
//            gen_op_mtc0_watchhi7();
2745
            rn = "WatchHi7";
2746
//            break;
2745 2747
        default:
2746 2748
            goto die;
2747 2749
        }
......
2749 2751
    case 20:
2750 2752
        switch (sel) {
2751 2753
        case 0:
2752
           /* 64 bit MMU only */
2753
           /* Nothing writable in lower 32 bits */
2754
           rn = "XContext";
2755
           break;
2754
            /* 64 bit MMU only */
2755
            /* Nothing writable in lower 32 bits */
2756
            rn = "XContext";
2757
            break;
2756 2758
        default:
2757 2759
            goto die;
2758 2760
        }
......
2761 2763
       /* Officially reserved, but sel 0 is used for R1x000 framemask */
2762 2764
        switch (sel) {
2763 2765
        case 0:
2764
           gen_op_mtc0_framemask();
2765
           rn = "Framemask";
2766
           break;
2766
            gen_op_mtc0_framemask();
2767
            rn = "Framemask";
2768
            break;
2767 2769
        default:
2768 2770
            goto die;
2769 2771
        }
......
2771 2773
    case 22:
2772 2774
        /* ignored */
2773 2775
        rn = "Diagnostic"; /* implementation dependent */
2774
       break;
2776
        break;
2775 2777
    case 23:
2776 2778
        switch (sel) {
2777 2779
        case 0:
2778
           gen_op_mtc0_debug(); /* EJTAG support */
2779
           rn = "Debug";
2780
           break;
2780
            gen_op_mtc0_debug(); /* EJTAG support */
2781
            rn = "Debug";
2782
            break;
2781 2783
        case 1:
2782
//         gen_op_mtc0_tracecontrol(); /* PDtrace support */
2783
           rn = "TraceControl";
2784
//         break;
2784
//            gen_op_mtc0_tracecontrol(); /* PDtrace support */
2785
            rn = "TraceControl";
2786
//            break;
2785 2787
        case 2:
2786
//         gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2787
           rn = "TraceControl2";
2788
//         break;
2788
//            gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2789
            rn = "TraceControl2";
2790
//            break;
2789 2791
        case 3:
2790
//         gen_op_mtc0_usertracedata(); /* PDtrace support */
2791
           rn = "UserTraceData";
2792
//         break;
2792
//            gen_op_mtc0_usertracedata(); /* PDtrace support */
2793
            rn = "UserTraceData";
2794
//            break;
2793 2795
        case 4:
2794
//         gen_op_mtc0_debug(); /* PDtrace support */
2795
           rn = "TraceBPC";
2796
//         break;
2796
//            gen_op_mtc0_debug(); /* PDtrace support */
2797
            rn = "TraceBPC";
2798
//            break;
2797 2799
        default:
2798 2800
            goto die;
2799 2801
        }
2800
       /* Stop translation as we may have switched the execution mode */
2801
       ctx->bstate = BS_STOP;
2802
        /* Stop translation as we may have switched the execution mode */
2803
        ctx->bstate = BS_STOP;
2802 2804
        break;
2803 2805
    case 24:
2804 2806
        switch (sel) {
2805 2807
        case 0:
2806
           gen_op_mtc0_depc(); /* EJTAG support */
2807
           rn = "DEPC";
2808
           break;
2808
            gen_op_mtc0_depc(); /* EJTAG support */
2809
            rn = "DEPC";
2810
            break;
2809 2811
        default:
2810 2812
            goto die;
2811 2813
        }
......
2813 2815
    case 25:
2814 2816
        switch (sel) {
2815 2817
        case 0:
2816
           gen_op_mtc0_performance0();
2817
           rn = "Performance0";
2818
           break;
2818
            gen_op_mtc0_performance0();
2819
            rn = "Performance0";
2820
            break;
2819 2821
        case 1:
2820
//         gen_op_mtc0_performance1();
2821
           rn = "Performance1";
2822
//         break;
2822
//            gen_op_mtc0_performance1();
2823
            rn = "Performance1";
2824
//            break;
2823 2825
        case 2:
2824
//         gen_op_mtc0_performance2();
2825
           rn = "Performance2";
2826
//         break;
2826
//            gen_op_mtc0_performance2();
2827
            rn = "Performance2";
2828
//            break;
2827 2829
        case 3:
2828
//         gen_op_mtc0_performance3();
2829
           rn = "Performance3";
2830
//         break;
2830
//            gen_op_mtc0_performance3();
2831
            rn = "Performance3";
2832
//            break;
2831 2833
        case 4:
2832
//         gen_op_mtc0_performance4();
2833
           rn = "Performance4";
2834
//         break;
2834
//            gen_op_mtc0_performance4();
2835
            rn = "Performance4";
2836
//            break;
2835 2837
        case 5:
2836
//         gen_op_mtc0_performance5();
2837
           rn = "Performance5";
2838
//         break;
2838
//            gen_op_mtc0_performance5();
2839
            rn = "Performance5";
2840
//            break;
2839 2841
        case 6:
2840
//         gen_op_mtc0_performance6();
2841
           rn = "Performance6";
2842
//         break;
2842
//            gen_op_mtc0_performance6();
2843
            rn = "Performance6";
2844
//            break;
2843 2845
        case 7:
2844
//         gen_op_mtc0_performance7();
2845
           rn = "Performance7";
2846
//         break;
2846
//            gen_op_mtc0_performance7();
2847
            rn = "Performance7";
2848
//            break;
2847 2849
        default:
2848 2850
            goto die;
2849 2851
        }
2850 2852
       break;
2851 2853
    case 26:
2852
       /* ignored */
2854
        /* ignored */
2853 2855
        rn = "ECC";
2854
       break;
2856
        break;
2855 2857
    case 27:
2856 2858
        switch (sel) {
2857 2859
        case 0 ... 3:
2858
           /* ignored */
2859
           rn = "CacheErr";
2860
           break;
2860
            /* ignored */
2861
            rn = "CacheErr";
2862
            break;
2861 2863
        default:
2862 2864
            goto die;
2863 2865
        }
......
2875 2877
        case 3:
2876 2878
        case 5:
2877 2879
        case 7:
2878
           gen_op_mtc0_datalo();
2880
            gen_op_mtc0_datalo();
2879 2881
            rn = "DataLo";
2880 2882
            break;
2881 2883
        default:
......
2895 2897
        case 3:
2896 2898
        case 5:
2897 2899
        case 7:
2898
           gen_op_mtc0_datahi();
2900
            gen_op_mtc0_datahi();
2899 2901
            rn = "DataHi";
2900 2902
            break;
2901 2903
        default:
......
2906 2908
    case 30:
2907 2909
        switch (sel) {
2908 2910
        case 0:
2909
           gen_op_mtc0_errorepc();
2910
           rn = "ErrorEPC";
2911
           break;
2911
            gen_op_mtc0_errorepc();
2912
            rn = "ErrorEPC";
2913
            break;
2912 2914
        default:
2913 2915
            goto die;
2914 2916
        }
......
2916 2918
    case 31:
2917 2919
        switch (sel) {
2918 2920
        case 0:
2919
           gen_op_mtc0_desave(); /* EJTAG support */
2920
           rn = "DESAVE";
2921
           break;
2921
            gen_op_mtc0_desave(); /* EJTAG support */
2922
            rn = "DESAVE";
2923
            break;
2922 2924
        default:
2923 2925
            goto die;
2924 2926
        }
2925
       /* Stop translation as we may have switched the execution mode */
2926
       ctx->bstate = BS_STOP;
2927
        /* Stop translation as we may have switched the execution mode */
2928
        ctx->bstate = BS_STOP;
2927 2929
        break;
2928 2930
    default:
2929 2931
       goto die;
......
2955 2957
    case 0:
2956 2958
        switch (sel) {
2957 2959
        case 0:
2958
           gen_op_mfc0_index();
2960
            gen_op_mfc0_index();
2959 2961
            rn = "Index";
2960 2962
            break;
2961 2963
        case 1:
2962
//         gen_op_dmfc0_mvpcontrol(); /* MT ASE */
2964
//            gen_op_dmfc0_mvpcontrol(); /* MT ASE */
... This diff was truncated because it exceeds the maximum size that can be displayed.

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