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/*
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 * i386 virtual CPU header
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#define TARGET_HAS_ICE 1
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#ifdef TARGET_X86_64
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#define ELF_MACHINE        EM_X86_64
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#else
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#define ELF_MACHINE        EM_386
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#endif
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
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#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
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#define DESC_DPL_MASK   (1 << DESC_DPL_SHIFT)
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#define DESC_S_MASK     (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_A_MASK     (1 << 8)
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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
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#define DESC_C_MASK     (1 << 10) /* code: conforming */
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#define DESC_R_MASK     (1 << 9)  /* code: readable */
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#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
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#define DESC_W_MASK     (1 << 9)  /* data: writable */
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#define DESC_TSS_BUSY_MASK (1 << 9)
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/* eflags masks */
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#define CC_C           0x0001
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#define CC_P         0x0004
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#define CC_A        0x0010
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#define CC_Z        0x0040
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#define CC_S    0x0080
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#define CC_O    0x0800
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#define TF_SHIFT   8
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#define IOPL_SHIFT 12
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#define VM_SHIFT   17
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#define TF_MASK                 0x00000100
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#define IF_MASK                 0x00000200
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#define DF_MASK                 0x00000400
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#define IOPL_MASK                0x00003000
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#define NT_MASK                         0x00004000
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#define RF_MASK                        0x00010000
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#define VM_MASK                        0x00020000
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#define AC_MASK                        0x00040000
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#define VIF_MASK                0x00080000
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#define VIP_MASK                0x00100000
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#define ID_MASK                 0x00200000
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/* hidden flags - used internally by qemu to represent additional cpu
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   states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
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   redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
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   position to ease oring with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT         0
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/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT     2
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
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#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
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#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_SMM_SHIFT        19 /* CPU in SMM mode */
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#define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
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#define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
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#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
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#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
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#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
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#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
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#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
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#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
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#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
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#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
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#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
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#define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
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#define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
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/* hflags2 */
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#define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
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#define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
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#define HF2_NMI_SHIFT        2 /* CPU serving NMI */
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#define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
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#define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
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#define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT) 
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#define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
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#define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
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#define CR0_EM_MASK  (1 << 2)
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#define CR0_TS_MASK  (1 << 3)
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#define CR0_ET_MASK  (1 << 4)
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#define CR0_NE_MASK  (1 << 5)
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#define CR0_WP_MASK  (1 << 16)
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#define CR0_AM_MASK  (1 << 18)
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#define CR0_PG_MASK  (1 << 31)
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#define CR4_VME_MASK  (1 << 0)
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#define CR4_PVI_MASK  (1 << 1)
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#define CR4_TSD_MASK  (1 << 2)
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#define CR4_DE_MASK   (1 << 3)
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#define CR4_PSE_MASK  (1 << 4)
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#define CR4_PAE_MASK  (1 << 5)
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#define CR4_PGE_MASK  (1 << 7)
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#define CR4_PCE_MASK  (1 << 8)
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#define CR4_OSFXSR_MASK (1 << 9)
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#define CR4_OSXMMEXCPT_MASK  (1 << 10)
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#define PG_PRESENT_BIT        0
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#define PG_RW_BIT        1
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#define PG_USER_BIT        2
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#define PG_PWT_BIT        3
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#define PG_PCD_BIT        4
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#define PG_ACCESSED_BIT        5
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#define PG_DIRTY_BIT        6
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#define PG_PSE_BIT        7
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#define PG_GLOBAL_BIT        8
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#define PG_NX_BIT        63
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#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK         (1 << PG_RW_BIT)
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#define PG_USER_MASK         (1 << PG_USER_BIT)
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#define PG_PWT_MASK         (1 << PG_PWT_BIT)
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#define PG_PCD_MASK         (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK         (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK         (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK         (1 << PG_GLOBAL_BIT)
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#define PG_NX_MASK         (1LL << PG_NX_BIT)
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#define PG_ERROR_W_BIT     1
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#define PG_ERROR_P_MASK    0x01
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#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
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#define PG_ERROR_U_MASK    0x04
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#define PG_ERROR_RSVD_MASK 0x08
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#define PG_ERROR_I_D_MASK  0x10
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#define MSR_IA32_APICBASE               0x1b
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#define MSR_IA32_APICBASE_BSP           (1<<8)
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#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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#define MSR_IA32_SYSENTER_CS            0x174
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define MSR_MCG_CAP                     0x179
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#define MSR_MCG_STATUS                  0x17a
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#define MSR_MCG_CTL                     0x17b
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#define MSR_IA32_PERF_STATUS            0x198
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#define MSR_PAT                         0x277
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#define MSR_EFER                        0xc0000080
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#define MSR_EFER_SCE   (1 << 0)
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#define MSR_EFER_LME   (1 << 8)
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#define MSR_EFER_LMA   (1 << 10)
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#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_SVME  (1 << 12)
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#define MSR_EFER_FFXSR (1 << 14)
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#define MSR_STAR                        0xc0000081
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#define MSR_LSTAR                       0xc0000082
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#define MSR_CSTAR                       0xc0000083
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#define MSR_FMASK                       0xc0000084
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#define MSR_FSBASE                      0xc0000100
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#define MSR_GSBASE                      0xc0000101
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#define MSR_KERNELGSBASE                0xc0000102
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#define MSR_VM_HSAVE_PA                 0xc0010117
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/* cpuid_features bits */
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#define CPUID_FP87 (1 << 0)
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#define CPUID_VME  (1 << 1)
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#define CPUID_DE   (1 << 2)
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#define CPUID_PSE  (1 << 3)
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#define CPUID_TSC  (1 << 4)
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#define CPUID_MSR  (1 << 5)
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#define CPUID_PAE  (1 << 6)
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#define CPUID_MCE  (1 << 7)
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#define CPUID_CX8  (1 << 8)
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#define CPUID_APIC (1 << 9)
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#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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#define CPUID_MTRR (1 << 12)
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#define CPUID_PGE  (1 << 13)
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#define CPUID_MCA  (1 << 14)
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#define CPUID_CMOV (1 << 15)
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#define CPUID_PAT  (1 << 16)
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#define CPUID_PSE36   (1 << 17)
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#define CPUID_PN   (1 << 18)
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#define CPUID_CLFLUSH (1 << 19)
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#define CPUID_DTS (1 << 21)
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#define CPUID_ACPI (1 << 22)
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#define CPUID_MMX  (1 << 23)
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#define CPUID_FXSR (1 << 24)
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#define CPUID_SSE  (1 << 25)
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#define CPUID_SSE2 (1 << 26)
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#define CPUID_SS (1 << 27)
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#define CPUID_HT (1 << 28)
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#define CPUID_TM (1 << 29)
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#define CPUID_IA64 (1 << 30)
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#define CPUID_PBE (1 << 31)
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#define CPUID_EXT_SSE3     (1 << 0)
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#define CPUID_EXT_MONITOR  (1 << 3)
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#define CPUID_EXT_DSCPL    (1 << 4)
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#define CPUID_EXT_VMX      (1 << 5)
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#define CPUID_EXT_SMX      (1 << 6)
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#define CPUID_EXT_EST      (1 << 7)
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#define CPUID_EXT_TM2      (1 << 8)
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#define CPUID_EXT_SSSE3    (1 << 9)
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#define CPUID_EXT_CID      (1 << 10)
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#define CPUID_EXT_CX16     (1 << 13)
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#define CPUID_EXT_XTPR     (1 << 14)
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#define CPUID_EXT_DCA      (1 << 17)
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#define CPUID_EXT_POPCNT   (1 << 22)
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#define CPUID_EXT2_SYSCALL (1 << 11)
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#define CPUID_EXT2_MP      (1 << 19)
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#define CPUID_EXT2_NX      (1 << 20)
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#define CPUID_EXT2_MMXEXT  (1 << 22)
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#define CPUID_EXT2_FFXSR   (1 << 25)
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#define CPUID_EXT2_PDPE1GB (1 << 26)
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#define CPUID_EXT2_RDTSCP  (1 << 27)
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#define CPUID_EXT2_LM      (1 << 29)
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#define CPUID_EXT2_3DNOWEXT (1 << 30)
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#define CPUID_EXT2_3DNOW   (1 << 31)
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#define CPUID_EXT3_LAHF_LM (1 << 0)
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#define CPUID_EXT3_CMP_LEG (1 << 1)
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#define CPUID_EXT3_SVM     (1 << 2)
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#define CPUID_EXT3_EXTAPIC (1 << 3)
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#define CPUID_EXT3_CR8LEG  (1 << 4)
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#define CPUID_EXT3_ABM     (1 << 5)
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#define CPUID_EXT3_SSE4A   (1 << 6)
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#define CPUID_EXT3_MISALIGNSSE (1 << 7)
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#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
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#define CPUID_EXT3_OSVW    (1 << 9)
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#define CPUID_EXT3_IBS     (1 << 10)
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#define CPUID_EXT3_SKINIT  (1 << 12)
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#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
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#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
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#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
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#define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
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#define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */ 
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#define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
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#define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
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#define CPUID_MWAIT_EMX     (0 << 1) /* enumeration supported */
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#define EXCP00_DIVZ        0
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#define EXCP01_SSTP        1
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#define EXCP02_NMI        2
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#define EXCP03_INT3        3
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#define EXCP04_INTO        4
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#define EXCP05_BOUND        5
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#define EXCP06_ILLOP        6
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#define EXCP07_PREX        7
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#define EXCP08_DBLE        8
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#define EXCP09_XERR        9
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#define EXCP0A_TSS        10
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#define EXCP0B_NOSEG        11
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#define EXCP0C_STACK        12
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#define EXCP0D_GPF        13
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#define EXCP0E_PAGE        14
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#define EXCP10_COPR        16
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#define EXCP11_ALGN        17
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#define EXCP12_MCHK        18
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#define EXCP_SYSCALL    0x100 /* only happens in user only emulation
369
                                 for syscall instruction */
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enum {
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    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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    CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
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    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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    CC_OP_MULW,
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    CC_OP_MULL,
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    CC_OP_MULQ,
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    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADDW,
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    CC_OP_ADDL,
383
    CC_OP_ADDQ,
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    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
386
    CC_OP_ADCW,
387
    CC_OP_ADCL,
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    CC_OP_ADCQ,
389

    
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    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SUBW,
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    CC_OP_SUBL,
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    CC_OP_SUBQ,
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    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SBBW,
397
    CC_OP_SBBL,
398
    CC_OP_SBBQ,
399

    
400
    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
401
    CC_OP_LOGICW,
402
    CC_OP_LOGICL,
403
    CC_OP_LOGICQ,
404

    
405
    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
406
    CC_OP_INCW,
407
    CC_OP_INCL,
408
    CC_OP_INCQ,
409

    
410
    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
411
    CC_OP_DECW,
412
    CC_OP_DECL,
413
    CC_OP_DECQ,
414

    
415
    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
416
    CC_OP_SHLW,
417
    CC_OP_SHLL,
418
    CC_OP_SHLQ,
419

    
420
    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
421
    CC_OP_SARW,
422
    CC_OP_SARL,
423
    CC_OP_SARQ,
424

    
425
    CC_OP_NB,
426
};
427

    
428
#ifdef FLOATX80
429
#define USE_X86LDOUBLE
430
#endif
431

    
432
#ifdef USE_X86LDOUBLE
433
typedef floatx80 CPU86_LDouble;
434
#else
435
typedef float64 CPU86_LDouble;
436
#endif
437

    
438
typedef struct SegmentCache {
439
    uint32_t selector;
440
    target_ulong base;
441
    uint32_t limit;
442
    uint32_t flags;
443
} SegmentCache;
444

    
445
typedef union {
446
    uint8_t _b[16];
447
    uint16_t _w[8];
448
    uint32_t _l[4];
449
    uint64_t _q[2];
450
    float32 _s[4];
451
    float64 _d[2];
452
} XMMReg;
453

    
454
typedef union {
455
    uint8_t _b[8];
456
    uint16_t _w[4];
457
    uint32_t _l[2];
458
    float32 _s[2];
459
    uint64_t q;
460
} MMXReg;
461

    
462
#ifdef WORDS_BIGENDIAN
463
#define XMM_B(n) _b[15 - (n)]
464
#define XMM_W(n) _w[7 - (n)]
465
#define XMM_L(n) _l[3 - (n)]
466
#define XMM_S(n) _s[3 - (n)]
467
#define XMM_Q(n) _q[1 - (n)]
468
#define XMM_D(n) _d[1 - (n)]
469

    
470
#define MMX_B(n) _b[7 - (n)]
471
#define MMX_W(n) _w[3 - (n)]
472
#define MMX_L(n) _l[1 - (n)]
473
#define MMX_S(n) _s[1 - (n)]
474
#else
475
#define XMM_B(n) _b[n]
476
#define XMM_W(n) _w[n]
477
#define XMM_L(n) _l[n]
478
#define XMM_S(n) _s[n]
479
#define XMM_Q(n) _q[n]
480
#define XMM_D(n) _d[n]
481

    
482
#define MMX_B(n) _b[n]
483
#define MMX_W(n) _w[n]
484
#define MMX_L(n) _l[n]
485
#define MMX_S(n) _s[n]
486
#endif
487
#define MMX_Q(n) q
488

    
489
#ifdef TARGET_X86_64
490
#define CPU_NB_REGS 16
491
#else
492
#define CPU_NB_REGS 8
493
#endif
494

    
495
#define NB_MMU_MODES 2
496

    
497
typedef struct CPUX86State {
498
    /* standard registers */
499
    target_ulong regs[CPU_NB_REGS];
500
    target_ulong eip;
501
    target_ulong eflags; /* eflags register. During CPU emulation, CC
502
                        flags and DF are set to zero because they are
503
                        stored elsewhere */
504

    
505
    /* emulator internal eflags handling */
506
    target_ulong cc_src;
507
    target_ulong cc_dst;
508
    uint32_t cc_op;
509
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
510
    uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
511
                        are known at translation time. */
512
    uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
513

    
514
    /* segments */
515
    SegmentCache segs[6]; /* selector values */
516
    SegmentCache ldt;
517
    SegmentCache tr;
518
    SegmentCache gdt; /* only base and limit are used */
519
    SegmentCache idt; /* only base and limit are used */
520

    
521
    target_ulong cr[5]; /* NOTE: cr1 is unused */
522
    uint64_t a20_mask;
523

    
524
    /* FPU state */
525
    unsigned int fpstt; /* top of stack index */
526
    unsigned int fpus;
527
    unsigned int fpuc;
528
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
529
    union {
530
#ifdef USE_X86LDOUBLE
531
        CPU86_LDouble d __attribute__((aligned(16)));
532
#else
533
        CPU86_LDouble d;
534
#endif
535
        MMXReg mmx;
536
    } fpregs[8];
537

    
538
    /* emulator internal variables */
539
    float_status fp_status;
540
    CPU86_LDouble ft0;
541

    
542
    float_status mmx_status; /* for 3DNow! float ops */
543
    float_status sse_status;
544
    uint32_t mxcsr;
545
    XMMReg xmm_regs[CPU_NB_REGS];
546
    XMMReg xmm_t0;
547
    MMXReg mmx_t0;
548
    target_ulong cc_tmp; /* temporary for rcr/rcl */
549

    
550
    /* sysenter registers */
551
    uint32_t sysenter_cs;
552
    target_ulong sysenter_esp;
553
    target_ulong sysenter_eip;
554
    uint64_t efer;
555
    uint64_t star;
556

    
557
    uint64_t vm_hsave;
558
    uint64_t vm_vmcb;
559
    uint64_t tsc_offset;
560
    uint64_t intercept;
561
    uint16_t intercept_cr_read;
562
    uint16_t intercept_cr_write;
563
    uint16_t intercept_dr_read;
564
    uint16_t intercept_dr_write;
565
    uint32_t intercept_exceptions;
566
    uint8_t v_tpr;
567

    
568
#ifdef TARGET_X86_64
569
    target_ulong lstar;
570
    target_ulong cstar;
571
    target_ulong fmask;
572
    target_ulong kernelgsbase;
573
#endif
574

    
575
    uint64_t pat;
576

    
577
    /* exception/interrupt handling */
578
    int error_code;
579
    int exception_is_int;
580
    target_ulong exception_next_eip;
581
    target_ulong dr[8]; /* debug registers */
582
    uint32_t smbase;
583
    int old_exception;  /* exception in flight */
584

    
585
    CPU_COMMON
586

    
587
    /* processor features (e.g. for CPUID insn) */
588
    uint32_t cpuid_level;
589
    uint32_t cpuid_vendor1;
590
    uint32_t cpuid_vendor2;
591
    uint32_t cpuid_vendor3;
592
    uint32_t cpuid_version;
593
    uint32_t cpuid_features;
594
    uint32_t cpuid_ext_features;
595
    uint32_t cpuid_xlevel;
596
    uint32_t cpuid_model[12];
597
    uint32_t cpuid_ext2_features;
598
    uint32_t cpuid_ext3_features;
599
    uint32_t cpuid_apic_id;
600

    
601
#ifdef USE_KQEMU
602
    int kqemu_enabled;
603
    int last_io_time;
604
#endif
605
    /* in order to simplify APIC support, we leave this pointer to the
606
       user */
607
    struct APICState *apic_state;
608
} CPUX86State;
609

    
610
CPUX86State *cpu_x86_init(const char *cpu_model);
611
int cpu_x86_exec(CPUX86State *s);
612
void cpu_x86_close(CPUX86State *s);
613
void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
614
                                                 ...));
615
int cpu_get_pic_interrupt(CPUX86State *s);
616
/* MSDOS compatibility mode FPU exception support */
617
void cpu_set_ferr(CPUX86State *s);
618

    
619
/* this function must always be used to load data in the segment
620
   cache: it synchronizes the hflags with the segment cache values */
621
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
622
                                          int seg_reg, unsigned int selector,
623
                                          target_ulong base,
624
                                          unsigned int limit,
625
                                          unsigned int flags)
626
{
627
    SegmentCache *sc;
628
    unsigned int new_hflags;
629

    
630
    sc = &env->segs[seg_reg];
631
    sc->selector = selector;
632
    sc->base = base;
633
    sc->limit = limit;
634
    sc->flags = flags;
635

    
636
    /* update the hidden flags */
637
    {
638
        if (seg_reg == R_CS) {
639
#ifdef TARGET_X86_64
640
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
641
                /* long mode */
642
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
643
                env->hflags &= ~(HF_ADDSEG_MASK);
644
            } else
645
#endif
646
            {
647
                /* legacy / compatibility case */
648
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
649
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
650
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
651
                    new_hflags;
652
            }
653
        }
654
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
655
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
656
        if (env->hflags & HF_CS64_MASK) {
657
            /* zero base assumed for DS, ES and SS in long mode */
658
        } else if (!(env->cr[0] & CR0_PE_MASK) ||
659
                   (env->eflags & VM_MASK) ||
660
                   !(env->hflags & HF_CS32_MASK)) {
661
            /* XXX: try to avoid this test. The problem comes from the
662
               fact that is real mode or vm86 mode we only modify the
663
               'base' and 'selector' fields of the segment cache to go
664
               faster. A solution may be to force addseg to one in
665
               translate-i386.c. */
666
            new_hflags |= HF_ADDSEG_MASK;
667
        } else {
668
            new_hflags |= ((env->segs[R_DS].base |
669
                            env->segs[R_ES].base |
670
                            env->segs[R_SS].base) != 0) <<
671
                HF_ADDSEG_SHIFT;
672
        }
673
        env->hflags = (env->hflags &
674
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
675
    }
676
}
677

    
678
/* wrapper, just in case memory mappings must be changed */
679
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
680
{
681
#if HF_CPL_MASK == 3
682
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
683
#else
684
#error HF_CPL_MASK is hardcoded
685
#endif
686
}
687

    
688
/* used for debug or cpu save/restore */
689
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
690
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
691

    
692
/* the following helpers are only usable in user mode simulation as
693
   they can trigger unexpected exceptions */
694
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
695
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
696
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
697

    
698
/* you can call this signal handler from your SIGBUS and SIGSEGV
699
   signal handlers to inform the virtual CPU of exceptions. non zero
700
   is returned if the signal was handled by the virtual CPU.  */
701
int cpu_x86_signal_handler(int host_signum, void *pinfo,
702
                           void *puc);
703
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
704

    
705
uint64_t cpu_get_tsc(CPUX86State *env);
706

    
707
void cpu_set_apic_base(CPUX86State *env, uint64_t val);
708
uint64_t cpu_get_apic_base(CPUX86State *env);
709
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
710
#ifndef NO_CPU_IO_DEFS
711
uint8_t cpu_get_apic_tpr(CPUX86State *env);
712
#endif
713
void cpu_smm_update(CPUX86State *env);
714

    
715
/* will be suppressed */
716
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
717

    
718
/* used to debug */
719
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
720
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
721

    
722
#ifdef USE_KQEMU
723
static inline int cpu_get_time_fast(void)
724
{
725
    int low, high;
726
    asm volatile("rdtsc" : "=a" (low), "=d" (high));
727
    return low;
728
}
729
#endif
730

    
731
#define TARGET_PAGE_BITS 12
732

    
733
#define CPUState CPUX86State
734
#define cpu_init cpu_x86_init
735
#define cpu_exec cpu_x86_exec
736
#define cpu_gen_code cpu_x86_gen_code
737
#define cpu_signal_handler cpu_x86_signal_handler
738
#define cpu_list x86_cpu_list
739

    
740
#define CPU_SAVE_VERSION 7
741

    
742
/* MMU modes definitions */
743
#define MMU_MODE0_SUFFIX _kernel
744
#define MMU_MODE1_SUFFIX _user
745
#define MMU_USER_IDX 1
746
static inline int cpu_mmu_index (CPUState *env)
747
{
748
    return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
749
}
750

    
751
void optimize_flags_init(void);
752

    
753
typedef struct CCTable {
754
    int (*compute_all)(void); /* return all the flags */
755
    int (*compute_c)(void);  /* return the C flag */
756
} CCTable;
757

    
758
extern CCTable cc_table[];
759

    
760
#if defined(CONFIG_USER_ONLY)
761
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
762
{
763
    if (newsp)
764
        env->regs[R_ESP] = newsp;
765
    env->regs[R_EAX] = 0;
766
}
767
#endif
768

    
769
#define CPU_PC_FROM_TB(env, tb) env->eip = tb->pc - tb->cs_base
770

    
771
#include "cpu-all.h"
772

    
773
#include "svm.h"
774

    
775
#endif /* CPU_I386_H */