root / target-sparc / op_helper.c @ 24741ef3
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1 | e8af50a3 | bellard | #include "exec.h" |
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2 | e8af50a3 | bellard | |
3 | 83469015 | bellard | //#define DEBUG_PCALL
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4 | e80cfcfc | bellard | //#define DEBUG_MMU
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5 | e80cfcfc | bellard | |
6 | 9d893301 | bellard | void raise_exception(int tt) |
7 | 9d893301 | bellard | { |
8 | 9d893301 | bellard | env->exception_index = tt; |
9 | 9d893301 | bellard | cpu_loop_exit(); |
10 | 9d893301 | bellard | } |
11 | 9d893301 | bellard | |
12 | a0c4cb4a | bellard | #ifdef USE_INT_TO_FLOAT_HELPERS
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13 | a0c4cb4a | bellard | void do_fitos(void) |
14 | a0c4cb4a | bellard | { |
15 | a0c4cb4a | bellard | FT0 = (float) *((int32_t *)&FT1);
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16 | a0c4cb4a | bellard | } |
17 | a0c4cb4a | bellard | |
18 | a0c4cb4a | bellard | void do_fitod(void) |
19 | a0c4cb4a | bellard | { |
20 | a0c4cb4a | bellard | DT0 = (double) *((int32_t *)&FT1);
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21 | a0c4cb4a | bellard | } |
22 | a0c4cb4a | bellard | #endif
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23 | a0c4cb4a | bellard | |
24 | a0c4cb4a | bellard | void do_fabss(void) |
25 | e8af50a3 | bellard | { |
26 | 7a0e1f41 | bellard | FT0 = float32_abs(FT1); |
27 | e8af50a3 | bellard | } |
28 | e8af50a3 | bellard | |
29 | 3475187d | bellard | #ifdef TARGET_SPARC64
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30 | 3475187d | bellard | void do_fabsd(void) |
31 | 3475187d | bellard | { |
32 | 3475187d | bellard | DT0 = float64_abs(DT1); |
33 | 3475187d | bellard | } |
34 | 3475187d | bellard | #endif
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35 | 3475187d | bellard | |
36 | a0c4cb4a | bellard | void do_fsqrts(void) |
37 | e8af50a3 | bellard | { |
38 | 7a0e1f41 | bellard | FT0 = float32_sqrt(FT1, &env->fp_status); |
39 | e8af50a3 | bellard | } |
40 | e8af50a3 | bellard | |
41 | a0c4cb4a | bellard | void do_fsqrtd(void) |
42 | e8af50a3 | bellard | { |
43 | 7a0e1f41 | bellard | DT0 = float64_sqrt(DT1, &env->fp_status); |
44 | e8af50a3 | bellard | } |
45 | e8af50a3 | bellard | |
46 | 3475187d | bellard | #define FS 0 |
47 | a0c4cb4a | bellard | void do_fcmps (void) |
48 | e8af50a3 | bellard | { |
49 | 3475187d | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
50 | e8af50a3 | bellard | if (isnan(FT0) || isnan(FT1)) {
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51 | 3475187d | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
52 | e80cfcfc | bellard | if (env->fsr & FSR_NVM) {
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53 | 3475187d | bellard | env->fsr |= T0; |
54 | e80cfcfc | bellard | raise_exception(TT_FP_EXCP); |
55 | e80cfcfc | bellard | } else {
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56 | e80cfcfc | bellard | env->fsr |= FSR_NVA; |
57 | e80cfcfc | bellard | } |
58 | e8af50a3 | bellard | } else if (FT0 < FT1) { |
59 | 3475187d | bellard | T0 = FSR_FCC0 << FS; |
60 | e8af50a3 | bellard | } else if (FT0 > FT1) { |
61 | 3475187d | bellard | T0 = FSR_FCC1 << FS; |
62 | e8af50a3 | bellard | } else {
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63 | e8af50a3 | bellard | T0 = 0;
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64 | e8af50a3 | bellard | } |
65 | 3475187d | bellard | env->fsr |= T0; |
66 | e8af50a3 | bellard | } |
67 | e8af50a3 | bellard | |
68 | a0c4cb4a | bellard | void do_fcmpd (void) |
69 | e8af50a3 | bellard | { |
70 | 3475187d | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
71 | 3475187d | bellard | if (isnan(DT0) || isnan(DT1)) {
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72 | 3475187d | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
73 | 3475187d | bellard | if (env->fsr & FSR_NVM) {
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74 | 3475187d | bellard | env->fsr |= T0; |
75 | 3475187d | bellard | raise_exception(TT_FP_EXCP); |
76 | 3475187d | bellard | } else {
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77 | 3475187d | bellard | env->fsr |= FSR_NVA; |
78 | 3475187d | bellard | } |
79 | 3475187d | bellard | } else if (DT0 < DT1) { |
80 | 3475187d | bellard | T0 = FSR_FCC0 << FS; |
81 | 3475187d | bellard | } else if (DT0 > DT1) { |
82 | 3475187d | bellard | T0 = FSR_FCC1 << FS; |
83 | 3475187d | bellard | } else {
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84 | 3475187d | bellard | T0 = 0;
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85 | 3475187d | bellard | } |
86 | 3475187d | bellard | env->fsr |= T0; |
87 | 3475187d | bellard | } |
88 | 3475187d | bellard | |
89 | 3475187d | bellard | #ifdef TARGET_SPARC64
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90 | 3475187d | bellard | #undef FS
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91 | 3475187d | bellard | #define FS 22 |
92 | 3475187d | bellard | void do_fcmps_fcc1 (void) |
93 | 3475187d | bellard | { |
94 | 3475187d | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
95 | 3475187d | bellard | if (isnan(FT0) || isnan(FT1)) {
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96 | 3475187d | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
97 | 3475187d | bellard | if (env->fsr & FSR_NVM) {
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98 | 3475187d | bellard | env->fsr |= T0; |
99 | 3475187d | bellard | raise_exception(TT_FP_EXCP); |
100 | 3475187d | bellard | } else {
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101 | 3475187d | bellard | env->fsr |= FSR_NVA; |
102 | 3475187d | bellard | } |
103 | 3475187d | bellard | } else if (FT0 < FT1) { |
104 | 3475187d | bellard | T0 = FSR_FCC0 << FS; |
105 | 3475187d | bellard | } else if (FT0 > FT1) { |
106 | 3475187d | bellard | T0 = FSR_FCC1 << FS; |
107 | 3475187d | bellard | } else {
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108 | 3475187d | bellard | T0 = 0;
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109 | 3475187d | bellard | } |
110 | 3475187d | bellard | env->fsr |= T0; |
111 | 3475187d | bellard | } |
112 | 3475187d | bellard | |
113 | 3475187d | bellard | void do_fcmpd_fcc1 (void) |
114 | 3475187d | bellard | { |
115 | 3475187d | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
116 | 3475187d | bellard | if (isnan(DT0) || isnan(DT1)) {
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117 | 3475187d | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
118 | 3475187d | bellard | if (env->fsr & FSR_NVM) {
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119 | 3475187d | bellard | env->fsr |= T0; |
120 | 3475187d | bellard | raise_exception(TT_FP_EXCP); |
121 | 3475187d | bellard | } else {
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122 | 3475187d | bellard | env->fsr |= FSR_NVA; |
123 | 3475187d | bellard | } |
124 | 3475187d | bellard | } else if (DT0 < DT1) { |
125 | 3475187d | bellard | T0 = FSR_FCC0 << FS; |
126 | 3475187d | bellard | } else if (DT0 > DT1) { |
127 | 3475187d | bellard | T0 = FSR_FCC1 << FS; |
128 | 3475187d | bellard | } else {
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129 | 3475187d | bellard | T0 = 0;
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130 | 3475187d | bellard | } |
131 | 3475187d | bellard | env->fsr |= T0; |
132 | 3475187d | bellard | } |
133 | 3475187d | bellard | |
134 | 3475187d | bellard | #undef FS
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135 | 3475187d | bellard | #define FS 24 |
136 | 3475187d | bellard | void do_fcmps_fcc2 (void) |
137 | 3475187d | bellard | { |
138 | 3475187d | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
139 | 3475187d | bellard | if (isnan(FT0) || isnan(FT1)) {
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140 | 3475187d | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
141 | 3475187d | bellard | if (env->fsr & FSR_NVM) {
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142 | 3475187d | bellard | env->fsr |= T0; |
143 | 3475187d | bellard | raise_exception(TT_FP_EXCP); |
144 | 3475187d | bellard | } else {
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145 | 3475187d | bellard | env->fsr |= FSR_NVA; |
146 | 3475187d | bellard | } |
147 | 3475187d | bellard | } else if (FT0 < FT1) { |
148 | 3475187d | bellard | T0 = FSR_FCC0 << FS; |
149 | 3475187d | bellard | } else if (FT0 > FT1) { |
150 | 3475187d | bellard | T0 = FSR_FCC1 << FS; |
151 | 3475187d | bellard | } else {
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152 | 3475187d | bellard | T0 = 0;
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153 | 3475187d | bellard | } |
154 | 3475187d | bellard | env->fsr |= T0; |
155 | 3475187d | bellard | } |
156 | 3475187d | bellard | |
157 | 3475187d | bellard | void do_fcmpd_fcc2 (void) |
158 | 3475187d | bellard | { |
159 | 3475187d | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
160 | e8af50a3 | bellard | if (isnan(DT0) || isnan(DT1)) {
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161 | 3475187d | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
162 | e80cfcfc | bellard | if (env->fsr & FSR_NVM) {
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163 | 3475187d | bellard | env->fsr |= T0; |
164 | e80cfcfc | bellard | raise_exception(TT_FP_EXCP); |
165 | e80cfcfc | bellard | } else {
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166 | e80cfcfc | bellard | env->fsr |= FSR_NVA; |
167 | e80cfcfc | bellard | } |
168 | e8af50a3 | bellard | } else if (DT0 < DT1) { |
169 | 3475187d | bellard | T0 = FSR_FCC0 << FS; |
170 | e8af50a3 | bellard | } else if (DT0 > DT1) { |
171 | 3475187d | bellard | T0 = FSR_FCC1 << FS; |
172 | 3475187d | bellard | } else {
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173 | 3475187d | bellard | T0 = 0;
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174 | 3475187d | bellard | } |
175 | 3475187d | bellard | env->fsr |= T0; |
176 | 3475187d | bellard | } |
177 | 3475187d | bellard | |
178 | 3475187d | bellard | #undef FS
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179 | 3475187d | bellard | #define FS 26 |
180 | 3475187d | bellard | void do_fcmps_fcc3 (void) |
181 | 3475187d | bellard | { |
182 | 3475187d | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
183 | 3475187d | bellard | if (isnan(FT0) || isnan(FT1)) {
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184 | 3475187d | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
185 | 3475187d | bellard | if (env->fsr & FSR_NVM) {
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186 | 3475187d | bellard | env->fsr |= T0; |
187 | 3475187d | bellard | raise_exception(TT_FP_EXCP); |
188 | 3475187d | bellard | } else {
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189 | 3475187d | bellard | env->fsr |= FSR_NVA; |
190 | 3475187d | bellard | } |
191 | 3475187d | bellard | } else if (FT0 < FT1) { |
192 | 3475187d | bellard | T0 = FSR_FCC0 << FS; |
193 | 3475187d | bellard | } else if (FT0 > FT1) { |
194 | 3475187d | bellard | T0 = FSR_FCC1 << FS; |
195 | e8af50a3 | bellard | } else {
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196 | e8af50a3 | bellard | T0 = 0;
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197 | e8af50a3 | bellard | } |
198 | 3475187d | bellard | env->fsr |= T0; |
199 | e8af50a3 | bellard | } |
200 | e8af50a3 | bellard | |
201 | 3475187d | bellard | void do_fcmpd_fcc3 (void) |
202 | 3475187d | bellard | { |
203 | 3475187d | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
204 | 3475187d | bellard | if (isnan(DT0) || isnan(DT1)) {
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205 | 3475187d | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
206 | 3475187d | bellard | if (env->fsr & FSR_NVM) {
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207 | 3475187d | bellard | env->fsr |= T0; |
208 | 3475187d | bellard | raise_exception(TT_FP_EXCP); |
209 | 3475187d | bellard | } else {
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210 | 3475187d | bellard | env->fsr |= FSR_NVA; |
211 | 3475187d | bellard | } |
212 | 3475187d | bellard | } else if (DT0 < DT1) { |
213 | 3475187d | bellard | T0 = FSR_FCC0 << FS; |
214 | 3475187d | bellard | } else if (DT0 > DT1) { |
215 | 3475187d | bellard | T0 = FSR_FCC1 << FS; |
216 | 3475187d | bellard | } else {
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217 | 3475187d | bellard | T0 = 0;
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218 | 3475187d | bellard | } |
219 | 3475187d | bellard | env->fsr |= T0; |
220 | 3475187d | bellard | } |
221 | 3475187d | bellard | #undef FS
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222 | 3475187d | bellard | #endif
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223 | 3475187d | bellard | |
224 | 24741ef3 | bellard | #if defined(CONFIG_USER_ONLY)
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225 | 24741ef3 | bellard | void helper_ld_asi(int asi, int size, int sign) |
226 | 24741ef3 | bellard | { |
227 | 24741ef3 | bellard | } |
228 | 24741ef3 | bellard | |
229 | 24741ef3 | bellard | void helper_st_asi(int asi, int size, int sign) |
230 | 24741ef3 | bellard | { |
231 | 24741ef3 | bellard | } |
232 | 24741ef3 | bellard | #else
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233 | 3475187d | bellard | #ifndef TARGET_SPARC64
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234 | a0c4cb4a | bellard | void helper_ld_asi(int asi, int size, int sign) |
235 | e8af50a3 | bellard | { |
236 | 83469015 | bellard | uint32_t ret = 0;
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237 | e80cfcfc | bellard | |
238 | e80cfcfc | bellard | switch (asi) {
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239 | e8af50a3 | bellard | case 3: /* MMU probe */ |
240 | e80cfcfc | bellard | { |
241 | e80cfcfc | bellard | int mmulev;
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242 | e80cfcfc | bellard | |
243 | e80cfcfc | bellard | mmulev = (T0 >> 8) & 15; |
244 | e80cfcfc | bellard | if (mmulev > 4) |
245 | e80cfcfc | bellard | ret = 0;
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246 | e80cfcfc | bellard | else {
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247 | ee5bbe38 | bellard | ret = mmu_probe(env, T0, mmulev); |
248 | e80cfcfc | bellard | //bswap32s(&ret);
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249 | e80cfcfc | bellard | } |
250 | e80cfcfc | bellard | #ifdef DEBUG_MMU
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251 | e80cfcfc | bellard | printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
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252 | e80cfcfc | bellard | #endif
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253 | e80cfcfc | bellard | } |
254 | e80cfcfc | bellard | break;
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255 | e8af50a3 | bellard | case 4: /* read MMU regs */ |
256 | e8af50a3 | bellard | { |
257 | e80cfcfc | bellard | int reg = (T0 >> 8) & 0xf; |
258 | e8af50a3 | bellard | |
259 | e80cfcfc | bellard | ret = env->mmuregs[reg]; |
260 | 55754d9e | bellard | if (reg == 3) /* Fault status cleared on read */ |
261 | 55754d9e | bellard | env->mmuregs[reg] = 0;
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262 | 55754d9e | bellard | #ifdef DEBUG_MMU
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263 | 55754d9e | bellard | printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
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264 | 55754d9e | bellard | #endif
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265 | e8af50a3 | bellard | } |
266 | e80cfcfc | bellard | break;
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267 | e8af50a3 | bellard | case 0x20 ... 0x2f: /* MMU passthrough */ |
268 | 02aab46a | bellard | switch(size) {
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269 | 02aab46a | bellard | case 1: |
270 | 02aab46a | bellard | ret = ldub_phys(T0); |
271 | 02aab46a | bellard | break;
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272 | 02aab46a | bellard | case 2: |
273 | 02aab46a | bellard | ret = lduw_phys(T0 & ~1);
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274 | 02aab46a | bellard | break;
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275 | 02aab46a | bellard | default:
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276 | 02aab46a | bellard | case 4: |
277 | 02aab46a | bellard | ret = ldl_phys(T0 & ~3);
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278 | 02aab46a | bellard | break;
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279 | 02aab46a | bellard | } |
280 | e80cfcfc | bellard | break;
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281 | e8af50a3 | bellard | default:
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282 | e80cfcfc | bellard | ret = 0;
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283 | e80cfcfc | bellard | break;
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284 | e8af50a3 | bellard | } |
285 | e80cfcfc | bellard | T1 = ret; |
286 | e8af50a3 | bellard | } |
287 | e8af50a3 | bellard | |
288 | a0c4cb4a | bellard | void helper_st_asi(int asi, int size, int sign) |
289 | e8af50a3 | bellard | { |
290 | e8af50a3 | bellard | switch(asi) {
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291 | e8af50a3 | bellard | case 3: /* MMU flush */ |
292 | e80cfcfc | bellard | { |
293 | e80cfcfc | bellard | int mmulev;
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294 | e80cfcfc | bellard | |
295 | e80cfcfc | bellard | mmulev = (T0 >> 8) & 15; |
296 | 55754d9e | bellard | #ifdef DEBUG_MMU
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297 | 55754d9e | bellard | printf("mmu flush level %d\n", mmulev);
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298 | 55754d9e | bellard | #endif
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299 | e80cfcfc | bellard | switch (mmulev) {
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300 | e80cfcfc | bellard | case 0: // flush page |
301 | 55754d9e | bellard | tlb_flush_page(env, T0 & 0xfffff000);
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302 | e80cfcfc | bellard | break;
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303 | e80cfcfc | bellard | case 1: // flush segment (256k) |
304 | e80cfcfc | bellard | case 2: // flush region (16M) |
305 | e80cfcfc | bellard | case 3: // flush context (4G) |
306 | e80cfcfc | bellard | case 4: // flush entire |
307 | 55754d9e | bellard | tlb_flush(env, 1);
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308 | e80cfcfc | bellard | break;
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309 | e80cfcfc | bellard | default:
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310 | e80cfcfc | bellard | break;
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311 | e80cfcfc | bellard | } |
312 | 55754d9e | bellard | #ifdef DEBUG_MMU
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313 | ee5bbe38 | bellard | dump_mmu(env); |
314 | 55754d9e | bellard | #endif
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315 | e80cfcfc | bellard | return;
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316 | e80cfcfc | bellard | } |
317 | e8af50a3 | bellard | case 4: /* write MMU regs */ |
318 | e8af50a3 | bellard | { |
319 | 83469015 | bellard | int reg = (T0 >> 8) & 0xf; |
320 | 83469015 | bellard | uint32_t oldreg; |
321 | e80cfcfc | bellard | |
322 | e80cfcfc | bellard | oldreg = env->mmuregs[reg]; |
323 | 55754d9e | bellard | switch(reg) {
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324 | 55754d9e | bellard | case 0: |
325 | e8af50a3 | bellard | env->mmuregs[reg] &= ~(MMU_E | MMU_NF); |
326 | e8af50a3 | bellard | env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF); |
327 | 6f7e9aec | bellard | // Mappings generated during no-fault mode or MMU
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328 | 6f7e9aec | bellard | // disabled mode are invalid in normal mode
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329 | 6f7e9aec | bellard | if (oldreg != env->mmuregs[reg])
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330 | 55754d9e | bellard | tlb_flush(env, 1);
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331 | 55754d9e | bellard | break;
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332 | 55754d9e | bellard | case 2: |
333 | e8af50a3 | bellard | env->mmuregs[reg] = T1; |
334 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
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335 | 55754d9e | bellard | /* we flush when the MMU context changes because
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336 | 55754d9e | bellard | QEMU has no MMU context support */
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337 | 55754d9e | bellard | tlb_flush(env, 1);
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338 | 55754d9e | bellard | } |
339 | 55754d9e | bellard | break;
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340 | 55754d9e | bellard | case 3: |
341 | 55754d9e | bellard | case 4: |
342 | 55754d9e | bellard | break;
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343 | 55754d9e | bellard | default:
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344 | 55754d9e | bellard | env->mmuregs[reg] = T1; |
345 | 55754d9e | bellard | break;
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346 | 55754d9e | bellard | } |
347 | 55754d9e | bellard | #ifdef DEBUG_MMU
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348 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
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349 | 55754d9e | bellard | printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
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350 | 55754d9e | bellard | } |
351 | ee5bbe38 | bellard | dump_mmu(env); |
352 | 55754d9e | bellard | #endif
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353 | e8af50a3 | bellard | return;
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354 | e8af50a3 | bellard | } |
355 | e80cfcfc | bellard | case 0x17: /* Block copy, sta access */ |
356 | e80cfcfc | bellard | { |
357 | e80cfcfc | bellard | // value (T1) = src
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358 | e80cfcfc | bellard | // address (T0) = dst
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359 | e80cfcfc | bellard | // copy 32 bytes
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360 | 83469015 | bellard | uint32_t src = T1, dst = T0; |
361 | e80cfcfc | bellard | uint8_t temp[32];
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362 | e80cfcfc | bellard | |
363 | 49be8030 | bellard | tswap32s(&src); |
364 | e80cfcfc | bellard | |
365 | e80cfcfc | bellard | cpu_physical_memory_read(src, (void *) &temp, 32); |
366 | e80cfcfc | bellard | cpu_physical_memory_write(dst, (void *) &temp, 32); |
367 | e80cfcfc | bellard | } |
368 | e80cfcfc | bellard | return;
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369 | e80cfcfc | bellard | case 0x1f: /* Block fill, stda access */ |
370 | e80cfcfc | bellard | { |
371 | e80cfcfc | bellard | // value (T1, T2)
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372 | e80cfcfc | bellard | // address (T0) = dst
|
373 | e80cfcfc | bellard | // fill 32 bytes
|
374 | 83469015 | bellard | int i;
|
375 | 83469015 | bellard | uint32_t dst = T0; |
376 | e80cfcfc | bellard | uint64_t val; |
377 | e80cfcfc | bellard | |
378 | e80cfcfc | bellard | val = (((uint64_t)T1) << 32) | T2;
|
379 | 49be8030 | bellard | tswap64s(&val); |
380 | e80cfcfc | bellard | |
381 | e80cfcfc | bellard | for (i = 0; i < 32; i += 8, dst += 8) { |
382 | e80cfcfc | bellard | cpu_physical_memory_write(dst, (void *) &val, 8); |
383 | e80cfcfc | bellard | } |
384 | e80cfcfc | bellard | } |
385 | e80cfcfc | bellard | return;
|
386 | e8af50a3 | bellard | case 0x20 ... 0x2f: /* MMU passthrough */ |
387 | e8af50a3 | bellard | { |
388 | 02aab46a | bellard | switch(size) {
|
389 | 02aab46a | bellard | case 1: |
390 | 02aab46a | bellard | stb_phys(T0, T1); |
391 | 02aab46a | bellard | break;
|
392 | 02aab46a | bellard | case 2: |
393 | 02aab46a | bellard | stw_phys(T0 & ~1, T1);
|
394 | 02aab46a | bellard | break;
|
395 | 02aab46a | bellard | case 4: |
396 | 02aab46a | bellard | default:
|
397 | 02aab46a | bellard | stl_phys(T0 & ~3, T1);
|
398 | 02aab46a | bellard | break;
|
399 | 02aab46a | bellard | } |
400 | e8af50a3 | bellard | } |
401 | e8af50a3 | bellard | return;
|
402 | e8af50a3 | bellard | default:
|
403 | e8af50a3 | bellard | return;
|
404 | e8af50a3 | bellard | } |
405 | e8af50a3 | bellard | } |
406 | e8af50a3 | bellard | |
407 | 3475187d | bellard | #else
|
408 | 3475187d | bellard | |
409 | 3475187d | bellard | void helper_ld_asi(int asi, int size, int sign) |
410 | 3475187d | bellard | { |
411 | 83469015 | bellard | uint64_t ret = 0;
|
412 | 3475187d | bellard | |
413 | 3475187d | bellard | if (asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
414 | 83469015 | bellard | raise_exception(TT_PRIV_ACT); |
415 | 3475187d | bellard | |
416 | 3475187d | bellard | switch (asi) {
|
417 | 3475187d | bellard | case 0x14: // Bypass |
418 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
419 | 3475187d | bellard | { |
420 | 02aab46a | bellard | switch(size) {
|
421 | 02aab46a | bellard | case 1: |
422 | 02aab46a | bellard | ret = ldub_phys(T0); |
423 | 02aab46a | bellard | break;
|
424 | 02aab46a | bellard | case 2: |
425 | 02aab46a | bellard | ret = lduw_phys(T0 & ~1);
|
426 | 02aab46a | bellard | break;
|
427 | 02aab46a | bellard | case 4: |
428 | 02aab46a | bellard | ret = ldl_phys(T0 & ~3);
|
429 | 02aab46a | bellard | break;
|
430 | 02aab46a | bellard | default:
|
431 | 02aab46a | bellard | case 8: |
432 | 02aab46a | bellard | ret = ldq_phys(T0 & ~7);
|
433 | 02aab46a | bellard | break;
|
434 | 02aab46a | bellard | } |
435 | 3475187d | bellard | break;
|
436 | 3475187d | bellard | } |
437 | 83469015 | bellard | case 0x04: // Nucleus |
438 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
439 | 83469015 | bellard | case 0x10: // As if user primary |
440 | 83469015 | bellard | case 0x11: // As if user secondary |
441 | 83469015 | bellard | case 0x18: // As if user primary LE |
442 | 83469015 | bellard | case 0x19: // As if user secondary LE |
443 | 3475187d | bellard | case 0x1c: // Bypass LE |
444 | 3475187d | bellard | case 0x1d: // Bypass, non-cacheable LE |
445 | 83469015 | bellard | case 0x24: // Nucleus quad LDD 128 bit atomic |
446 | 83469015 | bellard | case 0x2c: // Nucleus quad LDD 128 bit atomic |
447 | 83469015 | bellard | case 0x4a: // UPA config |
448 | 83469015 | bellard | case 0x82: // Primary no-fault |
449 | 83469015 | bellard | case 0x83: // Secondary no-fault |
450 | 83469015 | bellard | case 0x88: // Primary LE |
451 | 83469015 | bellard | case 0x89: // Secondary LE |
452 | 83469015 | bellard | case 0x8a: // Primary no-fault LE |
453 | 83469015 | bellard | case 0x8b: // Secondary no-fault LE |
454 | 3475187d | bellard | // XXX
|
455 | 3475187d | bellard | break;
|
456 | 3475187d | bellard | case 0x45: // LSU |
457 | 3475187d | bellard | ret = env->lsu; |
458 | 3475187d | bellard | break;
|
459 | 3475187d | bellard | case 0x50: // I-MMU regs |
460 | 3475187d | bellard | { |
461 | 3475187d | bellard | int reg = (T0 >> 3) & 0xf; |
462 | 3475187d | bellard | |
463 | 3475187d | bellard | ret = env->immuregs[reg]; |
464 | 3475187d | bellard | break;
|
465 | 3475187d | bellard | } |
466 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer |
467 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer |
468 | 3475187d | bellard | case 0x55: // I-MMU data access |
469 | 83469015 | bellard | // XXX
|
470 | 3475187d | bellard | break;
|
471 | 83469015 | bellard | case 0x56: // I-MMU tag read |
472 | 83469015 | bellard | { |
473 | 83469015 | bellard | unsigned int i; |
474 | 83469015 | bellard | |
475 | 83469015 | bellard | for (i = 0; i < 64; i++) { |
476 | 83469015 | bellard | // Valid, ctx match, vaddr match
|
477 | 83469015 | bellard | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && |
478 | 83469015 | bellard | env->itlb_tag[i] == T0) { |
479 | 83469015 | bellard | ret = env->itlb_tag[i]; |
480 | 83469015 | bellard | break;
|
481 | 83469015 | bellard | } |
482 | 83469015 | bellard | } |
483 | 83469015 | bellard | break;
|
484 | 83469015 | bellard | } |
485 | 3475187d | bellard | case 0x58: // D-MMU regs |
486 | 3475187d | bellard | { |
487 | 3475187d | bellard | int reg = (T0 >> 3) & 0xf; |
488 | 3475187d | bellard | |
489 | 3475187d | bellard | ret = env->dmmuregs[reg]; |
490 | 3475187d | bellard | break;
|
491 | 3475187d | bellard | } |
492 | 83469015 | bellard | case 0x5e: // D-MMU tag read |
493 | 83469015 | bellard | { |
494 | 83469015 | bellard | unsigned int i; |
495 | 83469015 | bellard | |
496 | 83469015 | bellard | for (i = 0; i < 64; i++) { |
497 | 83469015 | bellard | // Valid, ctx match, vaddr match
|
498 | 83469015 | bellard | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && |
499 | 83469015 | bellard | env->dtlb_tag[i] == T0) { |
500 | 83469015 | bellard | ret = env->dtlb_tag[i]; |
501 | 83469015 | bellard | break;
|
502 | 83469015 | bellard | } |
503 | 83469015 | bellard | } |
504 | 83469015 | bellard | break;
|
505 | 83469015 | bellard | } |
506 | 3475187d | bellard | case 0x59: // D-MMU 8k TSB pointer |
507 | 3475187d | bellard | case 0x5a: // D-MMU 64k TSB pointer |
508 | 3475187d | bellard | case 0x5b: // D-MMU data pointer |
509 | 3475187d | bellard | case 0x5d: // D-MMU data access |
510 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
511 | 83469015 | bellard | case 0x49: // Interrupt data receive |
512 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
513 | 83469015 | bellard | // XXX
|
514 | 3475187d | bellard | break;
|
515 | 3475187d | bellard | case 0x54: // I-MMU data in, WO |
516 | 3475187d | bellard | case 0x57: // I-MMU demap, WO |
517 | 3475187d | bellard | case 0x5c: // D-MMU data in, WO |
518 | 3475187d | bellard | case 0x5f: // D-MMU demap, WO |
519 | 83469015 | bellard | case 0x77: // Interrupt vector, WO |
520 | 3475187d | bellard | default:
|
521 | 3475187d | bellard | ret = 0;
|
522 | 3475187d | bellard | break;
|
523 | 3475187d | bellard | } |
524 | 3475187d | bellard | T1 = ret; |
525 | 3475187d | bellard | } |
526 | 3475187d | bellard | |
527 | 3475187d | bellard | void helper_st_asi(int asi, int size, int sign) |
528 | 3475187d | bellard | { |
529 | 3475187d | bellard | if (asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
530 | 83469015 | bellard | raise_exception(TT_PRIV_ACT); |
531 | 3475187d | bellard | |
532 | 3475187d | bellard | switch(asi) {
|
533 | 3475187d | bellard | case 0x14: // Bypass |
534 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
535 | 3475187d | bellard | { |
536 | 02aab46a | bellard | switch(size) {
|
537 | 02aab46a | bellard | case 1: |
538 | 02aab46a | bellard | stb_phys(T0, T1); |
539 | 02aab46a | bellard | break;
|
540 | 02aab46a | bellard | case 2: |
541 | 02aab46a | bellard | stw_phys(T0 & ~1, T1);
|
542 | 02aab46a | bellard | break;
|
543 | 02aab46a | bellard | case 4: |
544 | 02aab46a | bellard | stl_phys(T0 & ~3, T1);
|
545 | 02aab46a | bellard | break;
|
546 | 02aab46a | bellard | case 8: |
547 | 02aab46a | bellard | default:
|
548 | 02aab46a | bellard | stq_phys(T0 & ~7, T1);
|
549 | 02aab46a | bellard | break;
|
550 | 02aab46a | bellard | } |
551 | 3475187d | bellard | } |
552 | 3475187d | bellard | return;
|
553 | 83469015 | bellard | case 0x04: // Nucleus |
554 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
555 | 83469015 | bellard | case 0x10: // As if user primary |
556 | 83469015 | bellard | case 0x11: // As if user secondary |
557 | 83469015 | bellard | case 0x18: // As if user primary LE |
558 | 83469015 | bellard | case 0x19: // As if user secondary LE |
559 | 3475187d | bellard | case 0x1c: // Bypass LE |
560 | 3475187d | bellard | case 0x1d: // Bypass, non-cacheable LE |
561 | 83469015 | bellard | case 0x24: // Nucleus quad LDD 128 bit atomic |
562 | 83469015 | bellard | case 0x2c: // Nucleus quad LDD 128 bit atomic |
563 | 83469015 | bellard | case 0x4a: // UPA config |
564 | 83469015 | bellard | case 0x88: // Primary LE |
565 | 83469015 | bellard | case 0x89: // Secondary LE |
566 | 3475187d | bellard | // XXX
|
567 | 3475187d | bellard | return;
|
568 | 3475187d | bellard | case 0x45: // LSU |
569 | 3475187d | bellard | { |
570 | 3475187d | bellard | uint64_t oldreg; |
571 | 3475187d | bellard | |
572 | 3475187d | bellard | oldreg = env->lsu; |
573 | 3475187d | bellard | env->lsu = T1 & (DMMU_E | IMMU_E); |
574 | 3475187d | bellard | // Mappings generated during D/I MMU disabled mode are
|
575 | 3475187d | bellard | // invalid in normal mode
|
576 | 83469015 | bellard | if (oldreg != env->lsu) {
|
577 | 83469015 | bellard | #ifdef DEBUG_MMU
|
578 | 83469015 | bellard | printf("LSU change: 0x%llx -> 0x%llx\n", oldreg, env->lsu);
|
579 | 83469015 | bellard | dump_mmu(env); |
580 | 83469015 | bellard | #endif
|
581 | 3475187d | bellard | tlb_flush(env, 1);
|
582 | 83469015 | bellard | } |
583 | 3475187d | bellard | return;
|
584 | 3475187d | bellard | } |
585 | 3475187d | bellard | case 0x50: // I-MMU regs |
586 | 3475187d | bellard | { |
587 | 3475187d | bellard | int reg = (T0 >> 3) & 0xf; |
588 | 3475187d | bellard | uint64_t oldreg; |
589 | 3475187d | bellard | |
590 | 3475187d | bellard | oldreg = env->immuregs[reg]; |
591 | 3475187d | bellard | switch(reg) {
|
592 | 3475187d | bellard | case 0: // RO |
593 | 3475187d | bellard | case 4: |
594 | 3475187d | bellard | return;
|
595 | 3475187d | bellard | case 1: // Not in I-MMU |
596 | 3475187d | bellard | case 2: |
597 | 3475187d | bellard | case 7: |
598 | 3475187d | bellard | case 8: |
599 | 3475187d | bellard | return;
|
600 | 3475187d | bellard | case 3: // SFSR |
601 | 3475187d | bellard | if ((T1 & 1) == 0) |
602 | 3475187d | bellard | T1 = 0; // Clear SFSR |
603 | 3475187d | bellard | break;
|
604 | 3475187d | bellard | case 5: // TSB access |
605 | 3475187d | bellard | case 6: // Tag access |
606 | 3475187d | bellard | default:
|
607 | 3475187d | bellard | break;
|
608 | 3475187d | bellard | } |
609 | 3475187d | bellard | env->immuregs[reg] = T1; |
610 | 3475187d | bellard | #ifdef DEBUG_MMU
|
611 | 3475187d | bellard | if (oldreg != env->immuregs[reg]) {
|
612 | 83469015 | bellard | printf("mmu change reg[%d]: 0x%08llx -> 0x%08llx\n", reg, oldreg, env->immuregs[reg]);
|
613 | 3475187d | bellard | } |
614 | ee5bbe38 | bellard | dump_mmu(env); |
615 | 3475187d | bellard | #endif
|
616 | 3475187d | bellard | return;
|
617 | 3475187d | bellard | } |
618 | 3475187d | bellard | case 0x54: // I-MMU data in |
619 | 3475187d | bellard | { |
620 | 3475187d | bellard | unsigned int i; |
621 | 3475187d | bellard | |
622 | 3475187d | bellard | // Try finding an invalid entry
|
623 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
624 | 3475187d | bellard | if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { |
625 | 3475187d | bellard | env->itlb_tag[i] = env->immuregs[6];
|
626 | 3475187d | bellard | env->itlb_tte[i] = T1; |
627 | 3475187d | bellard | return;
|
628 | 3475187d | bellard | } |
629 | 3475187d | bellard | } |
630 | 3475187d | bellard | // Try finding an unlocked entry
|
631 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
632 | 3475187d | bellard | if ((env->itlb_tte[i] & 0x40) == 0) { |
633 | 3475187d | bellard | env->itlb_tag[i] = env->immuregs[6];
|
634 | 3475187d | bellard | env->itlb_tte[i] = T1; |
635 | 3475187d | bellard | return;
|
636 | 3475187d | bellard | } |
637 | 3475187d | bellard | } |
638 | 3475187d | bellard | // error state?
|
639 | 3475187d | bellard | return;
|
640 | 3475187d | bellard | } |
641 | 3475187d | bellard | case 0x55: // I-MMU data access |
642 | 3475187d | bellard | { |
643 | 3475187d | bellard | unsigned int i = (T0 >> 3) & 0x3f; |
644 | 3475187d | bellard | |
645 | 3475187d | bellard | env->itlb_tag[i] = env->immuregs[6];
|
646 | 3475187d | bellard | env->itlb_tte[i] = T1; |
647 | 3475187d | bellard | return;
|
648 | 3475187d | bellard | } |
649 | 3475187d | bellard | case 0x57: // I-MMU demap |
650 | 83469015 | bellard | // XXX
|
651 | 3475187d | bellard | return;
|
652 | 3475187d | bellard | case 0x58: // D-MMU regs |
653 | 3475187d | bellard | { |
654 | 3475187d | bellard | int reg = (T0 >> 3) & 0xf; |
655 | 3475187d | bellard | uint64_t oldreg; |
656 | 3475187d | bellard | |
657 | 3475187d | bellard | oldreg = env->dmmuregs[reg]; |
658 | 3475187d | bellard | switch(reg) {
|
659 | 3475187d | bellard | case 0: // RO |
660 | 3475187d | bellard | case 4: |
661 | 3475187d | bellard | return;
|
662 | 3475187d | bellard | case 3: // SFSR |
663 | 3475187d | bellard | if ((T1 & 1) == 0) { |
664 | 3475187d | bellard | T1 = 0; // Clear SFSR, Fault address |
665 | 3475187d | bellard | env->dmmuregs[4] = 0; |
666 | 3475187d | bellard | } |
667 | 3475187d | bellard | env->dmmuregs[reg] = T1; |
668 | 3475187d | bellard | break;
|
669 | 3475187d | bellard | case 1: // Primary context |
670 | 3475187d | bellard | case 2: // Secondary context |
671 | 3475187d | bellard | case 5: // TSB access |
672 | 3475187d | bellard | case 6: // Tag access |
673 | 3475187d | bellard | case 7: // Virtual Watchpoint |
674 | 3475187d | bellard | case 8: // Physical Watchpoint |
675 | 3475187d | bellard | default:
|
676 | 3475187d | bellard | break;
|
677 | 3475187d | bellard | } |
678 | 3475187d | bellard | env->dmmuregs[reg] = T1; |
679 | 3475187d | bellard | #ifdef DEBUG_MMU
|
680 | 3475187d | bellard | if (oldreg != env->dmmuregs[reg]) {
|
681 | 83469015 | bellard | printf("mmu change reg[%d]: 0x%08llx -> 0x%08llx\n", reg, oldreg, env->dmmuregs[reg]);
|
682 | 3475187d | bellard | } |
683 | ee5bbe38 | bellard | dump_mmu(env); |
684 | 3475187d | bellard | #endif
|
685 | 3475187d | bellard | return;
|
686 | 3475187d | bellard | } |
687 | 3475187d | bellard | case 0x5c: // D-MMU data in |
688 | 3475187d | bellard | { |
689 | 3475187d | bellard | unsigned int i; |
690 | 3475187d | bellard | |
691 | 3475187d | bellard | // Try finding an invalid entry
|
692 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
693 | 3475187d | bellard | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { |
694 | 3475187d | bellard | env->dtlb_tag[i] = env->dmmuregs[6];
|
695 | 3475187d | bellard | env->dtlb_tte[i] = T1; |
696 | 3475187d | bellard | return;
|
697 | 3475187d | bellard | } |
698 | 3475187d | bellard | } |
699 | 3475187d | bellard | // Try finding an unlocked entry
|
700 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
701 | 3475187d | bellard | if ((env->dtlb_tte[i] & 0x40) == 0) { |
702 | 3475187d | bellard | env->dtlb_tag[i] = env->dmmuregs[6];
|
703 | 3475187d | bellard | env->dtlb_tte[i] = T1; |
704 | 3475187d | bellard | return;
|
705 | 3475187d | bellard | } |
706 | 3475187d | bellard | } |
707 | 3475187d | bellard | // error state?
|
708 | 3475187d | bellard | return;
|
709 | 3475187d | bellard | } |
710 | 3475187d | bellard | case 0x5d: // D-MMU data access |
711 | 3475187d | bellard | { |
712 | 3475187d | bellard | unsigned int i = (T0 >> 3) & 0x3f; |
713 | 3475187d | bellard | |
714 | 3475187d | bellard | env->dtlb_tag[i] = env->dmmuregs[6];
|
715 | 3475187d | bellard | env->dtlb_tte[i] = T1; |
716 | 3475187d | bellard | return;
|
717 | 3475187d | bellard | } |
718 | 3475187d | bellard | case 0x5f: // D-MMU demap |
719 | 83469015 | bellard | case 0x49: // Interrupt data receive |
720 | 83469015 | bellard | // XXX
|
721 | 3475187d | bellard | return;
|
722 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer, RO |
723 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer, RO |
724 | 3475187d | bellard | case 0x56: // I-MMU tag read, RO |
725 | 3475187d | bellard | case 0x59: // D-MMU 8k TSB pointer, RO |
726 | 3475187d | bellard | case 0x5a: // D-MMU 64k TSB pointer, RO |
727 | 3475187d | bellard | case 0x5b: // D-MMU data pointer, RO |
728 | 3475187d | bellard | case 0x5e: // D-MMU tag read, RO |
729 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
730 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
731 | 83469015 | bellard | case 0x82: // Primary no-fault, RO |
732 | 83469015 | bellard | case 0x83: // Secondary no-fault, RO |
733 | 83469015 | bellard | case 0x8a: // Primary no-fault LE, RO |
734 | 83469015 | bellard | case 0x8b: // Secondary no-fault LE, RO |
735 | 3475187d | bellard | default:
|
736 | 3475187d | bellard | return;
|
737 | 3475187d | bellard | } |
738 | 3475187d | bellard | } |
739 | 3475187d | bellard | #endif
|
740 | 24741ef3 | bellard | #endif /* !CONFIG_USER_ONLY */ |
741 | 3475187d | bellard | |
742 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
743 | a0c4cb4a | bellard | void helper_rett()
|
744 | e8af50a3 | bellard | { |
745 | af7bf89b | bellard | unsigned int cwp; |
746 | af7bf89b | bellard | |
747 | e8af50a3 | bellard | env->psret = 1;
|
748 | e8af50a3 | bellard | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
749 | e8af50a3 | bellard | if (env->wim & (1 << cwp)) { |
750 | e8af50a3 | bellard | raise_exception(TT_WIN_UNF); |
751 | e8af50a3 | bellard | } |
752 | e8af50a3 | bellard | set_cwp(cwp); |
753 | e8af50a3 | bellard | env->psrs = env->psrps; |
754 | e8af50a3 | bellard | } |
755 | 3475187d | bellard | #endif
|
756 | e8af50a3 | bellard | |
757 | 8d5f07fa | bellard | void helper_ldfsr(void) |
758 | e8af50a3 | bellard | { |
759 | 7a0e1f41 | bellard | int rnd_mode;
|
760 | e8af50a3 | bellard | switch (env->fsr & FSR_RD_MASK) {
|
761 | e8af50a3 | bellard | case FSR_RD_NEAREST:
|
762 | 7a0e1f41 | bellard | rnd_mode = float_round_nearest_even; |
763 | e8af50a3 | bellard | break;
|
764 | ed910241 | bellard | default:
|
765 | e8af50a3 | bellard | case FSR_RD_ZERO:
|
766 | 7a0e1f41 | bellard | rnd_mode = float_round_to_zero; |
767 | e8af50a3 | bellard | break;
|
768 | e8af50a3 | bellard | case FSR_RD_POS:
|
769 | 7a0e1f41 | bellard | rnd_mode = float_round_up; |
770 | e8af50a3 | bellard | break;
|
771 | e8af50a3 | bellard | case FSR_RD_NEG:
|
772 | 7a0e1f41 | bellard | rnd_mode = float_round_down; |
773 | e8af50a3 | bellard | break;
|
774 | e8af50a3 | bellard | } |
775 | 7a0e1f41 | bellard | set_float_rounding_mode(rnd_mode, &env->fp_status); |
776 | e8af50a3 | bellard | } |
777 | e80cfcfc | bellard | |
778 | e80cfcfc | bellard | void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f) |
779 | e80cfcfc | bellard | { |
780 | e80cfcfc | bellard | int exptemp;
|
781 | e80cfcfc | bellard | |
782 | e80cfcfc | bellard | *pmant = ldexp(frexp(f, &exptemp), 53);
|
783 | e80cfcfc | bellard | *pexp = exptemp; |
784 | e80cfcfc | bellard | } |
785 | e80cfcfc | bellard | |
786 | e80cfcfc | bellard | double cpu_put_fp64(uint64_t mant, uint16_t exp)
|
787 | e80cfcfc | bellard | { |
788 | e80cfcfc | bellard | return ldexp((double) mant, exp - 53); |
789 | e80cfcfc | bellard | } |
790 | e80cfcfc | bellard | |
791 | e80cfcfc | bellard | void helper_debug()
|
792 | e80cfcfc | bellard | { |
793 | e80cfcfc | bellard | env->exception_index = EXCP_DEBUG; |
794 | e80cfcfc | bellard | cpu_loop_exit(); |
795 | e80cfcfc | bellard | } |
796 | af7bf89b | bellard | |
797 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
798 | af7bf89b | bellard | void do_wrpsr()
|
799 | af7bf89b | bellard | { |
800 | af7bf89b | bellard | PUT_PSR(env, T0); |
801 | af7bf89b | bellard | } |
802 | af7bf89b | bellard | |
803 | af7bf89b | bellard | void do_rdpsr()
|
804 | af7bf89b | bellard | { |
805 | af7bf89b | bellard | T0 = GET_PSR(env); |
806 | af7bf89b | bellard | } |
807 | 3475187d | bellard | |
808 | 3475187d | bellard | #else
|
809 | 3475187d | bellard | |
810 | 3475187d | bellard | void do_popc()
|
811 | 3475187d | bellard | { |
812 | 3475187d | bellard | T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL); |
813 | 3475187d | bellard | T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL); |
814 | 3475187d | bellard | T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL); |
815 | 3475187d | bellard | T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL); |
816 | 3475187d | bellard | T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL); |
817 | 3475187d | bellard | T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL); |
818 | 3475187d | bellard | } |
819 | 83469015 | bellard | |
820 | 83469015 | bellard | static inline uint64_t *get_gregset(uint64_t pstate) |
821 | 83469015 | bellard | { |
822 | 83469015 | bellard | switch (pstate) {
|
823 | 83469015 | bellard | default:
|
824 | 83469015 | bellard | case 0: |
825 | 83469015 | bellard | return env->bgregs;
|
826 | 83469015 | bellard | case PS_AG:
|
827 | 83469015 | bellard | return env->agregs;
|
828 | 83469015 | bellard | case PS_MG:
|
829 | 83469015 | bellard | return env->mgregs;
|
830 | 83469015 | bellard | case PS_IG:
|
831 | 83469015 | bellard | return env->igregs;
|
832 | 83469015 | bellard | } |
833 | 83469015 | bellard | } |
834 | 83469015 | bellard | |
835 | 83469015 | bellard | void do_wrpstate()
|
836 | 83469015 | bellard | { |
837 | 83469015 | bellard | uint64_t new_pstate, pstate_regs, new_pstate_regs; |
838 | 83469015 | bellard | uint64_t *src, *dst; |
839 | 83469015 | bellard | |
840 | 83469015 | bellard | new_pstate = T0 & 0xf3f;
|
841 | 83469015 | bellard | pstate_regs = env->pstate & 0xc01;
|
842 | 83469015 | bellard | new_pstate_regs = new_pstate & 0xc01;
|
843 | 83469015 | bellard | if (new_pstate_regs != pstate_regs) {
|
844 | 83469015 | bellard | // Switch global register bank
|
845 | 83469015 | bellard | src = get_gregset(new_pstate_regs); |
846 | 83469015 | bellard | dst = get_gregset(pstate_regs); |
847 | 83469015 | bellard | memcpy32(dst, env->gregs); |
848 | 83469015 | bellard | memcpy32(env->gregs, src); |
849 | 83469015 | bellard | } |
850 | 83469015 | bellard | env->pstate = new_pstate; |
851 | 83469015 | bellard | } |
852 | 83469015 | bellard | |
853 | 83469015 | bellard | void do_done(void) |
854 | 83469015 | bellard | { |
855 | 83469015 | bellard | env->tl--; |
856 | 83469015 | bellard | env->pc = env->tnpc[env->tl]; |
857 | 83469015 | bellard | env->npc = env->tnpc[env->tl] + 4;
|
858 | 83469015 | bellard | PUT_CCR(env, env->tstate[env->tl] >> 32);
|
859 | 83469015 | bellard | env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
860 | 83469015 | bellard | env->pstate = (env->tstate[env->tl] >> 8) & 0xfff; |
861 | 83469015 | bellard | set_cwp(env->tstate[env->tl] & 0xff);
|
862 | 83469015 | bellard | } |
863 | 83469015 | bellard | |
864 | 83469015 | bellard | void do_retry(void) |
865 | 83469015 | bellard | { |
866 | 83469015 | bellard | env->tl--; |
867 | 83469015 | bellard | env->pc = env->tpc[env->tl]; |
868 | 83469015 | bellard | env->npc = env->tnpc[env->tl]; |
869 | 83469015 | bellard | PUT_CCR(env, env->tstate[env->tl] >> 32);
|
870 | 83469015 | bellard | env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
871 | 83469015 | bellard | env->pstate = (env->tstate[env->tl] >> 8) & 0xfff; |
872 | 83469015 | bellard | set_cwp(env->tstate[env->tl] & 0xff);
|
873 | 83469015 | bellard | } |
874 | 3475187d | bellard | #endif
|
875 | ee5bbe38 | bellard | |
876 | ee5bbe38 | bellard | void set_cwp(int new_cwp) |
877 | ee5bbe38 | bellard | { |
878 | ee5bbe38 | bellard | /* put the modified wrap registers at their proper location */
|
879 | ee5bbe38 | bellard | if (env->cwp == (NWINDOWS - 1)) |
880 | ee5bbe38 | bellard | memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
881 | ee5bbe38 | bellard | env->cwp = new_cwp; |
882 | ee5bbe38 | bellard | /* put the wrap registers at their temporary location */
|
883 | ee5bbe38 | bellard | if (new_cwp == (NWINDOWS - 1)) |
884 | ee5bbe38 | bellard | memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
885 | ee5bbe38 | bellard | env->regwptr = env->regbase + (new_cwp * 16);
|
886 | ee5bbe38 | bellard | REGWPTR = env->regwptr; |
887 | ee5bbe38 | bellard | } |
888 | ee5bbe38 | bellard | |
889 | ee5bbe38 | bellard | void cpu_set_cwp(CPUState *env1, int new_cwp) |
890 | ee5bbe38 | bellard | { |
891 | ee5bbe38 | bellard | CPUState *saved_env; |
892 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
893 | ee5bbe38 | bellard | target_ulong *saved_regwptr; |
894 | ee5bbe38 | bellard | #endif
|
895 | ee5bbe38 | bellard | |
896 | ee5bbe38 | bellard | saved_env = env; |
897 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
898 | ee5bbe38 | bellard | saved_regwptr = REGWPTR; |
899 | ee5bbe38 | bellard | #endif
|
900 | ee5bbe38 | bellard | env = env1; |
901 | ee5bbe38 | bellard | set_cwp(new_cwp); |
902 | ee5bbe38 | bellard | env = saved_env; |
903 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
904 | ee5bbe38 | bellard | REGWPTR = saved_regwptr; |
905 | ee5bbe38 | bellard | #endif
|
906 | ee5bbe38 | bellard | } |
907 | ee5bbe38 | bellard | |
908 | ee5bbe38 | bellard | #ifdef TARGET_SPARC64
|
909 | ee5bbe38 | bellard | void do_interrupt(int intno) |
910 | ee5bbe38 | bellard | { |
911 | ee5bbe38 | bellard | #ifdef DEBUG_PCALL
|
912 | ee5bbe38 | bellard | if (loglevel & CPU_LOG_INT) {
|
913 | ee5bbe38 | bellard | static int count; |
914 | 83469015 | bellard | fprintf(logfile, "%6d: v=%04x pc=%016llx npc=%016llx SP=%016llx\n",
|
915 | ee5bbe38 | bellard | count, intno, |
916 | ee5bbe38 | bellard | env->pc, |
917 | ee5bbe38 | bellard | env->npc, env->regwptr[6]);
|
918 | ee5bbe38 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
919 | ee5bbe38 | bellard | #if 0
|
920 | ee5bbe38 | bellard | {
|
921 | ee5bbe38 | bellard | int i;
|
922 | ee5bbe38 | bellard | uint8_t *ptr;
|
923 | ee5bbe38 | bellard | |
924 | ee5bbe38 | bellard | fprintf(logfile, " code=");
|
925 | ee5bbe38 | bellard | ptr = (uint8_t *)env->pc;
|
926 | ee5bbe38 | bellard | for(i = 0; i < 16; i++) {
|
927 | ee5bbe38 | bellard | fprintf(logfile, " %02x", ldub(ptr + i));
|
928 | ee5bbe38 | bellard | }
|
929 | ee5bbe38 | bellard | fprintf(logfile, "\n");
|
930 | ee5bbe38 | bellard | }
|
931 | ee5bbe38 | bellard | #endif
|
932 | ee5bbe38 | bellard | count++; |
933 | ee5bbe38 | bellard | } |
934 | ee5bbe38 | bellard | #endif
|
935 | ee5bbe38 | bellard | #if !defined(CONFIG_USER_ONLY)
|
936 | 83469015 | bellard | if (env->tl == MAXTL) {
|
937 | 83469015 | bellard | cpu_abort(cpu_single_env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
938 | ee5bbe38 | bellard | return;
|
939 | ee5bbe38 | bellard | } |
940 | ee5bbe38 | bellard | #endif
|
941 | ee5bbe38 | bellard | env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | |
942 | ee5bbe38 | bellard | ((env->pstate & 0xfff) << 8) | (env->cwp & 0xff); |
943 | ee5bbe38 | bellard | env->tpc[env->tl] = env->pc; |
944 | ee5bbe38 | bellard | env->tnpc[env->tl] = env->npc; |
945 | ee5bbe38 | bellard | env->tt[env->tl] = intno; |
946 | 83469015 | bellard | env->pstate = PS_PEF | PS_PRIV | PS_AG; |
947 | 83469015 | bellard | env->tbr &= ~0x7fffULL;
|
948 | 83469015 | bellard | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
949 | 83469015 | bellard | if (env->tl < MAXTL - 1) { |
950 | 83469015 | bellard | env->tl++; |
951 | 83469015 | bellard | } else {
|
952 | 83469015 | bellard | env->pstate |= PS_RED; |
953 | 83469015 | bellard | if (env->tl != MAXTL)
|
954 | 83469015 | bellard | env->tl++; |
955 | 83469015 | bellard | } |
956 | ee5bbe38 | bellard | env->pc = env->tbr; |
957 | ee5bbe38 | bellard | env->npc = env->pc + 4;
|
958 | ee5bbe38 | bellard | env->exception_index = 0;
|
959 | ee5bbe38 | bellard | } |
960 | ee5bbe38 | bellard | #else
|
961 | ee5bbe38 | bellard | void do_interrupt(int intno) |
962 | ee5bbe38 | bellard | { |
963 | ee5bbe38 | bellard | int cwp;
|
964 | ee5bbe38 | bellard | |
965 | ee5bbe38 | bellard | #ifdef DEBUG_PCALL
|
966 | ee5bbe38 | bellard | if (loglevel & CPU_LOG_INT) {
|
967 | ee5bbe38 | bellard | static int count; |
968 | ee5bbe38 | bellard | fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
|
969 | ee5bbe38 | bellard | count, intno, |
970 | ee5bbe38 | bellard | env->pc, |
971 | ee5bbe38 | bellard | env->npc, env->regwptr[6]);
|
972 | ee5bbe38 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
973 | ee5bbe38 | bellard | #if 0
|
974 | ee5bbe38 | bellard | {
|
975 | ee5bbe38 | bellard | int i;
|
976 | ee5bbe38 | bellard | uint8_t *ptr;
|
977 | ee5bbe38 | bellard | |
978 | ee5bbe38 | bellard | fprintf(logfile, " code=");
|
979 | ee5bbe38 | bellard | ptr = (uint8_t *)env->pc;
|
980 | ee5bbe38 | bellard | for(i = 0; i < 16; i++) {
|
981 | ee5bbe38 | bellard | fprintf(logfile, " %02x", ldub(ptr + i));
|
982 | ee5bbe38 | bellard | }
|
983 | ee5bbe38 | bellard | fprintf(logfile, "\n");
|
984 | ee5bbe38 | bellard | }
|
985 | ee5bbe38 | bellard | #endif
|
986 | ee5bbe38 | bellard | count++; |
987 | ee5bbe38 | bellard | } |
988 | ee5bbe38 | bellard | #endif
|
989 | ee5bbe38 | bellard | #if !defined(CONFIG_USER_ONLY)
|
990 | ee5bbe38 | bellard | if (env->psret == 0) { |
991 | ee5bbe38 | bellard | cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
992 | ee5bbe38 | bellard | return;
|
993 | ee5bbe38 | bellard | } |
994 | ee5bbe38 | bellard | #endif
|
995 | ee5bbe38 | bellard | env->psret = 0;
|
996 | ee5bbe38 | bellard | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
997 | ee5bbe38 | bellard | set_cwp(cwp); |
998 | ee5bbe38 | bellard | env->regwptr[9] = env->pc;
|
999 | ee5bbe38 | bellard | env->regwptr[10] = env->npc;
|
1000 | ee5bbe38 | bellard | env->psrps = env->psrs; |
1001 | ee5bbe38 | bellard | env->psrs = 1;
|
1002 | ee5bbe38 | bellard | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
1003 | ee5bbe38 | bellard | env->pc = env->tbr; |
1004 | ee5bbe38 | bellard | env->npc = env->pc + 4;
|
1005 | ee5bbe38 | bellard | env->exception_index = 0;
|
1006 | ee5bbe38 | bellard | } |
1007 | ee5bbe38 | bellard | #endif
|
1008 | ee5bbe38 | bellard | |
1009 | ee5bbe38 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1010 | ee5bbe38 | bellard | |
1011 | ee5bbe38 | bellard | #define MMUSUFFIX _mmu
|
1012 | ee5bbe38 | bellard | #define GETPC() (__builtin_return_address(0)) |
1013 | ee5bbe38 | bellard | |
1014 | ee5bbe38 | bellard | #define SHIFT 0 |
1015 | ee5bbe38 | bellard | #include "softmmu_template.h" |
1016 | ee5bbe38 | bellard | |
1017 | ee5bbe38 | bellard | #define SHIFT 1 |
1018 | ee5bbe38 | bellard | #include "softmmu_template.h" |
1019 | ee5bbe38 | bellard | |
1020 | ee5bbe38 | bellard | #define SHIFT 2 |
1021 | ee5bbe38 | bellard | #include "softmmu_template.h" |
1022 | ee5bbe38 | bellard | |
1023 | ee5bbe38 | bellard | #define SHIFT 3 |
1024 | ee5bbe38 | bellard | #include "softmmu_template.h" |
1025 | ee5bbe38 | bellard | |
1026 | ee5bbe38 | bellard | |
1027 | ee5bbe38 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
|
1028 | ee5bbe38 | bellard | NULL, it means that the function was called in C code (i.e. not
|
1029 | ee5bbe38 | bellard | from generated code or from helper.c) */
|
1030 | ee5bbe38 | bellard | /* XXX: fix it to restore all registers */
|
1031 | ee5bbe38 | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
1032 | ee5bbe38 | bellard | { |
1033 | ee5bbe38 | bellard | TranslationBlock *tb; |
1034 | ee5bbe38 | bellard | int ret;
|
1035 | ee5bbe38 | bellard | unsigned long pc; |
1036 | ee5bbe38 | bellard | CPUState *saved_env; |
1037 | ee5bbe38 | bellard | |
1038 | ee5bbe38 | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
1039 | ee5bbe38 | bellard | generated code */
|
1040 | ee5bbe38 | bellard | saved_env = env; |
1041 | ee5bbe38 | bellard | env = cpu_single_env; |
1042 | ee5bbe38 | bellard | |
1043 | ee5bbe38 | bellard | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
1044 | ee5bbe38 | bellard | if (ret) {
|
1045 | ee5bbe38 | bellard | if (retaddr) {
|
1046 | ee5bbe38 | bellard | /* now we have a real cpu fault */
|
1047 | ee5bbe38 | bellard | pc = (unsigned long)retaddr; |
1048 | ee5bbe38 | bellard | tb = tb_find_pc(pc); |
1049 | ee5bbe38 | bellard | if (tb) {
|
1050 | ee5bbe38 | bellard | /* the PC is inside the translated code. It means that we have
|
1051 | ee5bbe38 | bellard | a virtual CPU fault */
|
1052 | ee5bbe38 | bellard | cpu_restore_state(tb, env, pc, (void *)T2);
|
1053 | ee5bbe38 | bellard | } |
1054 | ee5bbe38 | bellard | } |
1055 | ee5bbe38 | bellard | cpu_loop_exit(); |
1056 | ee5bbe38 | bellard | } |
1057 | ee5bbe38 | bellard | env = saved_env; |
1058 | ee5bbe38 | bellard | } |
1059 | ee5bbe38 | bellard | |
1060 | ee5bbe38 | bellard | #endif |