Revision 24c7b0e3 hw/mips_int.c

b/hw/mips_int.c
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   IRQ may change */
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void cpu_mips_update_irq(CPUState *env)
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{
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    if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
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        (env->CP0_Status & (1 << CP0St_IE)) &&
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        !(env->hflags & MIPS_HFLAG_EXL) &&
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	!(env->hflags & MIPS_HFLAG_ERL) &&
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	!(env->hflags & MIPS_HFLAG_DM)) {
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        if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
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    if ((env->CP0_Status & (1 << CP0St_IE)) &&
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        !(env->CP0_Status & (1 << CP0St_EXL)) &&
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        !(env->CP0_Status & (1 << CP0St_ERL)) &&
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        !(env->hflags & MIPS_HFLAG_DM)) {
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        if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
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            !(env->interrupt_request & CPU_INTERRUPT_HARD)) {
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            cpu_interrupt(env, CPU_INTERRUPT_HARD);
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	}
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    } else {
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    } else
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        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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    }
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}
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void cpu_mips_irq_request(void *opaque, int irq, int level)


  		












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