Revision 24c7b0e3 target-mips/op.c
| b/target-mips/op.c | ||
|---|---|---|
| 1105 | 1105 |
void op_mfc0_status (void) |
| 1106 | 1106 |
{
|
| 1107 | 1107 |
T0 = env->CP0_Status; |
| 1108 |
if (env->hflags & MIPS_HFLAG_UM) |
|
| 1109 |
T0 |= (1 << CP0St_UM); |
|
| 1110 |
if (env->hflags & MIPS_HFLAG_ERL) |
|
| 1111 |
T0 |= (1 << CP0St_ERL); |
|
| 1112 |
if (env->hflags & MIPS_HFLAG_EXL) |
|
| 1113 |
T0 |= (1 << CP0St_EXL); |
|
| 1114 | 1108 |
RETURN(); |
| 1115 | 1109 |
} |
| 1116 | 1110 |
|
| ... | ... | |
| 1365 | 1359 |
{
|
| 1366 | 1360 |
uint32_t val, old; |
| 1367 | 1361 |
|
| 1368 |
val = (int32_t)T0 & 0xFA78FF01; |
|
| 1362 |
/* No 64bit FPU, no reverse endianness, no MDMX/DSP, no 64bit ops, |
|
| 1363 |
no 64bit addressing implemented. */ |
|
| 1364 |
val = (int32_t)T0 & 0xF878FF17; |
|
| 1369 | 1365 |
old = env->CP0_Status; |
| 1370 |
if (T0 & (1 << CP0St_UM)) |
|
| 1371 |
env->hflags |= MIPS_HFLAG_UM; |
|
| 1372 |
else |
|
| 1373 |
env->hflags &= ~MIPS_HFLAG_UM; |
|
| 1374 |
if (T0 & (1 << CP0St_ERL)) |
|
| 1375 |
env->hflags |= MIPS_HFLAG_ERL; |
|
| 1376 |
else |
|
| 1377 |
env->hflags &= ~MIPS_HFLAG_ERL; |
|
| 1378 |
if (T0 & (1 << CP0St_EXL)) |
|
| 1379 |
env->hflags |= MIPS_HFLAG_EXL; |
|
| 1380 |
else |
|
| 1381 |
env->hflags &= ~MIPS_HFLAG_EXL; |
|
| 1382 | 1366 |
env->CP0_Status = val; |
| 1383 | 1367 |
if (loglevel & CPU_LOG_TB_IN_ASM) |
| 1384 | 1368 |
CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
| ... | ... | |
| 1662 | 1646 |
# define DEBUG_FPU_STATE() do { } while(0)
|
| 1663 | 1647 |
#endif |
| 1664 | 1648 |
|
| 1649 |
void op_cp0_enabled(void) |
|
| 1650 |
{
|
|
| 1651 |
if (!(env->CP0_Status & (1 << CP0St_CU0)) && |
|
| 1652 |
(env->hflags & MIPS_HFLAG_UM)) {
|
|
| 1653 |
CALL_FROM_TB2(do_raise_exception_direct_err, EXCP_CpU, 0); |
|
| 1654 |
} |
|
| 1655 |
RETURN(); |
|
| 1656 |
} |
|
| 1657 |
|
|
| 1665 | 1658 |
void op_cp1_enabled(void) |
| 1666 | 1659 |
{
|
| 1667 | 1660 |
if (!(env->CP0_Status & (1 << CP0St_CU1))) {
|
| ... | ... | |
| 2091 | 2084 |
void op_eret (void) |
| 2092 | 2085 |
{
|
| 2093 | 2086 |
CALL_FROM_TB0(debug_eret); |
| 2094 |
if (env->hflags & MIPS_HFLAG_ERL) {
|
|
| 2087 |
if (env->CP0_Status & (1 << CP0St_ERL)) {
|
|
| 2095 | 2088 |
env->PC = env->CP0_ErrorEPC; |
| 2096 |
env->hflags &= ~MIPS_HFLAG_ERL; |
|
| 2097 |
env->CP0_Status &= ~(1 << CP0St_ERL); |
|
| 2089 |
env->CP0_Status &= ~(1 << CP0St_ERL); |
|
| 2098 | 2090 |
} else {
|
| 2099 | 2091 |
env->PC = env->CP0_EPC; |
| 2100 |
env->hflags &= ~MIPS_HFLAG_EXL; |
|
| 2101 |
env->CP0_Status &= ~(1 << CP0St_EXL); |
|
| 2092 |
env->CP0_Status &= ~(1 << CP0St_EXL); |
|
| 2102 | 2093 |
} |
| 2094 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
|
| 2095 |
!(env->CP0_Status & (1 << CP0St_ERL)) && |
|
| 2096 |
!(env->hflags & MIPS_HFLAG_DM) && |
|
| 2097 |
(env->CP0_Status & (1 << CP0St_UM))) |
|
| 2098 |
env->hflags |= MIPS_HFLAG_UM; |
|
| 2103 | 2099 |
env->CP0_LLAddr = 1; |
| 2104 | 2100 |
RETURN(); |
| 2105 | 2101 |
} |
| ... | ... | |
| 2108 | 2104 |
{
|
| 2109 | 2105 |
CALL_FROM_TB0(debug_eret); |
| 2110 | 2106 |
env->PC = env->CP0_DEPC; |
| 2107 |
env->hflags |= MIPS_HFLAG_DM; |
|
| 2108 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
|
| 2109 |
!(env->CP0_Status & (1 << CP0St_ERL)) && |
|
| 2110 |
!(env->hflags & MIPS_HFLAG_DM) && |
|
| 2111 |
(env->CP0_Status & (1 << CP0St_UM))) |
|
| 2112 |
env->hflags |= MIPS_HFLAG_UM; |
|
| 2113 |
env->CP0_LLAddr = 1; |
|
| 2111 | 2114 |
RETURN(); |
| 2112 | 2115 |
} |
| 2113 | 2116 |
|
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