Revision 24c7b0e3 target-mips/translate.c

b/target-mips/translate.c
4022 4022
{
4023 4023
    const char *opn = "unk";
4024 4024

  
4025
    if ((!ctx->CP0_Status & (1 << CP0St_CU0) &&
4026
          (ctx->hflags & MIPS_HFLAG_UM)) &&
4027
        !(ctx->hflags & MIPS_HFLAG_ERL) &&
4028
        !(ctx->hflags & MIPS_HFLAG_EXL)) {
4029
        if (loglevel & CPU_LOG_TB_IN_ASM) {
4030
            fprintf(logfile, "CP0 is not usable\n");
4031
        }
4032
        generate_exception (ctx, EXCP_CpU);
4033
        return;
4034
    }
4035

  
4036 4025
    switch (opc) {
4037 4026
    case OPC_MFC0:
4038 4027
        if (rt == 0) {
......
4809 4798
            gen_trap(ctx, op1, rs, -1, imm);
4810 4799
            break;
4811 4800
        case OPC_SYNCI:
4812
           /* treat as noop */
4801
            /* treat as noop */
4813 4802
            break;
4814 4803
        default:            /* Invalid */
4815 4804
            MIPS_INVAL("REGIMM");
......
4818 4807
        }
4819 4808
        break;
4820 4809
    case OPC_CP0:
4810
        gen_op_cp0_enabled();
4821 4811
        op1 = MASK_CP0(ctx->opcode);
4822 4812
        switch (op1) {
4823 4813
        case OPC_MFC0:
......
5258 5248
    }
5259 5249

  
5260 5250
    c0_status = env->CP0_Status;
5261
    if (env->hflags & MIPS_HFLAG_UM)
5262
        c0_status |= (1 << CP0St_UM);
5263
    if (env->hflags & MIPS_HFLAG_ERL)
5264
        c0_status |= (1 << CP0St_ERL);
5265
    if (env->hflags & MIPS_HFLAG_EXL)
5266
        c0_status |= (1 << CP0St_EXL);
5267 5251

  
5268 5252
    cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",
5269 5253
                c0_status, env->CP0_Cause, env->CP0_EPC);
......
5304 5288
    } else {
5305 5289
        env->CP0_ErrorEPC = env->PC;
5306 5290
    }
5291
    env->hflags = 0;
5307 5292
    env->PC = (int32_t)0xBFC00000;
5308 5293
#if defined (MIPS_USES_R4K_TLB)
5309 5294
    env->CP0_Random = MIPS_TLB_NB - 1;
......
5314 5299
    env->CP0_EBase = 0x80000000;
5315 5300
    env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
5316 5301
    env->CP0_WatchLo = 0;
5317
    env->hflags = MIPS_HFLAG_ERL;
5318 5302
    /* Count register increments in debug mode, EJTAG version 1 */
5319 5303
    env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
5320 5304
#endif

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