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# Date Author Comment
24e838b7 03/24/2011 04:27 am Peter Maydell

tcg/arm: Support host code being compiled for Thumb

Although the TCG generated code is always in ARM mode, it is possible
that the host code was compiled by gcc in Thumb mode (this is often the
default for Linux distributions targeting ARM v7 only). Handle this...

56779034 01/12/2011 01:06 am Aurelien Jarno

tcg arm/mips/ia64: add a comment about retranslation and caches

Add a comment about cache coherency and retranslation, so that people
developping new targets based on existing ones are warned of the issue.

Acked-by: Edgar E. Iglesias <>...

0f11f25a 01/10/2011 08:30 am Aurelien Jarno

tcg/arm: improve constant loading

Improve constant loading in two ways:
- On all ARM versions, it's possible to load 0xffffff00 = 0x100 using
the mvn rd, #0. Fix the conditions.
On <= ARMv6 versions, where movw and movt are not available, load the
constants using mov and orr with rotations depending on the constant...

9a3abc21 01/08/2011 05:41 pm Aurelien Jarno

tcg/arm: fix qemu_st64 for big endian targets

Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of
a 64 bit word before saving it. This patch fixes that.

Acked-by: Andrzej Zaborowski <>
Signed-off-by: Aurelien Jarno <>

c69806ab 01/08/2011 05:39 pm Aurelien Jarno

tcg/arm: fix branch target change during code retranslation

QEMU uses code retranslation to restore the CPU state when an exception
happens. For it to work the retranslation must not modify the generated
code. This is what is currently implemented in ARM TCG....

e4d58b41 06/09/2010 12:18 pm Richard Henderson

tcg: Make some tcg-target.c routines static.

Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

3b6dac34 06/09/2010 12:18 pm Richard Henderson

tcg: Add TYPE parameter to tcg_out_mov.

Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"...

e23886a9 04/25/2010 06:46 am Aurelien Jarno

tcg/arm: fix condition in zero/sign extension functions

Signed-off-by: Aurelien Jarno <>

7e0d9562 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: remove conditional argument for qemu_ld/st

While it make sense to pass a conditional argument to tcg_out_*()
functions as the ARM architecture allows that, it doesn't make sense
for qemu_ld/st functions. These functions use comparison instructions...

e854b6d3 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: use ext* ops in qemu_ld

Signed-off-by: Aurelien Jarno <>

67dcab73 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: bswap arguments in qemu_ld/st if needed

On big endian targets, data arguments of qemu_ld/st ops have to be
byte swapped. Two temporary registers are needed for qemu_st to do
the bswap. r0 and r1 are used in system mode, do the same in user
mode, which implies reworking the constraints....

2633a2d0 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: remove useless register tests in qemu_ld/st

addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to the
constraints. Don't check if they equals these registers.

Signed-off-by: Aurelien Jarno <>

bf5675ef 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: fix argument alignment in qemu_st64

64-bit arguments should be aligned on an even register as specified
by the "Procedure Call Standard for the ARM Architecture".

Signed-off-by: Aurelien Jarno <>

914ccf51 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: optimize register allocation order

The beginning of the register allocation order list on the TCG arm
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled....

c66b5c2c 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: don't try to load constants using pc

There is statistically almost 0 chances to use this code, so
remove it.

Signed-off-by: Aurelien Jarno <>

8f7f749f 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: sxtb and sxth are available starting with ARMv6

Signed-off-by: Aurelien Jarno <>

23401b58 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: use the blx instruction when possible

Signed-off-by: Aurelien Jarno <>

293579e5 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: add rotation ops

Signed-off-by: Aurelien Jarno <>

9517094f 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: add ext16u op

Add an ext16u op, either using the uxth instruction on ARMv6+ or two
shifts on previous ARM versions. In both cases the result use the same
number or less instructions than the pure TCG version.

Also move all sign extension code to separate functions, so that they...

244b1e81 04/19/2010 08:03 am Aurelien Jarno

tcg/arm: add bswap ops

Add an bswap16 and bswap32 ops, either using the rev and rev16
instructions on ARMv6+ or shifts and logical operations on previous
ARM versions. In both cases the result use less instructions than
the pure TCG version.

These ops are also needed by the qemu_ld/st functions....

39221a82 04/19/2010 08:02 am Aurelien Jarno

tcg/arm: remove SAVE_LR code

There is no need to save the LR register (r14) before a call to a
subroutine. According to the "Procedure Call Standard for the ARM
Architecture", it is the job of the callee to save this register.
Moreover, this register is already saved in the prologue/epilogue....

e4a7d5e8 04/19/2010 08:02 am Aurelien Jarno

tcg/arm: explicitely list clobbered/reserved regs

Instead of writing very compact code, declare all registers that are
clobbered or reserved one by one. This makes the code easier to read.

Also declare all the 16 registers to TCG, and mark pc as reserved....

f694a27e 04/19/2010 08:02 am Aurelien Jarno

tcg/arm: remove store signed functions

Store signed functions doesn't make sense, and are not used. Remove
them.

Signed-off-by: Aurelien Jarno <>

c8d80cef 04/19/2010 08:02 am Aurelien Jarno

tcg/arm: replace integer values by registers enum

The TCG ARM backends uses integer values to refer to both immediate
values and register number. This makes the code difficult to read.

The patch below replaces all (if I haven't miss any ;-) integer values...

ac34fb5c 04/19/2010 08:02 am Aurelien Jarno

tcg/arm: add variables to define the allowed instructions set

Use a set of variables to define the allowed ARM instructions, depending
on the ARM_ARCH_* GCC defines.

Signed-off-by: Aurelien Jarno <>

1584c845 03/28/2010 05:39 pm Stefan Weil

tcg/arm: Replace qemu_ld32u (left over from previous commit)

Commit 86feb1c860dc38e9c89e787c5210e8191800385e
did not change all occurrences of INDEX_op_qemu_ld32u
for tcg/arm.

Please note that I could not test this patch
(I have currently no arm system available)....

86feb1c8 03/27/2010 12:01 am Richard Henderson

tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.

Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand). For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with...

a9751609 03/26/2010 10:28 pm Richard Henderson

tcg: Name the opcode enumeration.

Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

9e97d8e9 03/20/2010 01:27 pm Aurelien Jarno

tcg/arm: don't save/restore r7 in prologue/epilogue

There is no need to save r7, it is used to store the address
of the env structure and is not modified by GCC.

Signed-off-by: Aurelien Jarno <>

26c5d372 03/20/2010 01:10 pm Aurelien Jarno

tcg/arm: fix load/store definitions for 32-bit targets

Signed-off-by: Aurelien Jarno <>

2b71cd72 03/14/2010 11:04 pm Aurelien Jarno

tcg/arm: use helpers for divu/remu

Signed-off-by: Aurelien Jarno <>

932234f6 03/13/2010 12:46 pm Aurelien Jarno

tcg/arm: implement andc op

Signed-off-by: Aurelien Jarno <>

4e17eae9 03/13/2010 12:44 pm Aurelien Jarno

tcg/arm: correctly save/restore registers in prologue/epilogue

Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crashes
on ARM hosts. This is not a bug of this commit, but a latent bug
revealed by this commit.

The TCG code is called through a procedure call using the prologue...

20cb400d 03/12/2010 08:34 pm Paul Brook

Remove TLB from userspace

Remove TLB from userspace CPU structure.

Signed-off-by: Paul Brook <>

023e77f8 03/02/2010 11:31 pm Aurelien Jarno

tcg/arm: accept immediate arguments for brcond/setcond

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Andrzej Zaborowski <>

b525f0a9 03/02/2010 11:26 pm Andrzej Zaborowski

Add a missing break

e0404769 03/02/2010 11:19 pm Aurelien Jarno

tcg/arm: implement setcond2

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Andrzej Zaborowski <>

f72a6cd7 03/02/2010 11:17 pm Aurelien Jarno

tcg/arm: implement setcond

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Andrzej Zaborowski <>

6b658613 03/02/2010 09:19 pm Aurelien Jarno

tcg/arm: fix div2/divu2

When restoring register values, increase the stack register for skipped
values.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Andrzej Zaborowski <>

7990496d 09/26/2009 10:29 pm Laurent Desnogues

ARM back-end: Use sxt[bh] instructions for ext{8, 6}s

This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Aurelien Jarno <>

d89c682f 09/25/2009 05:31 pm Stefan Weil

Suppress some variants of English in comments

Replace surpress, supress by suppress.

Signed-off-by: Stefan Weil <>
Signed-off-by: Aurelien Jarno <>

4e6f6d4c 08/25/2009 02:14 am Laurent Desnogues

ARM back-end: Fix encode_imm

the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>

94953e6d 08/22/2009 03:29 pm Laurent Desnogues

ARM back-end: Handle all possible immediates for ALU ops

this patch handles all possible constants for immediate operand of ALU ops.
I'm not very satisfied by the implementation.

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>

f878d2d2 08/22/2009 02:55 pm Laurent Desnogues

ARM back-end: Add TCG not

this patch:

- implements TCG not.

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>

e2542fe2 07/27/2009 10:09 pm Juan Quintela

rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>

cb4e581f 07/18/2009 03:20 pm Laurent Desnogues

this patch improves the ARM back-end in the following way:

- use movw/movt to load immediate values for ARMv7-A
- implement add/sub/and/or/xor with immediate (only 8-bit)

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>

379f6698 07/17/2009 03:12 pm Paul Brook

Userspace guest address offsetting

Re-implement GUEST_BASE support.
Offset guest ddress space by default if the guest binary contains
regions below the host mmap_min_addr.
Implement support for i386, x86-64 and arm hosts.

Signed-off-by: Riku Voipio <>...

2d69f359 07/17/2009 01:21 pm Paul Brook

ARM host fixes

Minor TCG cleanups and warning fixes for ARM hosts.

Signed-off-by: Paul Brook <>

419bafa5 03/10/2009 11:43 pm aurel32

tcg-arm: fix qemu_ld64

Emulating fldl on arm doesn't seem to work too well. It's the way
qemu_ld64 is translated to arm instructions.

tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);...
aef3a282 12/08/2008 01:35 am balrog

Fix 64-bit targets compilation on ARM host.

Only fix compilation, probably doesn't run.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5947 c046a42c-6fe2-441c-8c8c-71466251a162

0c9c3a9e 12/01/2008 01:57 pm balrog

arm: Don't potentially overwrite input registers in add2, sub2.

According to malc TCG will often genereate an add2/sub2/mul2 with low
half of the output in the same register as high half of one of the
inputs, so account for that.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162

fe33867b 12/01/2008 04:17 am balrog

Don't rely on ARM tcg_out_goto() generating just a single insn.

Otherwise when tb_exit generates a jump beyond the pc-relative range,
tcg_out_goto() spans two/three instructions and we load the tb return
value from a wrong address. This is #ifdefed out currently because...

d4a9eb1f 10/05/2008 12:59 pm blueswir1

Add some missing static and const qualifiers, reg_names only used if NDEBUG set

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162

79383c9c 08/30/2008 12:51 pm blueswir1

Fix some warnings that would be generated by gcc -Wredundant-decls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162

9b7b85d2 05/25/2008 03:36 am pbrook

Fix off-by-one unwinding error.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162

d0660ed4 05/25/2008 02:12 am balrog

Relax a constraint for qemu_ld64 on ARM host.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4567 c046a42c-6fe2-441c-8c8c-71466251a162

eae6ce52 05/25/2008 01:56 am balrog

Fix a deadly typo, correct comments.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4566 c046a42c-6fe2-441c-8c8c-71466251a162

3979144c 05/24/2008 11:07 pm pbrook

Fix ARM host TLB.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4564 c046a42c-6fe2-441c-8c8c-71466251a162

91a3c1b0 05/23/2008 09:51 pm balrog

Comment non-obvious calculation. Don't clobber r3 in qemu_st64.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4548 c046a42c-6fe2-441c-8c8c-71466251a162

e936243a 05/23/2008 09:50 pm balrog

A branch insn must not overwrite the branch target before relocation.

When a branch to label is translated it generates a reloc that is filled in
when the label is translated. However, when handling an exception and
searching for the pc we abort the translation early and we sometimes...

225b4376 05/23/2008 03:55 pm balrog

Fix qemu_ld/st for mem_index > 0 on arm host.

offsetof(CPUState, tlb_table[mem_index][0].addr_read) with mem_index > 0
was larger than max immediate offset for ldr and str (12-bit) so insert an
additional insn to add the mem_index offset.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4542 c046a42c-6fe2-441c-8c8c-71466251a162

204c1674 05/20/2008 02:28 pm balrog

Fix 8-bit signed load/store and a typo.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4504 c046a42c-6fe2-441c-8c8c-71466251a162

650bbb36 05/20/2008 02:26 pm balrog

Implement neg_i32, clean-up.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162

811d4cf4 05/20/2008 02:59 am balrog

ARM host support for TCG targets.

Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162