Revision 2507c12a hw/omap_sx1.c
| b/hw/omap_sx1.c | ||
|---|---|---|
| 143 | 143 |
qemu_ram_alloc(NULL, "omap_sx1.flash0-0", |
| 144 | 144 |
flash_size) | IO_MEM_ROM); |
| 145 | 145 |
|
| 146 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val); |
|
| 146 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val, |
|
| 147 |
DEVICE_NATIVE_ENDIAN); |
|
| 147 | 148 |
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, |
| 148 | 149 |
OMAP_CS0_SIZE - flash_size, io); |
| 149 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val); |
|
| 150 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val, |
|
| 151 |
DEVICE_NATIVE_ENDIAN); |
|
| 150 | 152 |
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); |
| 151 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val); |
|
| 153 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val, |
|
| 154 |
DEVICE_NATIVE_ENDIAN); |
|
| 152 | 155 |
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); |
| 153 | 156 |
|
| 154 | 157 |
fl_idx = 0; |
| ... | ... | |
| 175 | 178 |
cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size, |
| 176 | 179 |
qemu_ram_alloc(NULL, "omap_sx1.flash1-0", |
| 177 | 180 |
flash1_size) | IO_MEM_ROM); |
| 178 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val); |
|
| 181 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val, |
|
| 182 |
DEVICE_NATIVE_ENDIAN); |
|
| 179 | 183 |
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, |
| 180 | 184 |
OMAP_CS1_SIZE - flash1_size, io); |
| 181 | 185 |
|
| ... | ... | |
| 189 | 193 |
} |
| 190 | 194 |
fl_idx++; |
| 191 | 195 |
} else {
|
| 192 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val); |
|
| 196 |
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val, |
|
| 197 |
DEVICE_NATIVE_ENDIAN); |
|
| 193 | 198 |
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); |
| 194 | 199 |
} |
| 195 | 200 |
|
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