Revision 2507c12a hw/ppc405_uc.c
b/hw/ppc405_uc.c | ||
---|---|---|
383 | 383 |
#ifdef DEBUG_OPBA |
384 | 384 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
385 | 385 |
#endif |
386 |
io = cpu_register_io_memory(opba_read, opba_write, opba); |
|
386 |
io = cpu_register_io_memory(opba_read, opba_write, opba, |
|
387 |
DEVICE_NATIVE_ENDIAN); |
|
387 | 388 |
cpu_register_physical_memory(base, 0x002, io); |
388 | 389 |
qemu_register_reset(ppc4xx_opba_reset, opba); |
389 | 390 |
} |
... | ... | |
809 | 810 |
#ifdef DEBUG_GPIO |
810 | 811 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
811 | 812 |
#endif |
812 |
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio); |
|
813 |
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio, |
|
814 |
DEVICE_NATIVE_ENDIAN); |
|
813 | 815 |
cpu_register_physical_memory(base, 0x038, io); |
814 | 816 |
qemu_register_reset(&ppc405_gpio_reset, gpio); |
815 | 817 |
} |
... | ... | |
1218 | 1220 |
#ifdef DEBUG_I2C |
1219 | 1221 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
1220 | 1222 |
#endif |
1221 |
io = cpu_register_io_memory(i2c_read, i2c_write, i2c); |
|
1223 |
io = cpu_register_io_memory(i2c_read, i2c_write, i2c, |
|
1224 |
DEVICE_NATIVE_ENDIAN); |
|
1222 | 1225 |
cpu_register_physical_memory(base, 0x011, io); |
1223 | 1226 |
qemu_register_reset(ppc4xx_i2c_reset, i2c); |
1224 | 1227 |
} |
... | ... | |
1501 | 1504 |
#ifdef DEBUG_GPT |
1502 | 1505 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
1503 | 1506 |
#endif |
1504 |
io = cpu_register_io_memory(gpt_read, gpt_write, gpt); |
|
1507 |
io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
|
|
1505 | 1508 |
cpu_register_physical_memory(base, 0x0d4, io); |
1506 | 1509 |
qemu_register_reset(ppc4xx_gpt_reset, gpt); |
1507 | 1510 |
} |
Also available in: Unified diff