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/*
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* QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "sysbus.h" |
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#include "escc.h" |
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#include "qemu-char.h" |
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#include "console.h" |
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/* debug serial */
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//#define DEBUG_SERIAL
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/* debug keyboard */
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//#define DEBUG_KBD
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/* debug mouse */
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//#define DEBUG_MOUSE
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/*
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* Chipset docs:
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* "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual",
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* http://www.zilog.com/docs/serial/scc_escc_um.pdf
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*
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* On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001
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* (Slave I/O), also produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
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* mouse and keyboard ports don't implement all functions and they are
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* only asynchronous. There is no DMA.
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*
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* Z85C30 is also used on PowerMacs. There are some small differences
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* between Sparc version (sunzilog) and PowerMac (pmac):
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* Offset between control and data registers
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* There is some kind of lockup bug, but we can ignore it
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* CTS is inverted
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* DMA on pmac using DBDMA chip
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* pmac can do IRDA and faster rates, sunzilog can only do 38400
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* pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
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*/
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/*
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* Modifications:
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* 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
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* serial mouse queue.
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* Implemented serial mouse protocol.
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*
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* 2010-May-23 Artyom Tarasenko: Reworked IUS logic
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*/
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#ifdef DEBUG_SERIAL
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#define SER_DPRINTF(fmt, ...) \
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do { printf("SER: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define SER_DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_KBD
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#define KBD_DPRINTF(fmt, ...) \
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do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define KBD_DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_MOUSE
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#define MS_DPRINTF(fmt, ...) \
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do { printf("MSC: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define MS_DPRINTF(fmt, ...)
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#endif
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typedef enum { |
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chn_a, chn_b, |
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} ChnID; |
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#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a') |
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typedef enum { |
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ser, kbd, mouse, |
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} ChnType; |
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|
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#define SERIO_QUEUE_SIZE 256 |
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|
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typedef struct { |
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uint8_t data[SERIO_QUEUE_SIZE]; |
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int rptr, wptr, count;
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} SERIOQueue; |
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|
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#define SERIAL_REGS 16 |
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typedef struct ChannelState { |
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qemu_irq irq; |
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uint32_t reg; |
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uint32_t rxint, txint, rxint_under_svc, txint_under_svc; |
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ChnID chn; // this channel, A (base+4) or B (base+0)
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ChnType type; |
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struct ChannelState *otherchn;
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uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS]; |
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SERIOQueue queue; |
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CharDriverState *chr; |
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int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
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int disabled;
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int clock;
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uint32_t vmstate_dummy; |
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} ChannelState; |
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|
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struct SerialState {
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SysBusDevice busdev; |
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struct ChannelState chn[2]; |
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uint32_t it_shift; |
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int mmio_index;
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uint32_t disabled; |
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uint32_t frequency; |
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}; |
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|
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#define SERIAL_CTRL 0 |
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#define SERIAL_DATA 1 |
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|
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#define W_CMD 0 |
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#define CMD_PTR_MASK 0x07 |
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#define CMD_CMD_MASK 0x38 |
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#define CMD_HI 0x08 |
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#define CMD_CLR_TXINT 0x28 |
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#define CMD_CLR_IUS 0x38 |
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#define W_INTR 1 |
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#define INTR_INTALL 0x01 |
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#define INTR_TXINT 0x02 |
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#define INTR_RXMODEMSK 0x18 |
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#define INTR_RXINT1ST 0x08 |
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#define INTR_RXINTALL 0x10 |
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#define W_IVEC 2 |
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#define W_RXCTRL 3 |
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#define RXCTRL_RXEN 0x01 |
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#define W_TXCTRL1 4 |
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#define TXCTRL1_PAREN 0x01 |
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#define TXCTRL1_PAREV 0x02 |
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#define TXCTRL1_1STOP 0x04 |
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#define TXCTRL1_1HSTOP 0x08 |
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#define TXCTRL1_2STOP 0x0c |
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#define TXCTRL1_STPMSK 0x0c |
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#define TXCTRL1_CLK1X 0x00 |
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#define TXCTRL1_CLK16X 0x40 |
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#define TXCTRL1_CLK32X 0x80 |
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#define TXCTRL1_CLK64X 0xc0 |
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#define TXCTRL1_CLKMSK 0xc0 |
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#define W_TXCTRL2 5 |
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#define TXCTRL2_TXEN 0x08 |
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#define TXCTRL2_BITMSK 0x60 |
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#define TXCTRL2_5BITS 0x00 |
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#define TXCTRL2_7BITS 0x20 |
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#define TXCTRL2_6BITS 0x40 |
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#define TXCTRL2_8BITS 0x60 |
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#define W_SYNC1 6 |
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#define W_SYNC2 7 |
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#define W_TXBUF 8 |
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#define W_MINTR 9 |
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#define MINTR_STATUSHI 0x10 |
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#define MINTR_RST_MASK 0xc0 |
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#define MINTR_RST_B 0x40 |
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#define MINTR_RST_A 0x80 |
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#define MINTR_RST_ALL 0xc0 |
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#define W_MISC1 10 |
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#define W_CLOCK 11 |
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#define CLOCK_TRXC 0x08 |
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#define W_BRGLO 12 |
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#define W_BRGHI 13 |
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#define W_MISC2 14 |
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#define MISC2_PLLDIS 0x30 |
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#define W_EXTINT 15 |
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#define EXTINT_DCD 0x08 |
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#define EXTINT_SYNCINT 0x10 |
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#define EXTINT_CTSINT 0x20 |
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#define EXTINT_TXUNDRN 0x40 |
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#define EXTINT_BRKINT 0x80 |
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|
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#define R_STATUS 0 |
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#define STATUS_RXAV 0x01 |
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#define STATUS_ZERO 0x02 |
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#define STATUS_TXEMPTY 0x04 |
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#define STATUS_DCD 0x08 |
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#define STATUS_SYNC 0x10 |
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#define STATUS_CTS 0x20 |
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#define STATUS_TXUNDRN 0x40 |
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#define STATUS_BRK 0x80 |
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#define R_SPEC 1 |
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#define SPEC_ALLSENT 0x01 |
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#define SPEC_BITS8 0x06 |
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#define R_IVEC 2 |
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#define IVEC_TXINTB 0x00 |
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#define IVEC_LONOINT 0x06 |
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#define IVEC_LORXINTA 0x0c |
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#define IVEC_LORXINTB 0x04 |
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#define IVEC_LOTXINTA 0x08 |
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#define IVEC_HINOINT 0x60 |
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#define IVEC_HIRXINTA 0x30 |
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#define IVEC_HIRXINTB 0x20 |
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#define IVEC_HITXINTA 0x10 |
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#define R_INTR 3 |
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#define INTR_EXTINTB 0x01 |
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#define INTR_TXINTB 0x02 |
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#define INTR_RXINTB 0x04 |
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#define INTR_EXTINTA 0x08 |
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#define INTR_TXINTA 0x10 |
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#define INTR_RXINTA 0x20 |
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#define R_IPEN 4 |
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#define R_TXCTRL1 5 |
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#define R_TXCTRL2 6 |
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#define R_BC 7 |
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#define R_RXBUF 8 |
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#define R_RXCTRL 9 |
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#define R_MISC 10 |
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#define R_MISC1 11 |
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#define R_BRGLO 12 |
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#define R_BRGHI 13 |
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#define R_MISC1I 14 |
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#define R_EXTINT 15 |
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|
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static void handle_kbd_command(ChannelState *s, int val); |
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static int serial_can_receive(void *opaque); |
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static void serial_receive_byte(ChannelState *s, int ch); |
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static void clear_queue(void *opaque) |
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{ |
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ChannelState *s = opaque; |
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SERIOQueue *q = &s->queue; |
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q->rptr = q->wptr = q->count = 0;
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} |
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static void put_queue(void *opaque, int b) |
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{ |
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ChannelState *s = opaque; |
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SERIOQueue *q = &s->queue; |
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SER_DPRINTF("channel %c put: 0x%02x\n", CHN_C(s), b);
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if (q->count >= SERIO_QUEUE_SIZE)
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return;
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q->data[q->wptr] = b; |
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if (++q->wptr == SERIO_QUEUE_SIZE)
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q->wptr = 0;
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q->count++; |
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serial_receive_byte(s, 0);
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} |
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static uint32_t get_queue(void *opaque) |
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{ |
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ChannelState *s = opaque; |
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SERIOQueue *q = &s->queue; |
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int val;
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|
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if (q->count == 0) { |
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return 0; |
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} else {
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val = q->data[q->rptr]; |
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if (++q->rptr == SERIO_QUEUE_SIZE)
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q->rptr = 0;
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q->count--; |
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} |
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SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val);
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if (q->count > 0) |
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serial_receive_byte(s, 0);
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return val;
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} |
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static int escc_update_irq_chn(ChannelState *s) |
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{ |
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if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) || |
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// tx ints enabled, pending
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((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) || |
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((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) && |
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s->rxint == 1) || // rx ints enabled, pending |
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((s->wregs[W_EXTINT] & EXTINT_BRKINT) && |
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(s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p
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return 1; |
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} |
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return 0; |
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} |
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|
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static void escc_update_irq(ChannelState *s) |
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{ |
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int irq;
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irq = escc_update_irq_chn(s); |
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irq |= escc_update_irq_chn(s->otherchn); |
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|
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SER_DPRINTF("IRQ = %d\n", irq);
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qemu_set_irq(s->irq, irq); |
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} |
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|
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static void escc_reset_chn(ChannelState *s) |
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{ |
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int i;
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s->reg = 0;
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for (i = 0; i < SERIAL_REGS; i++) { |
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s->rregs[i] = 0;
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s->wregs[i] = 0;
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} |
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s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity
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s->wregs[W_MINTR] = MINTR_RST_ALL; |
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s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC
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s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled
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s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | |
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EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts
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if (s->disabled)
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s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | |
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STATUS_CTS | STATUS_TXUNDRN; |
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else
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s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN; |
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s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT; |
328 |
|
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s->rx = s->tx = 0;
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s->rxint = s->txint = 0;
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s->rxint_under_svc = s->txint_under_svc = 0;
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s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
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clear_queue(s); |
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} |
335 |
|
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static void escc_reset(DeviceState *d) |
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{ |
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SerialState *s = container_of(d, SerialState, busdev.qdev); |
339 |
|
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escc_reset_chn(&s->chn[0]);
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escc_reset_chn(&s->chn[1]);
|
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} |
343 |
|
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static inline void set_rxint(ChannelState *s) |
345 |
{ |
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s->rxint = 1;
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/* XXX: missing daisy chainnig: chn_b rx should have a lower priority
|
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than chn_a rx/tx/special_condition service*/
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s->rxint_under_svc = 1;
|
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if (s->chn == chn_a) {
|
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s->rregs[R_INTR] |= INTR_RXINTA; |
352 |
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
|
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s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA; |
354 |
else
|
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s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA; |
356 |
} else {
|
357 |
s->otherchn->rregs[R_INTR] |= INTR_RXINTB; |
358 |
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
|
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s->rregs[R_IVEC] = IVEC_HIRXINTB; |
360 |
else
|
361 |
s->rregs[R_IVEC] = IVEC_LORXINTB; |
362 |
} |
363 |
escc_update_irq(s); |
364 |
} |
365 |
|
366 |
static inline void set_txint(ChannelState *s) |
367 |
{ |
368 |
s->txint = 1;
|
369 |
if (!s->rxint_under_svc) {
|
370 |
s->txint_under_svc = 1;
|
371 |
if (s->chn == chn_a) {
|
372 |
s->rregs[R_INTR] |= INTR_TXINTA; |
373 |
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
|
374 |
s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA; |
375 |
else
|
376 |
s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA; |
377 |
} else {
|
378 |
s->rregs[R_IVEC] = IVEC_TXINTB; |
379 |
s->otherchn->rregs[R_INTR] |= INTR_TXINTB; |
380 |
} |
381 |
escc_update_irq(s); |
382 |
} |
383 |
} |
384 |
|
385 |
static inline void clr_rxint(ChannelState *s) |
386 |
{ |
387 |
s->rxint = 0;
|
388 |
s->rxint_under_svc = 0;
|
389 |
if (s->chn == chn_a) {
|
390 |
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
|
391 |
s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; |
392 |
else
|
393 |
s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; |
394 |
s->rregs[R_INTR] &= ~INTR_RXINTA; |
395 |
} else {
|
396 |
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
|
397 |
s->rregs[R_IVEC] = IVEC_HINOINT; |
398 |
else
|
399 |
s->rregs[R_IVEC] = IVEC_LONOINT; |
400 |
s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB; |
401 |
} |
402 |
if (s->txint)
|
403 |
set_txint(s); |
404 |
escc_update_irq(s); |
405 |
} |
406 |
|
407 |
static inline void clr_txint(ChannelState *s) |
408 |
{ |
409 |
s->txint = 0;
|
410 |
s->txint_under_svc = 0;
|
411 |
if (s->chn == chn_a) {
|
412 |
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
|
413 |
s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; |
414 |
else
|
415 |
s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; |
416 |
s->rregs[R_INTR] &= ~INTR_TXINTA; |
417 |
} else {
|
418 |
s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; |
419 |
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
|
420 |
s->rregs[R_IVEC] = IVEC_HINOINT; |
421 |
else
|
422 |
s->rregs[R_IVEC] = IVEC_LONOINT; |
423 |
s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; |
424 |
} |
425 |
if (s->rxint)
|
426 |
set_rxint(s); |
427 |
escc_update_irq(s); |
428 |
} |
429 |
|
430 |
static void escc_update_parameters(ChannelState *s) |
431 |
{ |
432 |
int speed, parity, data_bits, stop_bits;
|
433 |
QEMUSerialSetParams ssp; |
434 |
|
435 |
if (!s->chr || s->type != ser)
|
436 |
return;
|
437 |
|
438 |
if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {
|
439 |
if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV)
|
440 |
parity = 'E';
|
441 |
else
|
442 |
parity = 'O';
|
443 |
} else {
|
444 |
parity = 'N';
|
445 |
} |
446 |
if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP)
|
447 |
stop_bits = 2;
|
448 |
else
|
449 |
stop_bits = 1;
|
450 |
switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) {
|
451 |
case TXCTRL2_5BITS:
|
452 |
data_bits = 5;
|
453 |
break;
|
454 |
case TXCTRL2_7BITS:
|
455 |
data_bits = 7;
|
456 |
break;
|
457 |
case TXCTRL2_6BITS:
|
458 |
data_bits = 6;
|
459 |
break;
|
460 |
default:
|
461 |
case TXCTRL2_8BITS:
|
462 |
data_bits = 8;
|
463 |
break;
|
464 |
} |
465 |
speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2); |
466 |
switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) {
|
467 |
case TXCTRL1_CLK1X:
|
468 |
break;
|
469 |
case TXCTRL1_CLK16X:
|
470 |
speed /= 16;
|
471 |
break;
|
472 |
case TXCTRL1_CLK32X:
|
473 |
speed /= 32;
|
474 |
break;
|
475 |
default:
|
476 |
case TXCTRL1_CLK64X:
|
477 |
speed /= 64;
|
478 |
break;
|
479 |
} |
480 |
ssp.speed = speed; |
481 |
ssp.parity = parity; |
482 |
ssp.data_bits = data_bits; |
483 |
ssp.stop_bits = stop_bits; |
484 |
SER_DPRINTF("channel %c: speed=%d parity=%c data=%d stop=%d\n", CHN_C(s),
|
485 |
speed, parity, data_bits, stop_bits); |
486 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
487 |
} |
488 |
|
489 |
static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
490 |
{ |
491 |
SerialState *serial = opaque; |
492 |
ChannelState *s; |
493 |
uint32_t saddr; |
494 |
int newreg, channel;
|
495 |
|
496 |
val &= 0xff;
|
497 |
saddr = (addr >> serial->it_shift) & 1;
|
498 |
channel = (addr >> (serial->it_shift + 1)) & 1; |
499 |
s = &serial->chn[channel]; |
500 |
switch (saddr) {
|
501 |
case SERIAL_CTRL:
|
502 |
SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg,
|
503 |
val & 0xff);
|
504 |
newreg = 0;
|
505 |
switch (s->reg) {
|
506 |
case W_CMD:
|
507 |
newreg = val & CMD_PTR_MASK; |
508 |
val &= CMD_CMD_MASK; |
509 |
switch (val) {
|
510 |
case CMD_HI:
|
511 |
newreg |= CMD_HI; |
512 |
break;
|
513 |
case CMD_CLR_TXINT:
|
514 |
clr_txint(s); |
515 |
break;
|
516 |
case CMD_CLR_IUS:
|
517 |
if (s->rxint_under_svc) {
|
518 |
s->rxint_under_svc = 0;
|
519 |
if (s->txint) {
|
520 |
set_txint(s); |
521 |
} |
522 |
} else if (s->txint_under_svc) { |
523 |
s->txint_under_svc = 0;
|
524 |
} |
525 |
escc_update_irq(s); |
526 |
break;
|
527 |
default:
|
528 |
break;
|
529 |
} |
530 |
break;
|
531 |
case W_INTR ... W_RXCTRL:
|
532 |
case W_SYNC1 ... W_TXBUF:
|
533 |
case W_MISC1 ... W_CLOCK:
|
534 |
case W_MISC2 ... W_EXTINT:
|
535 |
s->wregs[s->reg] = val; |
536 |
break;
|
537 |
case W_TXCTRL1:
|
538 |
case W_TXCTRL2:
|
539 |
s->wregs[s->reg] = val; |
540 |
escc_update_parameters(s); |
541 |
break;
|
542 |
case W_BRGLO:
|
543 |
case W_BRGHI:
|
544 |
s->wregs[s->reg] = val; |
545 |
s->rregs[s->reg] = val; |
546 |
escc_update_parameters(s); |
547 |
break;
|
548 |
case W_MINTR:
|
549 |
switch (val & MINTR_RST_MASK) {
|
550 |
case 0: |
551 |
default:
|
552 |
break;
|
553 |
case MINTR_RST_B:
|
554 |
escc_reset_chn(&serial->chn[0]);
|
555 |
return;
|
556 |
case MINTR_RST_A:
|
557 |
escc_reset_chn(&serial->chn[1]);
|
558 |
return;
|
559 |
case MINTR_RST_ALL:
|
560 |
escc_reset(&serial->busdev.qdev); |
561 |
return;
|
562 |
} |
563 |
break;
|
564 |
default:
|
565 |
break;
|
566 |
} |
567 |
if (s->reg == 0) |
568 |
s->reg = newreg; |
569 |
else
|
570 |
s->reg = 0;
|
571 |
break;
|
572 |
case SERIAL_DATA:
|
573 |
SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
|
574 |
s->tx = val; |
575 |
if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled |
576 |
if (s->chr)
|
577 |
qemu_chr_write(s->chr, &s->tx, 1);
|
578 |
else if (s->type == kbd && !s->disabled) { |
579 |
handle_kbd_command(s, val); |
580 |
} |
581 |
} |
582 |
s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty
|
583 |
s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent
|
584 |
set_txint(s); |
585 |
break;
|
586 |
default:
|
587 |
break;
|
588 |
} |
589 |
} |
590 |
|
591 |
static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr) |
592 |
{ |
593 |
SerialState *serial = opaque; |
594 |
ChannelState *s; |
595 |
uint32_t saddr; |
596 |
uint32_t ret; |
597 |
int channel;
|
598 |
|
599 |
saddr = (addr >> serial->it_shift) & 1;
|
600 |
channel = (addr >> (serial->it_shift + 1)) & 1; |
601 |
s = &serial->chn[channel]; |
602 |
switch (saddr) {
|
603 |
case SERIAL_CTRL:
|
604 |
SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg,
|
605 |
s->rregs[s->reg]); |
606 |
ret = s->rregs[s->reg]; |
607 |
s->reg = 0;
|
608 |
return ret;
|
609 |
case SERIAL_DATA:
|
610 |
s->rregs[R_STATUS] &= ~STATUS_RXAV; |
611 |
clr_rxint(s); |
612 |
if (s->type == kbd || s->type == mouse)
|
613 |
ret = get_queue(s); |
614 |
else
|
615 |
ret = s->rx; |
616 |
SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
|
617 |
if (s->chr)
|
618 |
qemu_chr_accept_input(s->chr); |
619 |
return ret;
|
620 |
default:
|
621 |
break;
|
622 |
} |
623 |
return 0; |
624 |
} |
625 |
|
626 |
static int serial_can_receive(void *opaque) |
627 |
{ |
628 |
ChannelState *s = opaque; |
629 |
int ret;
|
630 |
|
631 |
if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled |
632 |
|| ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) |
633 |
// char already available
|
634 |
ret = 0;
|
635 |
else
|
636 |
ret = 1;
|
637 |
return ret;
|
638 |
} |
639 |
|
640 |
static void serial_receive_byte(ChannelState *s, int ch) |
641 |
{ |
642 |
SER_DPRINTF("channel %c put ch %d\n", CHN_C(s), ch);
|
643 |
s->rregs[R_STATUS] |= STATUS_RXAV; |
644 |
s->rx = ch; |
645 |
set_rxint(s); |
646 |
} |
647 |
|
648 |
static void serial_receive_break(ChannelState *s) |
649 |
{ |
650 |
s->rregs[R_STATUS] |= STATUS_BRK; |
651 |
escc_update_irq(s); |
652 |
} |
653 |
|
654 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
655 |
{ |
656 |
ChannelState *s = opaque; |
657 |
serial_receive_byte(s, buf[0]);
|
658 |
} |
659 |
|
660 |
static void serial_event(void *opaque, int event) |
661 |
{ |
662 |
ChannelState *s = opaque; |
663 |
if (event == CHR_EVENT_BREAK)
|
664 |
serial_receive_break(s); |
665 |
} |
666 |
|
667 |
static CPUReadMemoryFunc * const escc_mem_read[3] = { |
668 |
escc_mem_readb, |
669 |
NULL,
|
670 |
NULL,
|
671 |
}; |
672 |
|
673 |
static CPUWriteMemoryFunc * const escc_mem_write[3] = { |
674 |
escc_mem_writeb, |
675 |
NULL,
|
676 |
NULL,
|
677 |
}; |
678 |
|
679 |
static const VMStateDescription vmstate_escc_chn = { |
680 |
.name ="escc_chn",
|
681 |
.version_id = 2,
|
682 |
.minimum_version_id = 1,
|
683 |
.minimum_version_id_old = 1,
|
684 |
.fields = (VMStateField []) { |
685 |
VMSTATE_UINT32(vmstate_dummy, ChannelState), |
686 |
VMSTATE_UINT32(reg, ChannelState), |
687 |
VMSTATE_UINT32(rxint, ChannelState), |
688 |
VMSTATE_UINT32(txint, ChannelState), |
689 |
VMSTATE_UINT32(rxint_under_svc, ChannelState), |
690 |
VMSTATE_UINT32(txint_under_svc, ChannelState), |
691 |
VMSTATE_UINT8(rx, ChannelState), |
692 |
VMSTATE_UINT8(tx, ChannelState), |
693 |
VMSTATE_BUFFER(wregs, ChannelState), |
694 |
VMSTATE_BUFFER(rregs, ChannelState), |
695 |
VMSTATE_END_OF_LIST() |
696 |
} |
697 |
}; |
698 |
|
699 |
static const VMStateDescription vmstate_escc = { |
700 |
.name ="escc",
|
701 |
.version_id = 2,
|
702 |
.minimum_version_id = 1,
|
703 |
.minimum_version_id_old = 1,
|
704 |
.fields = (VMStateField []) { |
705 |
VMSTATE_STRUCT_ARRAY(chn, SerialState, 2, 2, vmstate_escc_chn, |
706 |
ChannelState), |
707 |
VMSTATE_END_OF_LIST() |
708 |
} |
709 |
}; |
710 |
|
711 |
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
|
712 |
CharDriverState *chrA, CharDriverState *chrB, |
713 |
int clock, int it_shift) |
714 |
{ |
715 |
DeviceState *dev; |
716 |
SysBusDevice *s; |
717 |
SerialState *d; |
718 |
|
719 |
dev = qdev_create(NULL, "escc"); |
720 |
qdev_prop_set_uint32(dev, "disabled", 0); |
721 |
qdev_prop_set_uint32(dev, "frequency", clock);
|
722 |
qdev_prop_set_uint32(dev, "it_shift", it_shift);
|
723 |
qdev_prop_set_chr(dev, "chrB", chrB);
|
724 |
qdev_prop_set_chr(dev, "chrA", chrA);
|
725 |
qdev_prop_set_uint32(dev, "chnBtype", ser);
|
726 |
qdev_prop_set_uint32(dev, "chnAtype", ser);
|
727 |
qdev_init_nofail(dev); |
728 |
s = sysbus_from_qdev(dev); |
729 |
sysbus_connect_irq(s, 0, irqB);
|
730 |
sysbus_connect_irq(s, 1, irqA);
|
731 |
if (base) {
|
732 |
sysbus_mmio_map(s, 0, base);
|
733 |
} |
734 |
|
735 |
d = FROM_SYSBUS(SerialState, s); |
736 |
return d->mmio_index;
|
737 |
} |
738 |
|
739 |
static const uint8_t keycodes[128] = { |
740 |
127, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 43, 53, |
741 |
54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 89, 76, 77, 78, |
742 |
79, 80, 81, 82, 83, 84, 85, 86, 87, 42, 99, 88, 100, 101, 102, 103, |
743 |
104, 105, 106, 107, 108, 109, 110, 47, 19, 121, 119, 5, 6, 8, 10, 12, |
744 |
14, 16, 17, 18, 7, 98, 23, 68, 69, 70, 71, 91, 92, 93, 125, 112, |
745 |
113, 114, 94, 50, 0, 0, 124, 9, 11, 0, 0, 0, 0, 0, 0, 0, |
746 |
90, 0, 46, 22, 13, 111, 52, 20, 96, 24, 28, 74, 27, 123, 44, 66, |
747 |
0, 45, 2, 4, 48, 0, 0, 21, 0, 0, 0, 0, 0, 120, 122, 67, |
748 |
}; |
749 |
|
750 |
static const uint8_t e0_keycodes[128] = { |
751 |
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
752 |
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 90, 76, 0, 0, |
753 |
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
754 |
0, 0, 0, 0, 0, 109, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, |
755 |
0, 0, 0, 0, 0, 0, 0, 68, 69, 70, 0, 91, 0, 93, 0, 112, |
756 |
113, 114, 94, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
757 |
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
758 |
1, 3, 25, 26, 49, 52, 72, 73, 97, 99, 111, 118, 120, 122, 67, 0, |
759 |
}; |
760 |
|
761 |
static void sunkbd_event(void *opaque, int ch) |
762 |
{ |
763 |
ChannelState *s = opaque; |
764 |
int release = ch & 0x80; |
765 |
|
766 |
KBD_DPRINTF("Untranslated keycode %2.2x (%s)\n", ch, release? "release" : |
767 |
"press");
|
768 |
switch (ch) {
|
769 |
case 58: // Caps lock press |
770 |
s->caps_lock_mode ^= 1;
|
771 |
if (s->caps_lock_mode == 2) |
772 |
return; // Drop second press |
773 |
break;
|
774 |
case 69: // Num lock press |
775 |
s->num_lock_mode ^= 1;
|
776 |
if (s->num_lock_mode == 2) |
777 |
return; // Drop second press |
778 |
break;
|
779 |
case 186: // Caps lock release |
780 |
s->caps_lock_mode ^= 2;
|
781 |
if (s->caps_lock_mode == 3) |
782 |
return; // Drop first release |
783 |
break;
|
784 |
case 197: // Num lock release |
785 |
s->num_lock_mode ^= 2;
|
786 |
if (s->num_lock_mode == 3) |
787 |
return; // Drop first release |
788 |
break;
|
789 |
case 0xe0: |
790 |
s->e0_mode = 1;
|
791 |
return;
|
792 |
default:
|
793 |
break;
|
794 |
} |
795 |
if (s->e0_mode) {
|
796 |
s->e0_mode = 0;
|
797 |
ch = e0_keycodes[ch & 0x7f];
|
798 |
} else {
|
799 |
ch = keycodes[ch & 0x7f];
|
800 |
} |
801 |
KBD_DPRINTF("Translated keycode %2.2x\n", ch);
|
802 |
put_queue(s, ch | release); |
803 |
} |
804 |
|
805 |
static void handle_kbd_command(ChannelState *s, int val) |
806 |
{ |
807 |
KBD_DPRINTF("Command %d\n", val);
|
808 |
if (s->led_mode) { // Ignore led byte |
809 |
s->led_mode = 0;
|
810 |
return;
|
811 |
} |
812 |
switch (val) {
|
813 |
case 1: // Reset, return type code |
814 |
clear_queue(s); |
815 |
put_queue(s, 0xff);
|
816 |
put_queue(s, 4); // Type 4 |
817 |
put_queue(s, 0x7f);
|
818 |
break;
|
819 |
case 0xe: // Set leds |
820 |
s->led_mode = 1;
|
821 |
break;
|
822 |
case 7: // Query layout |
823 |
case 0xf: |
824 |
clear_queue(s); |
825 |
put_queue(s, 0xfe);
|
826 |
put_queue(s, 0); // XXX, layout? |
827 |
break;
|
828 |
default:
|
829 |
break;
|
830 |
} |
831 |
} |
832 |
|
833 |
static void sunmouse_event(void *opaque, |
834 |
int dx, int dy, int dz, int buttons_state) |
835 |
{ |
836 |
ChannelState *s = opaque; |
837 |
int ch;
|
838 |
|
839 |
MS_DPRINTF("dx=%d dy=%d buttons=%01x\n", dx, dy, buttons_state);
|
840 |
|
841 |
ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */ |
842 |
|
843 |
if (buttons_state & MOUSE_EVENT_LBUTTON)
|
844 |
ch ^= 0x4;
|
845 |
if (buttons_state & MOUSE_EVENT_MBUTTON)
|
846 |
ch ^= 0x2;
|
847 |
if (buttons_state & MOUSE_EVENT_RBUTTON)
|
848 |
ch ^= 0x1;
|
849 |
|
850 |
put_queue(s, ch); |
851 |
|
852 |
ch = dx; |
853 |
|
854 |
if (ch > 127) |
855 |
ch = 127;
|
856 |
else if (ch < -127) |
857 |
ch = -127;
|
858 |
|
859 |
put_queue(s, ch & 0xff);
|
860 |
|
861 |
ch = -dy; |
862 |
|
863 |
if (ch > 127) |
864 |
ch = 127;
|
865 |
else if (ch < -127) |
866 |
ch = -127;
|
867 |
|
868 |
put_queue(s, ch & 0xff);
|
869 |
|
870 |
// MSC protocol specify two extra motion bytes
|
871 |
|
872 |
put_queue(s, 0);
|
873 |
put_queue(s, 0);
|
874 |
} |
875 |
|
876 |
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
|
877 |
int disabled, int clock, int it_shift) |
878 |
{ |
879 |
DeviceState *dev; |
880 |
SysBusDevice *s; |
881 |
|
882 |
dev = qdev_create(NULL, "escc"); |
883 |
qdev_prop_set_uint32(dev, "disabled", disabled);
|
884 |
qdev_prop_set_uint32(dev, "frequency", clock);
|
885 |
qdev_prop_set_uint32(dev, "it_shift", it_shift);
|
886 |
qdev_prop_set_chr(dev, "chrB", NULL); |
887 |
qdev_prop_set_chr(dev, "chrA", NULL); |
888 |
qdev_prop_set_uint32(dev, "chnBtype", mouse);
|
889 |
qdev_prop_set_uint32(dev, "chnAtype", kbd);
|
890 |
qdev_init_nofail(dev); |
891 |
s = sysbus_from_qdev(dev); |
892 |
sysbus_connect_irq(s, 0, irq);
|
893 |
sysbus_connect_irq(s, 1, irq);
|
894 |
sysbus_mmio_map(s, 0, base);
|
895 |
} |
896 |
|
897 |
static int escc_init1(SysBusDevice *dev) |
898 |
{ |
899 |
SerialState *s = FROM_SYSBUS(SerialState, dev); |
900 |
int io;
|
901 |
unsigned int i; |
902 |
|
903 |
s->chn[0].disabled = s->disabled;
|
904 |
s->chn[1].disabled = s->disabled;
|
905 |
for (i = 0; i < 2; i++) { |
906 |
sysbus_init_irq(dev, &s->chn[i].irq); |
907 |
s->chn[i].chn = 1 - i;
|
908 |
s->chn[i].clock = s->frequency / 2;
|
909 |
if (s->chn[i].chr) {
|
910 |
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, |
911 |
serial_receive1, serial_event, &s->chn[i]); |
912 |
} |
913 |
} |
914 |
s->chn[0].otherchn = &s->chn[1]; |
915 |
s->chn[1].otherchn = &s->chn[0]; |
916 |
|
917 |
io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s, |
918 |
DEVICE_NATIVE_ENDIAN); |
919 |
sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io); |
920 |
s->mmio_index = io; |
921 |
|
922 |
if (s->chn[0].type == mouse) { |
923 |
qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, |
924 |
"QEMU Sun Mouse");
|
925 |
} |
926 |
if (s->chn[1].type == kbd) { |
927 |
qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
|
928 |
} |
929 |
|
930 |
return 0; |
931 |
} |
932 |
|
933 |
static SysBusDeviceInfo escc_info = {
|
934 |
.init = escc_init1, |
935 |
.qdev.name = "escc",
|
936 |
.qdev.size = sizeof(SerialState),
|
937 |
.qdev.vmsd = &vmstate_escc, |
938 |
.qdev.reset = escc_reset, |
939 |
.qdev.props = (Property[]) { |
940 |
DEFINE_PROP_UINT32("frequency", SerialState, frequency, 0), |
941 |
DEFINE_PROP_UINT32("it_shift", SerialState, it_shift, 0), |
942 |
DEFINE_PROP_UINT32("disabled", SerialState, disabled, 0), |
943 |
DEFINE_PROP_UINT32("disabled", SerialState, disabled, 0), |
944 |
DEFINE_PROP_UINT32("chnBtype", SerialState, chn[0].type, 0), |
945 |
DEFINE_PROP_UINT32("chnAtype", SerialState, chn[1].type, 0), |
946 |
DEFINE_PROP_CHR("chrB", SerialState, chn[0].chr), |
947 |
DEFINE_PROP_CHR("chrA", SerialState, chn[1].chr), |
948 |
DEFINE_PROP_END_OF_LIST(), |
949 |
} |
950 |
}; |
951 |
|
952 |
static void escc_register_devices(void) |
953 |
{ |
954 |
sysbus_register_withprop(&escc_info); |
955 |
} |
956 |
|
957 |
device_init(escc_register_devices) |