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root / target-arm @ 2542bfd5

Name Size
cpu.h 17.8 kB
helper.c 90.8 kB
helper.h 17 kB
iwmmxt_helper.c 24.7 kB
machine.c 7.2 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 9.6 kB
translate.c 342.6 kB

Latest revisions

# Date Author Comment
7267c094 08/21/2011 07:01 am Anthony Liguori

Use glib memory allocation and free functions

qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <>
b9c6cbff 08/09/2011 08:16 pm Edgar E. Iglesias

Merge remote-tracking branch 'pm-arm/for-upstream' into pm
97b348e7 08/07/2011 12:32 pm Blue Swirl

Remove unused is_softmmu parameter from cpu_handle_mmu_fault

Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.

Acked-by: Richard Henderson <>...
3e457172 07/30/2011 12:41 pm Blue Swirl

exec.h cleanup

Move softmmu_exec.h include directives from target-*/exec.h to
target-*/op_helper.c. Move also various other stuff only used in
op_helper.c there.

Define global env in dyngen-exec.h.

For i386, move wrappers for segment and FPU helpers from user-exec.c...
7807eed9 07/26/2011 05:30 pm Jamie Iles

target-arm: support for ARM1176JZF-s cores

Add support for v6K ARM1176JZF-S. This core includes the VA<->PA
translation capability and security extensions.

Signed-off-by: Jamie Iles <>
Signed-off-by: Peter Maydell <>
906879a9 07/26/2011 05:30 pm Peter Maydell

target-arm: Mark 1136r1 as a v6K core

The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such,
thus enabling the TLS registers, NOP hints, CLREX, half and byte wide
exclusive load/stores, etc.

The VA-to-PA translation registers are not present on 1136r1, so...
87f19eb2 07/26/2011 05:30 pm Peter Maydell

target-arm: Support v6 barriers in linux-user mode

ARMv6 implemented various operations as special cases of cp15 accesses
which are true instructions in v7; this includes barriers (DMB, DSB, ISB).
Catch this special case at translate time, so that it works in linux-user...
934814f1 07/26/2011 05:30 pm Peter Maydell

target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM

Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. In
particular, we now generate an undef exception for overlarge imm8
values rather than generating 1000+ TCG ops and hitting an assertion....
6e0c0ed1 07/26/2011 05:30 pm Peter Maydell

target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assert

VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF.
This avoids a TCG assert later when the VCVTT/VCVTB code tries to
use a source register that wasn't ever set up.

We pull the check for the presence of the half-precision extension...
a492892c 07/26/2011 05:30 pm Peter Maydell

target-arm: Don't print debug messages for various UNDEF cases

Remove some stray printfs for cases which don't generally happen
(some VFP UNDEF cases, reads and writes to unknown cp14 registers);
we should simply generate an UNDEF when the instruction is executed....

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