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/*
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 *  PowerPC emulation for qemu: main translation routines.
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 * 
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 *  Copyright (c) 2003-2005 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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//#define DO_SINGLE_STEP
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//#define PPC_DEBUG_DISAS
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#ifdef USE_DIRECT_JUMP
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#define TBPARAM(x)
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#else
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#define TBPARAM(x) (long)(x)
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#endif
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enum {
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#define DEF(s, n, copy_size) INDEX_op_ ## s,
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#include "opc.h"
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#undef DEF
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    NB_OPS,
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};
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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#include "gen-op.h"
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#define GEN8(func, NAME) \
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static GenOpFunc *NAME ## _table [8] = {                                      \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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#define GEN16(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [16] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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#define GEN32(func, NAME) \
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static GenOpFunc *NAME ## _table [32] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
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};                                                                            \
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static inline void func(int n)                                                \
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{                                                                             \
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    NAME ## _table[n]();                                                      \
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}
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/* Condition register moves */
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GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
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GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
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GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
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GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
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/* Floating point condition and status register moves */
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GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
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GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
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GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
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static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
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    &gen_op_store_T0_fpscri_fpscr0,
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    &gen_op_store_T0_fpscri_fpscr1,
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    &gen_op_store_T0_fpscri_fpscr2,
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    &gen_op_store_T0_fpscri_fpscr3,
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    &gen_op_store_T0_fpscri_fpscr4,
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    &gen_op_store_T0_fpscri_fpscr5,
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    &gen_op_store_T0_fpscri_fpscr6,
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    &gen_op_store_T0_fpscri_fpscr7,
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};
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static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
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{
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    (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
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}
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/* Segment register moves */
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GEN16(gen_op_load_sr, gen_op_load_sr);
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GEN16(gen_op_store_sr, gen_op_store_sr);
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/* General purpose registers moves */
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GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
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GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
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GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
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GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
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GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
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GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
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/* floating point registers moves */
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GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
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GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
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GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
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GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
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GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
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GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
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static uint8_t  spr_access[1024 / 2];
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/* internal defines */
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typedef struct DisasContext {
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    struct TranslationBlock *tb;
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    target_ulong nip;
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    uint32_t opcode;
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    uint32_t exception;
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    /* Routine used to access memory */
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    int mem_idx;
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    /* Translation flags */
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#if !defined(CONFIG_USER_ONLY)
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    int supervisor;
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#endif
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    int fpu_enabled;
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    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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    int singlestep_enabled;
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} DisasContext;
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struct opc_handler_t {
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    /* invalid bits */
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    uint32_t inval;
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    /* instruction type */
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    uint32_t type;
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    /* handler */
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    void (*handler)(DisasContext *ctx);
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};
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#define RET_EXCP(ctx, excp, error)                                            \
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do {                                                                          \
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    if ((ctx)->exception == EXCP_NONE) {                                      \
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        gen_op_update_nip((ctx)->nip);                                        \
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    }                                                                         \
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    gen_op_raise_exception_err((excp), (error));                              \
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    ctx->exception = (excp);                                                  \
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} while (0)
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#define RET_INVAL(ctx)                                                        \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
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#define RET_PRIVOPC(ctx)                                                      \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
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#define RET_PRIVREG(ctx)                                                      \
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RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
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/* Stop translation */
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static inline void RET_STOP (DisasContext *ctx)
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{
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    gen_op_update_nip((ctx)->nip);
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    ctx->exception = EXCP_MTMSR;
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}
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/* No need to update nip here, as execution flow will change */
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static inline void RET_CHG_FLOW (DisasContext *ctx)
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{
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    ctx->exception = EXCP_MTMSR;
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}
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#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
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static void gen_##name (DisasContext *ctx);                                   \
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GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
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static void gen_##name (DisasContext *ctx)
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typedef struct opcode_t {
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    unsigned char opc1, opc2, opc3;
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#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
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    unsigned char pad[5];
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#else
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    unsigned char pad[1];
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#endif
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    opc_handler_t handler;
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    const unsigned char *oname;
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} opcode_t;
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/***                           Instruction decoding                        ***/
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#define EXTRACT_HELPER(name, shift, nb)                                       \
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static inline uint32_t name (uint32_t opcode)                                 \
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{                                                                             \
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    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
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}
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#define EXTRACT_SHELPER(name, shift, nb)                                      \
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static inline int32_t name (uint32_t opcode)                                  \
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{                                                                             \
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    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
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}
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/* Opcode part 1 */
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EXTRACT_HELPER(opc1, 26, 6);
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/* Opcode part 2 */
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EXTRACT_HELPER(opc2, 1, 5);
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/* Opcode part 3 */
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EXTRACT_HELPER(opc3, 6, 5);
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/* Update Cr0 flags */
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EXTRACT_HELPER(Rc, 0, 1);
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/* Destination */
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EXTRACT_HELPER(rD, 21, 5);
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/* Source */
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EXTRACT_HELPER(rS, 21, 5);
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/* First operand */
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EXTRACT_HELPER(rA, 16, 5);
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/* Second operand */
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EXTRACT_HELPER(rB, 11, 5);
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/* Third operand */
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EXTRACT_HELPER(rC, 6, 5);
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/***                               Get CRn                                 ***/
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EXTRACT_HELPER(crfD, 23, 3);
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EXTRACT_HELPER(crfS, 18, 3);
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EXTRACT_HELPER(crbD, 21, 5);
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EXTRACT_HELPER(crbA, 16, 5);
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EXTRACT_HELPER(crbB, 11, 5);
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/* SPR / TBL */
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EXTRACT_HELPER(_SPR, 11, 10);
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static inline uint32_t SPR (uint32_t opcode)
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{
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    uint32_t sprn = _SPR(opcode);
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    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
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}
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/***                              Get constants                            ***/
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EXTRACT_HELPER(IMM, 12, 8);
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/* 16 bits signed immediate value */
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EXTRACT_SHELPER(SIMM, 0, 16);
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/* 16 bits unsigned immediate value */
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EXTRACT_HELPER(UIMM, 0, 16);
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/* Bit count */
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EXTRACT_HELPER(NB, 11, 5);
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/* Shift count */
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EXTRACT_HELPER(SH, 11, 5);
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/* Mask start */
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EXTRACT_HELPER(MB, 6, 5);
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/* Mask end */
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EXTRACT_HELPER(ME, 1, 5);
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/* Trap operand */
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EXTRACT_HELPER(TO, 21, 5);
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EXTRACT_HELPER(CRM, 12, 8);
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EXTRACT_HELPER(FM, 17, 8);
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EXTRACT_HELPER(SR, 16, 4);
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EXTRACT_HELPER(FPIMM, 20, 4);
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/***                            Jump target decoding                       ***/
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/* Displacement */
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EXTRACT_SHELPER(d, 0, 16);
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/* Immediate address */
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static inline uint32_t LI (uint32_t opcode)
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{
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    return (opcode >> 0) & 0x03FFFFFC;
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}
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static inline uint32_t BD (uint32_t opcode)
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{
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    return (opcode >> 0) & 0xFFFC;
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}
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EXTRACT_HELPER(BO, 21, 5);
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EXTRACT_HELPER(BI, 16, 5);
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/* Absolute/relative address */
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EXTRACT_HELPER(AA, 1, 1);
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/* Link */
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EXTRACT_HELPER(LK, 0, 1);
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/* Create a mask between <start> and <end> bits */
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static inline uint32_t MASK (uint32_t start, uint32_t end)
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{
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    uint32_t ret;
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    ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
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    if (start > end)
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        return ~ret;
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    return ret;
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}
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#if HOST_LONG_BITS == 64
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#define OPC_ALIGN 8
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#else
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#define OPC_ALIGN 4
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#endif
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#if defined(__APPLE__)
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#define OPCODES_SECTION \
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    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
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#else
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#define OPCODES_SECTION \
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    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
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#endif
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#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
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OPCODES_SECTION opcode_t opc_##name = {                                       \
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    .opc1 = op1,                                                              \
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    .opc2 = op2,                                                              \
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    .opc3 = op3,                                                              \
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    .pad  = { 0, },                                                           \
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    .handler = {                                                              \
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        .inval   = invl,                                                      \
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        .type = _typ,                                                         \
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        .handler = &gen_##name,                                               \
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    },                                                                        \
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    .oname = stringify(name),                                                 \
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}
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#define GEN_OPCODE_MARK(name)                                                 \
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OPCODES_SECTION opcode_t opc_##name = {                                       \
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    .opc1 = 0xFF,                                                             \
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    .opc2 = 0xFF,                                                             \
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    .opc3 = 0xFF,                                                             \
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    .pad  = { 0, },                                                           \
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    .handler = {                                                              \
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        .inval   = 0x00000000,                                                \
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        .type = 0x00,                                                         \
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        .handler = NULL,                                                      \
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    },                                                                        \
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    .oname = stringify(name),                                                 \
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}
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/* Start opcode list */
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GEN_OPCODE_MARK(start);
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/* Invalid instruction */
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GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
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{
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    RET_INVAL(ctx);
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}
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static opc_handler_t invalid_handler = {
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    .inval   = 0xFFFFFFFF,
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    .type    = PPC_NONE,
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    .handler = gen_invalid,
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};
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/***                           Integer arithmetic                          ***/
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#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval)                       \
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GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \
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{                                                                             \
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    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
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    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
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    gen_op_##name();                                                          \
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    if (Rc(ctx->opcode) != 0)                                                 \
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        gen_op_set_Rc0();                                                     \
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    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
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}
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#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval)                     \
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GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \
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{                                                                             \
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    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
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    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
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    gen_op_##name();                                                          \
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    if (Rc(ctx->opcode) != 0)                                                 \
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        gen_op_set_Rc0();                                                     \
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    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
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}
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#define __GEN_INT_ARITH1(name, opc1, opc2, opc3)                              \
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GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \
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{                                                                             \
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    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
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    gen_op_##name();                                                          \
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    if (Rc(ctx->opcode) != 0)                                                 \
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        gen_op_set_Rc0();                                                     \
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    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
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}
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#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3)                            \
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GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \
400 79aceca5 bellard
{                                                                             \
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    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
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    gen_op_##name();                                                          \
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    if (Rc(ctx->opcode) != 0)                                                 \
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        gen_op_set_Rc0();                                                     \
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    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
406 79aceca5 bellard
}
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/* Two operands arithmetic functions */
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#define GEN_INT_ARITH2(name, opc1, opc2, opc3)                                \
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__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000)                          \
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__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
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/* Two operands arithmetic functions with no overflow allowed */
414 79aceca5 bellard
#define GEN_INT_ARITHN(name, opc1, opc2, opc3)                                \
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__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
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/* One operand arithmetic functions */
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#define GEN_INT_ARITH1(name, opc1, opc2, opc3)                                \
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__GEN_INT_ARITH1(name, opc1, opc2, opc3)                                      \
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__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
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/* add    add.    addo    addo.    */
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GEN_INT_ARITH2 (add,    0x1F, 0x0A, 0x08);
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/* addc   addc.   addco   addco.   */
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GEN_INT_ARITH2 (addc,   0x1F, 0x0A, 0x00);
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/* adde   adde.   addeo   addeo.   */
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GEN_INT_ARITH2 (adde,   0x1F, 0x0A, 0x04);
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/* addme  addme.  addmeo  addmeo.  */
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GEN_INT_ARITH1 (addme,  0x1F, 0x0A, 0x07);
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/* addze  addze.  addzeo  addzeo.  */
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GEN_INT_ARITH1 (addze,  0x1F, 0x0A, 0x06);
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/* divw   divw.   divwo   divwo.   */
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GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F);
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/* divwu  divwu.  divwuo  divwuo.  */
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GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E);
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/* mulhw  mulhw.                   */
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GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02);
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/* mulhwu mulhwu.                  */
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GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
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/* mullw  mullw.  mullwo  mullwo.  */
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GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07);
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/* neg    neg.    nego    nego.    */
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GEN_INT_ARITH1 (neg,    0x1F, 0x08, 0x03);
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/* subf   subf.   subfo   subfo.   */
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GEN_INT_ARITH2 (subf,   0x1F, 0x08, 0x01);
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/* subfc  subfc.  subfco  subfco.  */
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GEN_INT_ARITH2 (subfc,  0x1F, 0x08, 0x00);
448 79aceca5 bellard
/* subfe  subfe.  subfeo  subfeo.  */
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GEN_INT_ARITH2 (subfe,  0x1F, 0x08, 0x04);
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/* subfme subfme. subfmeo subfmeo. */
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GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
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/* subfze subfze. subfzeo subfzeo. */
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GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
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/* addi */
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GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
456 79aceca5 bellard
{
457 79aceca5 bellard
    int32_t simm = SIMM(ctx->opcode);
458 79aceca5 bellard
459 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
460 79aceca5 bellard
        gen_op_set_T0(simm);
461 79aceca5 bellard
    } else {
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        gen_op_load_gpr_T0(rA(ctx->opcode));
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        gen_op_addi(simm);
464 79aceca5 bellard
    }
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    gen_op_store_T0_gpr(rD(ctx->opcode));
466 79aceca5 bellard
}
467 79aceca5 bellard
/* addic */
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GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
469 79aceca5 bellard
{
470 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
471 79aceca5 bellard
    gen_op_addic(SIMM(ctx->opcode));
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    gen_op_store_T0_gpr(rD(ctx->opcode));
473 79aceca5 bellard
}
474 79aceca5 bellard
/* addic. */
475 79aceca5 bellard
GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
476 79aceca5 bellard
{
477 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
478 79aceca5 bellard
    gen_op_addic(SIMM(ctx->opcode));
479 79aceca5 bellard
    gen_op_set_Rc0();
480 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
481 79aceca5 bellard
}
482 79aceca5 bellard
/* addis */
483 79aceca5 bellard
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
484 79aceca5 bellard
{
485 79aceca5 bellard
    int32_t simm = SIMM(ctx->opcode);
486 79aceca5 bellard
487 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
488 79aceca5 bellard
        gen_op_set_T0(simm << 16);
489 79aceca5 bellard
    } else {
490 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
491 79aceca5 bellard
        gen_op_addi(simm << 16);
492 79aceca5 bellard
    }
493 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
494 79aceca5 bellard
}
495 79aceca5 bellard
/* mulli */
496 79aceca5 bellard
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
497 79aceca5 bellard
{
498 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
499 79aceca5 bellard
    gen_op_mulli(SIMM(ctx->opcode));
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    gen_op_store_T0_gpr(rD(ctx->opcode));
501 79aceca5 bellard
}
502 79aceca5 bellard
/* subfic */
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GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
504 79aceca5 bellard
{
505 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
506 79aceca5 bellard
    gen_op_subfic(SIMM(ctx->opcode));
507 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
508 79aceca5 bellard
}
509 79aceca5 bellard
510 79aceca5 bellard
/***                           Integer comparison                          ***/
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#define GEN_CMP(name, opc)                                                    \
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GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER)                   \
513 79aceca5 bellard
{                                                                             \
514 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
515 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
516 79aceca5 bellard
    gen_op_##name();                                                          \
517 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
518 79aceca5 bellard
}
519 79aceca5 bellard
520 79aceca5 bellard
/* cmp */
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GEN_CMP(cmp, 0x00);
522 79aceca5 bellard
/* cmpi */
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GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
524 79aceca5 bellard
{
525 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
526 79aceca5 bellard
    gen_op_cmpi(SIMM(ctx->opcode));
527 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
528 79aceca5 bellard
}
529 79aceca5 bellard
/* cmpl */
530 79aceca5 bellard
GEN_CMP(cmpl, 0x01);
531 79aceca5 bellard
/* cmpli */
532 79aceca5 bellard
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
533 79aceca5 bellard
{
534 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
535 79aceca5 bellard
    gen_op_cmpli(UIMM(ctx->opcode));
536 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
537 79aceca5 bellard
}
538 79aceca5 bellard
539 79aceca5 bellard
/***                            Integer logical                            ***/
540 79aceca5 bellard
#define __GEN_LOGICAL2(name, opc2, opc3)                                      \
541 79aceca5 bellard
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER)                  \
542 79aceca5 bellard
{                                                                             \
543 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
544 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
545 79aceca5 bellard
    gen_op_##name();                                                          \
546 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
547 79aceca5 bellard
        gen_op_set_Rc0();                                                     \
548 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
549 79aceca5 bellard
}
550 79aceca5 bellard
#define GEN_LOGICAL2(name, opc)                                               \
551 79aceca5 bellard
__GEN_LOGICAL2(name, 0x1C, opc)
552 79aceca5 bellard
553 79aceca5 bellard
#define GEN_LOGICAL1(name, opc)                                               \
554 79aceca5 bellard
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER)                   \
555 79aceca5 bellard
{                                                                             \
556 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
557 79aceca5 bellard
    gen_op_##name();                                                          \
558 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)                                                 \
559 79aceca5 bellard
        gen_op_set_Rc0();                                                     \
560 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
561 79aceca5 bellard
}
562 79aceca5 bellard
563 79aceca5 bellard
/* and & and. */
564 79aceca5 bellard
GEN_LOGICAL2(and, 0x00);
565 79aceca5 bellard
/* andc & andc. */
566 79aceca5 bellard
GEN_LOGICAL2(andc, 0x01);
567 79aceca5 bellard
/* andi. */
568 79aceca5 bellard
GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
569 79aceca5 bellard
{
570 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
571 79aceca5 bellard
    gen_op_andi_(UIMM(ctx->opcode));
572 79aceca5 bellard
    gen_op_set_Rc0();
573 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
574 79aceca5 bellard
}
575 79aceca5 bellard
/* andis. */
576 79aceca5 bellard
GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
577 79aceca5 bellard
{
578 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
579 79aceca5 bellard
    gen_op_andi_(UIMM(ctx->opcode) << 16);
580 79aceca5 bellard
    gen_op_set_Rc0();
581 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
582 79aceca5 bellard
}
583 79aceca5 bellard
584 79aceca5 bellard
/* cntlzw */
585 79aceca5 bellard
GEN_LOGICAL1(cntlzw, 0x00);
586 79aceca5 bellard
/* eqv & eqv. */
587 79aceca5 bellard
GEN_LOGICAL2(eqv, 0x08);
588 79aceca5 bellard
/* extsb & extsb. */
589 79aceca5 bellard
GEN_LOGICAL1(extsb, 0x1D);
590 79aceca5 bellard
/* extsh & extsh. */
591 79aceca5 bellard
GEN_LOGICAL1(extsh, 0x1C);
592 79aceca5 bellard
/* nand & nand. */
593 79aceca5 bellard
GEN_LOGICAL2(nand, 0x0E);
594 79aceca5 bellard
/* nor & nor. */
595 79aceca5 bellard
GEN_LOGICAL2(nor, 0x03);
596 9a64fbe4 bellard
597 79aceca5 bellard
/* or & or. */
598 9a64fbe4 bellard
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
599 9a64fbe4 bellard
{
600 9a64fbe4 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
601 9a64fbe4 bellard
    /* Optimisation for mr case */
602 9a64fbe4 bellard
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
603 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
604 9a64fbe4 bellard
        gen_op_or();
605 9a64fbe4 bellard
    }
606 9a64fbe4 bellard
    if (Rc(ctx->opcode) != 0)
607 9a64fbe4 bellard
        gen_op_set_Rc0();
608 9a64fbe4 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
609 9a64fbe4 bellard
}
610 9a64fbe4 bellard
611 79aceca5 bellard
/* orc & orc. */
612 79aceca5 bellard
GEN_LOGICAL2(orc, 0x0C);
613 79aceca5 bellard
/* xor & xor. */
614 9a64fbe4 bellard
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
615 9a64fbe4 bellard
{
616 9a64fbe4 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
617 9a64fbe4 bellard
    /* Optimisation for "set to zero" case */
618 9a64fbe4 bellard
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
619 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
620 9a64fbe4 bellard
        gen_op_xor();
621 9a64fbe4 bellard
    } else {
622 9a64fbe4 bellard
        gen_op_set_T0(0);
623 9a64fbe4 bellard
    }
624 9a64fbe4 bellard
    if (Rc(ctx->opcode) != 0)
625 9a64fbe4 bellard
        gen_op_set_Rc0();
626 9a64fbe4 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
627 9a64fbe4 bellard
}
628 79aceca5 bellard
/* ori */
629 79aceca5 bellard
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
630 79aceca5 bellard
{
631 79aceca5 bellard
    uint32_t uimm = UIMM(ctx->opcode);
632 79aceca5 bellard
633 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
634 9a64fbe4 bellard
        /* NOP */
635 9a64fbe4 bellard
        return;
636 79aceca5 bellard
        }
637 79aceca5 bellard
        gen_op_load_gpr_T0(rS(ctx->opcode));
638 9a64fbe4 bellard
    if (uimm != 0)
639 79aceca5 bellard
        gen_op_ori(uimm);
640 79aceca5 bellard
        gen_op_store_T0_gpr(rA(ctx->opcode));
641 79aceca5 bellard
}
642 79aceca5 bellard
/* oris */
643 79aceca5 bellard
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
644 79aceca5 bellard
{
645 79aceca5 bellard
    uint32_t uimm = UIMM(ctx->opcode);
646 79aceca5 bellard
647 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
648 9a64fbe4 bellard
        /* NOP */
649 9a64fbe4 bellard
        return;
650 79aceca5 bellard
        }
651 79aceca5 bellard
        gen_op_load_gpr_T0(rS(ctx->opcode));
652 9a64fbe4 bellard
    if (uimm != 0)
653 79aceca5 bellard
        gen_op_ori(uimm << 16);
654 79aceca5 bellard
        gen_op_store_T0_gpr(rA(ctx->opcode));
655 79aceca5 bellard
}
656 79aceca5 bellard
/* xori */
657 79aceca5 bellard
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
658 79aceca5 bellard
{
659 9a64fbe4 bellard
    uint32_t uimm = UIMM(ctx->opcode);
660 9a64fbe4 bellard
661 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
662 9a64fbe4 bellard
        /* NOP */
663 9a64fbe4 bellard
        return;
664 9a64fbe4 bellard
    }
665 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
666 9a64fbe4 bellard
    if (uimm != 0)
667 4b3686fa bellard
    gen_op_xori(uimm);
668 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
669 79aceca5 bellard
}
670 79aceca5 bellard
671 79aceca5 bellard
/* xoris */
672 79aceca5 bellard
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
673 79aceca5 bellard
{
674 9a64fbe4 bellard
    uint32_t uimm = UIMM(ctx->opcode);
675 9a64fbe4 bellard
676 9a64fbe4 bellard
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
677 9a64fbe4 bellard
        /* NOP */
678 9a64fbe4 bellard
        return;
679 9a64fbe4 bellard
    }
680 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
681 9a64fbe4 bellard
    if (uimm != 0)
682 4b3686fa bellard
    gen_op_xori(uimm << 16);
683 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
684 79aceca5 bellard
}
685 79aceca5 bellard
686 79aceca5 bellard
/***                             Integer rotate                            ***/
687 79aceca5 bellard
/* rlwimi & rlwimi. */
688 79aceca5 bellard
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
689 79aceca5 bellard
{
690 79aceca5 bellard
    uint32_t mb, me;
691 79aceca5 bellard
692 79aceca5 bellard
    mb = MB(ctx->opcode);
693 79aceca5 bellard
    me = ME(ctx->opcode);
694 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
695 fb0eaffc bellard
    gen_op_load_gpr_T1(rA(ctx->opcode));
696 79aceca5 bellard
    gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
697 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
698 79aceca5 bellard
        gen_op_set_Rc0();
699 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
700 79aceca5 bellard
}
701 79aceca5 bellard
/* rlwinm & rlwinm. */
702 79aceca5 bellard
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
703 79aceca5 bellard
{
704 79aceca5 bellard
    uint32_t mb, me, sh;
705 79aceca5 bellard
    
706 79aceca5 bellard
    sh = SH(ctx->opcode);
707 79aceca5 bellard
    mb = MB(ctx->opcode);
708 79aceca5 bellard
    me = ME(ctx->opcode);
709 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
710 4b3686fa bellard
#if 1 // TRY
711 4b3686fa bellard
    if (sh == 0) {
712 4b3686fa bellard
        gen_op_andi_(MASK(mb, me));
713 4b3686fa bellard
        goto store;
714 4b3686fa bellard
    }
715 4b3686fa bellard
#endif
716 79aceca5 bellard
    if (mb == 0) {
717 79aceca5 bellard
        if (me == 31) {
718 79aceca5 bellard
            gen_op_rotlwi(sh);
719 79aceca5 bellard
            goto store;
720 4b3686fa bellard
#if 0
721 79aceca5 bellard
        } else if (me == (31 - sh)) {
722 79aceca5 bellard
            gen_op_slwi(sh);
723 79aceca5 bellard
            goto store;
724 4b3686fa bellard
#endif
725 79aceca5 bellard
        }
726 79aceca5 bellard
    } else if (me == 31) {
727 4b3686fa bellard
#if 0
728 79aceca5 bellard
        if (sh == (32 - mb)) {
729 79aceca5 bellard
            gen_op_srwi(mb);
730 79aceca5 bellard
            goto store;
731 79aceca5 bellard
        }
732 4b3686fa bellard
#endif
733 79aceca5 bellard
    }
734 79aceca5 bellard
    gen_op_rlwinm(sh, MASK(mb, me));
735 79aceca5 bellard
store:
736 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
737 79aceca5 bellard
        gen_op_set_Rc0();
738 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
739 79aceca5 bellard
}
740 79aceca5 bellard
/* rlwnm & rlwnm. */
741 79aceca5 bellard
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
742 79aceca5 bellard
{
743 79aceca5 bellard
    uint32_t mb, me;
744 79aceca5 bellard
745 79aceca5 bellard
    mb = MB(ctx->opcode);
746 79aceca5 bellard
    me = ME(ctx->opcode);
747 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
748 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));
749 79aceca5 bellard
    if (mb == 0 && me == 31) {
750 79aceca5 bellard
        gen_op_rotl();
751 79aceca5 bellard
    } else
752 79aceca5 bellard
    {
753 79aceca5 bellard
        gen_op_rlwnm(MASK(mb, me));
754 79aceca5 bellard
    }
755 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
756 79aceca5 bellard
        gen_op_set_Rc0();
757 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
758 79aceca5 bellard
}
759 79aceca5 bellard
760 79aceca5 bellard
/***                             Integer shift                             ***/
761 79aceca5 bellard
/* slw & slw. */
762 79aceca5 bellard
__GEN_LOGICAL2(slw, 0x18, 0x00);
763 79aceca5 bellard
/* sraw & sraw. */
764 79aceca5 bellard
__GEN_LOGICAL2(sraw, 0x18, 0x18);
765 79aceca5 bellard
/* srawi & srawi. */
766 79aceca5 bellard
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
767 79aceca5 bellard
{
768 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
769 4ecc3190 bellard
    if (SH(ctx->opcode) != 0)
770 79aceca5 bellard
    gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
771 79aceca5 bellard
    if (Rc(ctx->opcode) != 0)
772 79aceca5 bellard
        gen_op_set_Rc0();
773 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));
774 79aceca5 bellard
}
775 79aceca5 bellard
/* srw & srw. */
776 79aceca5 bellard
__GEN_LOGICAL2(srw, 0x18, 0x10);
777 79aceca5 bellard
778 79aceca5 bellard
/***                       Floating-Point arithmetic                       ***/
779 4ecc3190 bellard
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat)                           \
780 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT)                   \
781 9a64fbe4 bellard
{                                                                             \
782 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
783 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
784 3cc62370 bellard
        return;                                                               \
785 3cc62370 bellard
    }                                                                         \
786 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
787 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
788 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
789 9a64fbe4 bellard
    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
790 4ecc3190 bellard
    gen_op_f##op();                                                           \
791 4ecc3190 bellard
    if (isfloat) {                                                            \
792 4ecc3190 bellard
        gen_op_frsp();                                                        \
793 4ecc3190 bellard
    }                                                                         \
794 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
795 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
796 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
797 9a64fbe4 bellard
}
798 9a64fbe4 bellard
799 9a64fbe4 bellard
#define GEN_FLOAT_ACB(name, op2)                                              \
800 4ecc3190 bellard
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0);                                     \
801 4ecc3190 bellard
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
802 9a64fbe4 bellard
803 4ecc3190 bellard
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat)                     \
804 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
805 9a64fbe4 bellard
{                                                                             \
806 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
807 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
808 3cc62370 bellard
        return;                                                               \
809 3cc62370 bellard
    }                                                                         \
810 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
811 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
812 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
813 4ecc3190 bellard
    gen_op_f##op();                                                           \
814 4ecc3190 bellard
    if (isfloat) {                                                            \
815 4ecc3190 bellard
        gen_op_frsp();                                                        \
816 4ecc3190 bellard
    }                                                                         \
817 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
818 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
819 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
820 9a64fbe4 bellard
}
821 9a64fbe4 bellard
#define GEN_FLOAT_AB(name, op2, inval)                                        \
822 4ecc3190 bellard
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0);                               \
823 4ecc3190 bellard
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
824 9a64fbe4 bellard
825 4ecc3190 bellard
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat)                     \
826 9a64fbe4 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
827 9a64fbe4 bellard
{                                                                             \
828 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
829 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
830 3cc62370 bellard
        return;                                                               \
831 3cc62370 bellard
    }                                                                         \
832 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
833 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
834 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
835 4ecc3190 bellard
    gen_op_f##op();                                                           \
836 4ecc3190 bellard
    if (isfloat) {                                                            \
837 4ecc3190 bellard
        gen_op_frsp();                                                        \
838 4ecc3190 bellard
    }                                                                         \
839 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
840 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
841 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
842 9a64fbe4 bellard
}
843 9a64fbe4 bellard
#define GEN_FLOAT_AC(name, op2, inval)                                        \
844 4ecc3190 bellard
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0);                               \
845 4ecc3190 bellard
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
846 9a64fbe4 bellard
847 9a64fbe4 bellard
#define GEN_FLOAT_B(name, op2, op3)                                           \
848 9a64fbe4 bellard
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT)                   \
849 9a64fbe4 bellard
{                                                                             \
850 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
851 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
852 3cc62370 bellard
        return;                                                               \
853 3cc62370 bellard
    }                                                                         \
854 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
855 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
856 9a64fbe4 bellard
    gen_op_f##name();                                                         \
857 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
858 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
859 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
860 79aceca5 bellard
}
861 79aceca5 bellard
862 4ecc3190 bellard
#define GEN_FLOAT_BS(name, op1, op2)                                          \
863 4ecc3190 bellard
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT)                   \
864 9a64fbe4 bellard
{                                                                             \
865 3cc62370 bellard
    if (!ctx->fpu_enabled) {                                                  \
866 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
867 3cc62370 bellard
        return;                                                               \
868 3cc62370 bellard
    }                                                                         \
869 9a64fbe4 bellard
    gen_op_reset_scrfx();                                                     \
870 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
871 9a64fbe4 bellard
    gen_op_f##name();                                                         \
872 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
873 9a64fbe4 bellard
    if (Rc(ctx->opcode))                                                      \
874 9a64fbe4 bellard
        gen_op_set_Rc1();                                                     \
875 79aceca5 bellard
}
876 79aceca5 bellard
877 9a64fbe4 bellard
/* fadd - fadds */
878 9a64fbe4 bellard
GEN_FLOAT_AB(add, 0x15, 0x000007C0);
879 4ecc3190 bellard
/* fdiv - fdivs */
880 9a64fbe4 bellard
GEN_FLOAT_AB(div, 0x12, 0x000007C0);
881 4ecc3190 bellard
/* fmul - fmuls */
882 9a64fbe4 bellard
GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
883 79aceca5 bellard
884 79aceca5 bellard
/* fres */
885 4ecc3190 bellard
GEN_FLOAT_BS(res, 0x3B, 0x18);
886 79aceca5 bellard
887 79aceca5 bellard
/* frsqrte */
888 4ecc3190 bellard
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
889 79aceca5 bellard
890 79aceca5 bellard
/* fsel */
891 4ecc3190 bellard
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
892 4ecc3190 bellard
/* fsub - fsubs */
893 9a64fbe4 bellard
GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
894 79aceca5 bellard
/* Optional: */
895 79aceca5 bellard
/* fsqrt */
896 c7d344af bellard
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
897 c7d344af bellard
{
898 c7d344af bellard
    if (!ctx->fpu_enabled) {
899 c7d344af bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
900 c7d344af bellard
        return;
901 c7d344af bellard
    }
902 c7d344af bellard
    gen_op_reset_scrfx();
903 c7d344af bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
904 c7d344af bellard
    gen_op_fsqrt();
905 c7d344af bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
906 c7d344af bellard
    if (Rc(ctx->opcode))
907 c7d344af bellard
        gen_op_set_Rc1();
908 c7d344af bellard
}
909 79aceca5 bellard
910 9a64fbe4 bellard
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
911 79aceca5 bellard
{
912 3cc62370 bellard
    if (!ctx->fpu_enabled) {
913 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
914 3cc62370 bellard
        return;
915 3cc62370 bellard
    }
916 9a64fbe4 bellard
    gen_op_reset_scrfx();
917 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
918 4ecc3190 bellard
    gen_op_fsqrt();
919 4ecc3190 bellard
    gen_op_frsp();
920 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
921 9a64fbe4 bellard
    if (Rc(ctx->opcode))
922 9a64fbe4 bellard
        gen_op_set_Rc1();
923 79aceca5 bellard
}
924 79aceca5 bellard
925 79aceca5 bellard
/***                     Floating-Point multiply-and-add                   ***/
926 4ecc3190 bellard
/* fmadd - fmadds */
927 9a64fbe4 bellard
GEN_FLOAT_ACB(madd, 0x1D);
928 4ecc3190 bellard
/* fmsub - fmsubs */
929 9a64fbe4 bellard
GEN_FLOAT_ACB(msub, 0x1C);
930 4ecc3190 bellard
/* fnmadd - fnmadds */
931 9a64fbe4 bellard
GEN_FLOAT_ACB(nmadd, 0x1F);
932 4ecc3190 bellard
/* fnmsub - fnmsubs */
933 9a64fbe4 bellard
GEN_FLOAT_ACB(nmsub, 0x1E);
934 79aceca5 bellard
935 79aceca5 bellard
/***                     Floating-Point round & convert                    ***/
936 79aceca5 bellard
/* fctiw */
937 9a64fbe4 bellard
GEN_FLOAT_B(ctiw, 0x0E, 0x00);
938 79aceca5 bellard
/* fctiwz */
939 9a64fbe4 bellard
GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
940 79aceca5 bellard
/* frsp */
941 9a64fbe4 bellard
GEN_FLOAT_B(rsp, 0x0C, 0x00);
942 79aceca5 bellard
943 79aceca5 bellard
/***                         Floating-Point compare                        ***/
944 79aceca5 bellard
/* fcmpo */
945 79aceca5 bellard
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
946 79aceca5 bellard
{
947 3cc62370 bellard
    if (!ctx->fpu_enabled) {
948 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
949 3cc62370 bellard
        return;
950 3cc62370 bellard
    }
951 9a64fbe4 bellard
    gen_op_reset_scrfx();
952 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));
953 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));
954 9a64fbe4 bellard
    gen_op_fcmpo();
955 9a64fbe4 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
956 79aceca5 bellard
}
957 79aceca5 bellard
958 79aceca5 bellard
/* fcmpu */
959 79aceca5 bellard
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
960 79aceca5 bellard
{
961 3cc62370 bellard
    if (!ctx->fpu_enabled) {
962 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
963 3cc62370 bellard
        return;
964 3cc62370 bellard
    }
965 9a64fbe4 bellard
    gen_op_reset_scrfx();
966 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rA(ctx->opcode));
967 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rB(ctx->opcode));
968 9a64fbe4 bellard
    gen_op_fcmpu();
969 9a64fbe4 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
970 79aceca5 bellard
}
971 79aceca5 bellard
972 9a64fbe4 bellard
/***                         Floating-point move                           ***/
973 9a64fbe4 bellard
/* fabs */
974 9a64fbe4 bellard
GEN_FLOAT_B(abs, 0x08, 0x08);
975 9a64fbe4 bellard
976 9a64fbe4 bellard
/* fmr  - fmr. */
977 9a64fbe4 bellard
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
978 9a64fbe4 bellard
{
979 3cc62370 bellard
    if (!ctx->fpu_enabled) {
980 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
981 3cc62370 bellard
        return;
982 3cc62370 bellard
    }
983 9a64fbe4 bellard
    gen_op_reset_scrfx();
984 9a64fbe4 bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
985 9a64fbe4 bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
986 9a64fbe4 bellard
    if (Rc(ctx->opcode))
987 9a64fbe4 bellard
        gen_op_set_Rc1();
988 9a64fbe4 bellard
}
989 9a64fbe4 bellard
990 9a64fbe4 bellard
/* fnabs */
991 9a64fbe4 bellard
GEN_FLOAT_B(nabs, 0x08, 0x04);
992 9a64fbe4 bellard
/* fneg */
993 9a64fbe4 bellard
GEN_FLOAT_B(neg, 0x08, 0x01);
994 9a64fbe4 bellard
995 79aceca5 bellard
/***                  Floating-Point status & ctrl register                ***/
996 79aceca5 bellard
/* mcrfs */
997 79aceca5 bellard
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
998 79aceca5 bellard
{
999 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1000 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1001 3cc62370 bellard
        return;
1002 3cc62370 bellard
    }
1003 fb0eaffc bellard
    gen_op_load_fpscr_T0(crfS(ctx->opcode));
1004 fb0eaffc bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
1005 fb0eaffc bellard
    gen_op_clear_fpscr(crfS(ctx->opcode));
1006 79aceca5 bellard
}
1007 79aceca5 bellard
1008 79aceca5 bellard
/* mffs */
1009 79aceca5 bellard
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1010 79aceca5 bellard
{
1011 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1012 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1013 3cc62370 bellard
        return;
1014 3cc62370 bellard
    }
1015 28b6751f bellard
    gen_op_load_fpscr();
1016 fb0eaffc bellard
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1017 fb0eaffc bellard
    if (Rc(ctx->opcode))
1018 fb0eaffc bellard
        gen_op_set_Rc1();
1019 79aceca5 bellard
}
1020 79aceca5 bellard
1021 79aceca5 bellard
/* mtfsb0 */
1022 79aceca5 bellard
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1023 79aceca5 bellard
{
1024 fb0eaffc bellard
    uint8_t crb;
1025 fb0eaffc bellard
    
1026 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1027 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1028 3cc62370 bellard
        return;
1029 3cc62370 bellard
    }
1030 fb0eaffc bellard
    crb = crbD(ctx->opcode) >> 2;
1031 fb0eaffc bellard
    gen_op_load_fpscr_T0(crb);
1032 fb0eaffc bellard
    gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
1033 fb0eaffc bellard
    gen_op_store_T0_fpscr(crb);
1034 fb0eaffc bellard
    if (Rc(ctx->opcode))
1035 fb0eaffc bellard
        gen_op_set_Rc1();
1036 79aceca5 bellard
}
1037 79aceca5 bellard
1038 79aceca5 bellard
/* mtfsb1 */
1039 79aceca5 bellard
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1040 79aceca5 bellard
{
1041 fb0eaffc bellard
    uint8_t crb;
1042 fb0eaffc bellard
    
1043 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1044 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1045 3cc62370 bellard
        return;
1046 3cc62370 bellard
    }
1047 fb0eaffc bellard
    crb = crbD(ctx->opcode) >> 2;
1048 fb0eaffc bellard
    gen_op_load_fpscr_T0(crb);
1049 fb0eaffc bellard
    gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1050 fb0eaffc bellard
    gen_op_store_T0_fpscr(crb);
1051 fb0eaffc bellard
    if (Rc(ctx->opcode))
1052 fb0eaffc bellard
        gen_op_set_Rc1();
1053 79aceca5 bellard
}
1054 79aceca5 bellard
1055 79aceca5 bellard
/* mtfsf */
1056 79aceca5 bellard
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1057 79aceca5 bellard
{
1058 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1059 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1060 3cc62370 bellard
        return;
1061 3cc62370 bellard
    }
1062 fb0eaffc bellard
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1063 28b6751f bellard
    gen_op_store_fpscr(FM(ctx->opcode));
1064 fb0eaffc bellard
    if (Rc(ctx->opcode))
1065 fb0eaffc bellard
        gen_op_set_Rc1();
1066 79aceca5 bellard
}
1067 79aceca5 bellard
1068 79aceca5 bellard
/* mtfsfi */
1069 79aceca5 bellard
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1070 79aceca5 bellard
{
1071 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1072 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1073 3cc62370 bellard
        return;
1074 3cc62370 bellard
    }
1075 fb0eaffc bellard
    gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1076 fb0eaffc bellard
    if (Rc(ctx->opcode))
1077 fb0eaffc bellard
        gen_op_set_Rc1();
1078 79aceca5 bellard
}
1079 79aceca5 bellard
1080 79aceca5 bellard
/***                             Integer load                              ***/
1081 111bfab3 bellard
#define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
1082 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1083 111bfab3 bellard
#define OP_LD_TABLE(width)                                                    \
1084 111bfab3 bellard
static GenOpFunc *gen_op_l##width[] = {                                       \
1085 111bfab3 bellard
    &gen_op_l##width##_raw,                                                   \
1086 111bfab3 bellard
    &gen_op_l##width##_le_raw,                                                \
1087 111bfab3 bellard
};
1088 111bfab3 bellard
#define OP_ST_TABLE(width)                                                    \
1089 111bfab3 bellard
static GenOpFunc *gen_op_st##width[] = {                                      \
1090 111bfab3 bellard
    &gen_op_st##width##_raw,                                                  \
1091 111bfab3 bellard
    &gen_op_st##width##_le_raw,                                               \
1092 111bfab3 bellard
};
1093 111bfab3 bellard
/* Byte access routine are endian safe */
1094 111bfab3 bellard
#define gen_op_stb_le_raw gen_op_stb_raw
1095 111bfab3 bellard
#define gen_op_lbz_le_raw gen_op_lbz_raw
1096 9a64fbe4 bellard
#else
1097 9a64fbe4 bellard
#define OP_LD_TABLE(width)                                                    \
1098 9a64fbe4 bellard
static GenOpFunc *gen_op_l##width[] = {                                       \
1099 9a64fbe4 bellard
    &gen_op_l##width##_user,                                                  \
1100 111bfab3 bellard
    &gen_op_l##width##_le_user,                                               \
1101 9a64fbe4 bellard
    &gen_op_l##width##_kernel,                                                \
1102 111bfab3 bellard
    &gen_op_l##width##_le_kernel,                                             \
1103 111bfab3 bellard
};
1104 9a64fbe4 bellard
#define OP_ST_TABLE(width)                                                    \
1105 9a64fbe4 bellard
static GenOpFunc *gen_op_st##width[] = {                                      \
1106 9a64fbe4 bellard
    &gen_op_st##width##_user,                                                 \
1107 111bfab3 bellard
    &gen_op_st##width##_le_user,                                              \
1108 9a64fbe4 bellard
    &gen_op_st##width##_kernel,                                               \
1109 111bfab3 bellard
    &gen_op_st##width##_le_kernel,                                            \
1110 111bfab3 bellard
};
1111 111bfab3 bellard
/* Byte access routine are endian safe */
1112 111bfab3 bellard
#define gen_op_stb_le_user gen_op_stb_user
1113 111bfab3 bellard
#define gen_op_lbz_le_user gen_op_lbz_user
1114 111bfab3 bellard
#define gen_op_stb_le_kernel gen_op_stb_kernel
1115 111bfab3 bellard
#define gen_op_lbz_le_kernel gen_op_lbz_kernel
1116 9a64fbe4 bellard
#endif
1117 9a64fbe4 bellard
1118 9a64fbe4 bellard
#define GEN_LD(width, opc)                                                    \
1119 79aceca5 bellard
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)               \
1120 79aceca5 bellard
{                                                                             \
1121 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1122 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1123 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1124 79aceca5 bellard
    } else {                                                                  \
1125 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1126 9a64fbe4 bellard
        if (simm != 0)                                                        \
1127 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1128 79aceca5 bellard
    }                                                                         \
1129 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1130 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1131 79aceca5 bellard
}
1132 79aceca5 bellard
1133 9a64fbe4 bellard
#define GEN_LDU(width, opc)                                                   \
1134 79aceca5 bellard
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)            \
1135 79aceca5 bellard
{                                                                             \
1136 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1137 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1138 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1139 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1140 9fddaa0c bellard
        return;                                                               \
1141 9a64fbe4 bellard
    }                                                                         \
1142 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1143 9a64fbe4 bellard
    if (simm != 0)                                                            \
1144 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1145 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1146 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1147 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1148 79aceca5 bellard
}
1149 79aceca5 bellard
1150 9a64fbe4 bellard
#define GEN_LDUX(width, opc)                                                  \
1151 79aceca5 bellard
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)           \
1152 79aceca5 bellard
{                                                                             \
1153 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1154 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1155 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1156 9fddaa0c bellard
        return;                                                               \
1157 9a64fbe4 bellard
    }                                                                         \
1158 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1159 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1160 9a64fbe4 bellard
    gen_op_add();                                                             \
1161 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1162 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1163 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1164 79aceca5 bellard
}
1165 79aceca5 bellard
1166 9a64fbe4 bellard
#define GEN_LDX(width, opc2, opc3)                                            \
1167 79aceca5 bellard
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)           \
1168 79aceca5 bellard
{                                                                             \
1169 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1170 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1171 79aceca5 bellard
    } else {                                                                  \
1172 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1173 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1174 9a64fbe4 bellard
        gen_op_add();                                                         \
1175 79aceca5 bellard
    }                                                                         \
1176 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1177 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1178 79aceca5 bellard
}
1179 79aceca5 bellard
1180 9a64fbe4 bellard
#define GEN_LDS(width, op)                                                    \
1181 9a64fbe4 bellard
OP_LD_TABLE(width);                                                           \
1182 9a64fbe4 bellard
GEN_LD(width, op | 0x20);                                                     \
1183 9a64fbe4 bellard
GEN_LDU(width, op | 0x21);                                                    \
1184 9a64fbe4 bellard
GEN_LDUX(width, op | 0x01);                                                   \
1185 9a64fbe4 bellard
GEN_LDX(width, 0x17, op | 0x00)
1186 79aceca5 bellard
1187 79aceca5 bellard
/* lbz lbzu lbzux lbzx */
1188 9a64fbe4 bellard
GEN_LDS(bz, 0x02);
1189 79aceca5 bellard
/* lha lhau lhaux lhax */
1190 9a64fbe4 bellard
GEN_LDS(ha, 0x0A);
1191 79aceca5 bellard
/* lhz lhzu lhzux lhzx */
1192 9a64fbe4 bellard
GEN_LDS(hz, 0x08);
1193 79aceca5 bellard
/* lwz lwzu lwzux lwzx */
1194 9a64fbe4 bellard
GEN_LDS(wz, 0x00);
1195 79aceca5 bellard
1196 79aceca5 bellard
/***                              Integer store                            ***/
1197 9a64fbe4 bellard
#define GEN_ST(width, opc)                                                    \
1198 79aceca5 bellard
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)              \
1199 79aceca5 bellard
{                                                                             \
1200 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1201 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1202 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1203 79aceca5 bellard
    } else {                                                                  \
1204 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1205 9a64fbe4 bellard
        if (simm != 0)                                                        \
1206 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1207 79aceca5 bellard
    }                                                                         \
1208 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1209 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1210 79aceca5 bellard
}
1211 79aceca5 bellard
1212 9a64fbe4 bellard
#define GEN_STU(width, opc)                                                   \
1213 79aceca5 bellard
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)           \
1214 79aceca5 bellard
{                                                                             \
1215 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1216 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1217 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1218 9fddaa0c bellard
        return;                                                               \
1219 9a64fbe4 bellard
    }                                                                         \
1220 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1221 9a64fbe4 bellard
    if (simm != 0)                                                            \
1222 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1223 79aceca5 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1224 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1225 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1226 79aceca5 bellard
}
1227 79aceca5 bellard
1228 9a64fbe4 bellard
#define GEN_STUX(width, opc)                                                  \
1229 79aceca5 bellard
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)          \
1230 79aceca5 bellard
{                                                                             \
1231 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1232 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1233 9fddaa0c bellard
        return;                                                               \
1234 9a64fbe4 bellard
    }                                                                         \
1235 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1236 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1237 9a64fbe4 bellard
    gen_op_add();                                                             \
1238 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1239 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1240 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1241 79aceca5 bellard
}
1242 79aceca5 bellard
1243 9a64fbe4 bellard
#define GEN_STX(width, opc2, opc3)                                            \
1244 79aceca5 bellard
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)          \
1245 79aceca5 bellard
{                                                                             \
1246 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1247 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1248 79aceca5 bellard
    } else {                                                                  \
1249 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1250 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1251 9a64fbe4 bellard
        gen_op_add();                                                         \
1252 79aceca5 bellard
    }                                                                         \
1253 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1254 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1255 79aceca5 bellard
}
1256 79aceca5 bellard
1257 9a64fbe4 bellard
#define GEN_STS(width, op)                                                    \
1258 9a64fbe4 bellard
OP_ST_TABLE(width);                                                           \
1259 9a64fbe4 bellard
GEN_ST(width, op | 0x20);                                                     \
1260 9a64fbe4 bellard
GEN_STU(width, op | 0x21);                                                    \
1261 9a64fbe4 bellard
GEN_STUX(width, op | 0x01);                                                   \
1262 9a64fbe4 bellard
GEN_STX(width, 0x17, op | 0x00)
1263 79aceca5 bellard
1264 79aceca5 bellard
/* stb stbu stbux stbx */
1265 9a64fbe4 bellard
GEN_STS(b, 0x06);
1266 79aceca5 bellard
/* sth sthu sthux sthx */
1267 9a64fbe4 bellard
GEN_STS(h, 0x0C);
1268 79aceca5 bellard
/* stw stwu stwux stwx */
1269 9a64fbe4 bellard
GEN_STS(w, 0x04);
1270 79aceca5 bellard
1271 79aceca5 bellard
/***                Integer load and store with byte reverse               ***/
1272 79aceca5 bellard
/* lhbrx */
1273 9a64fbe4 bellard
OP_LD_TABLE(hbr);
1274 9a64fbe4 bellard
GEN_LDX(hbr, 0x16, 0x18);
1275 79aceca5 bellard
/* lwbrx */
1276 9a64fbe4 bellard
OP_LD_TABLE(wbr);
1277 9a64fbe4 bellard
GEN_LDX(wbr, 0x16, 0x10);
1278 79aceca5 bellard
/* sthbrx */
1279 9a64fbe4 bellard
OP_ST_TABLE(hbr);
1280 9a64fbe4 bellard
GEN_STX(hbr, 0x16, 0x1C);
1281 79aceca5 bellard
/* stwbrx */
1282 9a64fbe4 bellard
OP_ST_TABLE(wbr);
1283 9a64fbe4 bellard
GEN_STX(wbr, 0x16, 0x14);
1284 79aceca5 bellard
1285 79aceca5 bellard
/***                    Integer load and store multiple                    ***/
1286 111bfab3 bellard
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1287 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1288 111bfab3 bellard
static GenOpFunc1 *gen_op_lmw[] = {
1289 111bfab3 bellard
    &gen_op_lmw_raw,
1290 111bfab3 bellard
    &gen_op_lmw_le_raw,
1291 111bfab3 bellard
};
1292 111bfab3 bellard
static GenOpFunc1 *gen_op_stmw[] = {
1293 111bfab3 bellard
    &gen_op_stmw_raw,
1294 111bfab3 bellard
    &gen_op_stmw_le_raw,
1295 111bfab3 bellard
};
1296 9a64fbe4 bellard
#else
1297 9a64fbe4 bellard
static GenOpFunc1 *gen_op_lmw[] = {
1298 9a64fbe4 bellard
    &gen_op_lmw_user,
1299 111bfab3 bellard
    &gen_op_lmw_le_user,
1300 9a64fbe4 bellard
    &gen_op_lmw_kernel,
1301 111bfab3 bellard
    &gen_op_lmw_le_kernel,
1302 9a64fbe4 bellard
};
1303 9a64fbe4 bellard
static GenOpFunc1 *gen_op_stmw[] = {
1304 9a64fbe4 bellard
    &gen_op_stmw_user,
1305 111bfab3 bellard
    &gen_op_stmw_le_user,
1306 9a64fbe4 bellard
    &gen_op_stmw_kernel,
1307 111bfab3 bellard
    &gen_op_stmw_le_kernel,
1308 9a64fbe4 bellard
};
1309 9a64fbe4 bellard
#endif
1310 9a64fbe4 bellard
1311 79aceca5 bellard
/* lmw */
1312 79aceca5 bellard
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1313 79aceca5 bellard
{
1314 9a64fbe4 bellard
    int simm = SIMM(ctx->opcode);
1315 9a64fbe4 bellard
1316 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1317 9a64fbe4 bellard
        gen_op_set_T0(simm);
1318 79aceca5 bellard
    } else {
1319 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1320 9a64fbe4 bellard
        if (simm != 0)
1321 9a64fbe4 bellard
            gen_op_addi(simm);
1322 79aceca5 bellard
    }
1323 9a64fbe4 bellard
    op_ldstm(lmw, rD(ctx->opcode));
1324 79aceca5 bellard
}
1325 79aceca5 bellard
1326 79aceca5 bellard
/* stmw */
1327 79aceca5 bellard
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1328 79aceca5 bellard
{
1329 9a64fbe4 bellard
    int simm = SIMM(ctx->opcode);
1330 9a64fbe4 bellard
1331 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1332 9a64fbe4 bellard
        gen_op_set_T0(simm);
1333 79aceca5 bellard
    } else {
1334 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1335 9a64fbe4 bellard
        if (simm != 0)
1336 9a64fbe4 bellard
            gen_op_addi(simm);
1337 79aceca5 bellard
    }
1338 9a64fbe4 bellard
    op_ldstm(stmw, rS(ctx->opcode));
1339 79aceca5 bellard
}
1340 79aceca5 bellard
1341 79aceca5 bellard
/***                    Integer load and store strings                     ***/
1342 9a64fbe4 bellard
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1343 9a64fbe4 bellard
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1344 111bfab3 bellard
#if defined(CONFIG_USER_ONLY)
1345 111bfab3 bellard
static GenOpFunc1 *gen_op_lswi[] = {
1346 111bfab3 bellard
    &gen_op_lswi_raw,
1347 111bfab3 bellard
    &gen_op_lswi_le_raw,
1348 111bfab3 bellard
};
1349 111bfab3 bellard
static GenOpFunc3 *gen_op_lswx[] = {
1350 111bfab3 bellard
    &gen_op_lswx_raw,
1351 111bfab3 bellard
    &gen_op_lswx_le_raw,
1352 111bfab3 bellard
};
1353 111bfab3 bellard
static GenOpFunc1 *gen_op_stsw[] = {
1354 111bfab3 bellard
    &gen_op_stsw_raw,
1355 111bfab3 bellard
    &gen_op_stsw_le_raw,
1356 111bfab3 bellard
};
1357 111bfab3 bellard
#else
1358 9a64fbe4 bellard
static GenOpFunc1 *gen_op_lswi[] = {
1359 9a64fbe4 bellard
    &gen_op_lswi_user,
1360 111bfab3 bellard
    &gen_op_lswi_le_user,
1361 9a64fbe4 bellard
    &gen_op_lswi_kernel,
1362 111bfab3 bellard
    &gen_op_lswi_le_kernel,
1363 9a64fbe4 bellard
};
1364 9a64fbe4 bellard
static GenOpFunc3 *gen_op_lswx[] = {
1365 9a64fbe4 bellard
    &gen_op_lswx_user,
1366 111bfab3 bellard
    &gen_op_lswx_le_user,
1367 9a64fbe4 bellard
    &gen_op_lswx_kernel,
1368 111bfab3 bellard
    &gen_op_lswx_le_kernel,
1369 9a64fbe4 bellard
};
1370 9a64fbe4 bellard
static GenOpFunc1 *gen_op_stsw[] = {
1371 9a64fbe4 bellard
    &gen_op_stsw_user,
1372 111bfab3 bellard
    &gen_op_stsw_le_user,
1373 9a64fbe4 bellard
    &gen_op_stsw_kernel,
1374 111bfab3 bellard
    &gen_op_stsw_le_kernel,
1375 9a64fbe4 bellard
};
1376 9a64fbe4 bellard
#endif
1377 9a64fbe4 bellard
1378 79aceca5 bellard
/* lswi */
1379 3fc6c082 bellard
/* PowerPC32 specification says we must generate an exception if
1380 9a64fbe4 bellard
 * rA is in the range of registers to be loaded.
1381 9a64fbe4 bellard
 * In an other hand, IBM says this is valid, but rA won't be loaded.
1382 9a64fbe4 bellard
 * For now, I'll follow the spec...
1383 9a64fbe4 bellard
 */
1384 79aceca5 bellard
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1385 79aceca5 bellard
{
1386 79aceca5 bellard
    int nb = NB(ctx->opcode);
1387 79aceca5 bellard
    int start = rD(ctx->opcode);
1388 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1389 79aceca5 bellard
    int nr;
1390 79aceca5 bellard
1391 79aceca5 bellard
    if (nb == 0)
1392 79aceca5 bellard
        nb = 32;
1393 79aceca5 bellard
    nr = nb / 4;
1394 297d8e62 bellard
    if (((start + nr) > 32  && start <= ra && (start + nr - 32) > ra) ||
1395 297d8e62 bellard
        ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1396 9fddaa0c bellard
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1397 9fddaa0c bellard
        return;
1398 297d8e62 bellard
    }
1399 9a64fbe4 bellard
    if (ra == 0) {
1400 79aceca5 bellard
        gen_op_set_T0(0);
1401 79aceca5 bellard
    } else {
1402 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1403 79aceca5 bellard
    }
1404 9a64fbe4 bellard
    gen_op_set_T1(nb);
1405 8dd4983c bellard
    /* NIP cannot be restored if the memory exception comes from an helper */
1406 8dd4983c bellard
    gen_op_update_nip((ctx)->nip - 4); 
1407 9a64fbe4 bellard
    op_ldsts(lswi, start);
1408 79aceca5 bellard
}
1409 79aceca5 bellard
1410 79aceca5 bellard
/* lswx */
1411 79aceca5 bellard
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1412 79aceca5 bellard
{
1413 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1414 9a64fbe4 bellard
    int rb = rB(ctx->opcode);
1415 9a64fbe4 bellard
1416 9a64fbe4 bellard
    if (ra == 0) {
1417 9a64fbe4 bellard
        gen_op_load_gpr_T0(rb);
1418 9a64fbe4 bellard
        ra = rb;
1419 79aceca5 bellard
    } else {
1420 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1421 9a64fbe4 bellard
        gen_op_load_gpr_T1(rb);
1422 9a64fbe4 bellard
        gen_op_add();
1423 79aceca5 bellard
    }
1424 9a64fbe4 bellard
    gen_op_load_xer_bc();
1425 8dd4983c bellard
    /* NIP cannot be restored if the memory exception comes from an helper */
1426 8dd4983c bellard
    gen_op_update_nip((ctx)->nip - 4); 
1427 9a64fbe4 bellard
    op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1428 79aceca5 bellard
}
1429 79aceca5 bellard
1430 79aceca5 bellard
/* stswi */
1431 79aceca5 bellard
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1432 79aceca5 bellard
{
1433 4b3686fa bellard
    int nb = NB(ctx->opcode);
1434 4b3686fa bellard
1435 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1436 79aceca5 bellard
        gen_op_set_T0(0);
1437 79aceca5 bellard
    } else {
1438 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1439 79aceca5 bellard
    }
1440 4b3686fa bellard
    if (nb == 0)
1441 4b3686fa bellard
        nb = 32;
1442 4b3686fa bellard
    gen_op_set_T1(nb);
1443 8dd4983c bellard
    /* NIP cannot be restored if the memory exception comes from an helper */
1444 8dd4983c bellard
    gen_op_update_nip((ctx)->nip - 4); 
1445 9a64fbe4 bellard
    op_ldsts(stsw, rS(ctx->opcode));
1446 79aceca5 bellard
}
1447 79aceca5 bellard
1448 79aceca5 bellard
/* stswx */
1449 79aceca5 bellard
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1450 79aceca5 bellard
{
1451 9a64fbe4 bellard
    int ra = rA(ctx->opcode);
1452 9a64fbe4 bellard
1453 9a64fbe4 bellard
    if (ra == 0) {
1454 9a64fbe4 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
1455 9a64fbe4 bellard
        ra = rB(ctx->opcode);
1456 79aceca5 bellard
    } else {
1457 9a64fbe4 bellard
        gen_op_load_gpr_T0(ra);
1458 9a64fbe4 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
1459 9a64fbe4 bellard
        gen_op_add();
1460 79aceca5 bellard
    }
1461 9a64fbe4 bellard
    gen_op_load_xer_bc();
1462 8dd4983c bellard
    /* NIP cannot be restored if the memory exception comes from an helper */
1463 8dd4983c bellard
    gen_op_update_nip((ctx)->nip - 4); 
1464 9a64fbe4 bellard
    op_ldsts(stsw, rS(ctx->opcode));
1465 79aceca5 bellard
}
1466 79aceca5 bellard
1467 79aceca5 bellard
/***                        Memory synchronisation                         ***/
1468 79aceca5 bellard
/* eieio */
1469 79aceca5 bellard
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1470 79aceca5 bellard
{
1471 79aceca5 bellard
}
1472 79aceca5 bellard
1473 79aceca5 bellard
/* isync */
1474 79aceca5 bellard
GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1475 79aceca5 bellard
{
1476 79aceca5 bellard
}
1477 79aceca5 bellard
1478 111bfab3 bellard
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1479 111bfab3 bellard
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1480 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1481 111bfab3 bellard
static GenOpFunc *gen_op_lwarx[] = {
1482 111bfab3 bellard
    &gen_op_lwarx_raw,
1483 111bfab3 bellard
    &gen_op_lwarx_le_raw,
1484 111bfab3 bellard
};
1485 111bfab3 bellard
static GenOpFunc *gen_op_stwcx[] = {
1486 111bfab3 bellard
    &gen_op_stwcx_raw,
1487 111bfab3 bellard
    &gen_op_stwcx_le_raw,
1488 111bfab3 bellard
};
1489 9a64fbe4 bellard
#else
1490 985a19d6 bellard
static GenOpFunc *gen_op_lwarx[] = {
1491 985a19d6 bellard
    &gen_op_lwarx_user,
1492 111bfab3 bellard
    &gen_op_lwarx_le_user,
1493 985a19d6 bellard
    &gen_op_lwarx_kernel,
1494 111bfab3 bellard
    &gen_op_lwarx_le_kernel,
1495 985a19d6 bellard
};
1496 9a64fbe4 bellard
static GenOpFunc *gen_op_stwcx[] = {
1497 9a64fbe4 bellard
    &gen_op_stwcx_user,
1498 111bfab3 bellard
    &gen_op_stwcx_le_user,
1499 9a64fbe4 bellard
    &gen_op_stwcx_kernel,
1500 111bfab3 bellard
    &gen_op_stwcx_le_kernel,
1501 9a64fbe4 bellard
};
1502 9a64fbe4 bellard
#endif
1503 9a64fbe4 bellard
1504 111bfab3 bellard
/* lwarx */
1505 9a64fbe4 bellard
GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1506 79aceca5 bellard
{
1507 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {
1508 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
1509 79aceca5 bellard
    } else {
1510 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
1511 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
1512 9a64fbe4 bellard
        gen_op_add();
1513 79aceca5 bellard
    }
1514 985a19d6 bellard
    op_lwarx();
1515 79aceca5 bellard
    gen_op_store_T1_gpr(rD(ctx->opcode));
1516 79aceca5 bellard
}
1517 79aceca5 bellard
1518 79aceca5 bellard
/* stwcx. */
1519 9a64fbe4 bellard
GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1520 79aceca5 bellard
{
1521 79aceca5 bellard
        if (rA(ctx->opcode) == 0) {
1522 79aceca5 bellard
            gen_op_load_gpr_T0(rB(ctx->opcode));
1523 79aceca5 bellard
        } else {
1524 79aceca5 bellard
            gen_op_load_gpr_T0(rA(ctx->opcode));
1525 79aceca5 bellard
            gen_op_load_gpr_T1(rB(ctx->opcode));
1526 9a64fbe4 bellard
        gen_op_add();
1527 79aceca5 bellard
        }
1528 9a64fbe4 bellard
    gen_op_load_gpr_T1(rS(ctx->opcode));
1529 9a64fbe4 bellard
    op_stwcx();
1530 79aceca5 bellard
}
1531 79aceca5 bellard
1532 79aceca5 bellard
/* sync */
1533 79aceca5 bellard
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1534 79aceca5 bellard
{
1535 79aceca5 bellard
}
1536 79aceca5 bellard
1537 79aceca5 bellard
/***                         Floating-point load                           ***/
1538 9a64fbe4 bellard
#define GEN_LDF(width, opc)                                                   \
1539 c7d344af bellard
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)                 \
1540 79aceca5 bellard
{                                                                             \
1541 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1542 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1543 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1544 4ecc3190 bellard
        return;                                                               \
1545 4ecc3190 bellard
    }                                                                         \
1546 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1547 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1548 79aceca5 bellard
    } else {                                                                  \
1549 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1550 9a64fbe4 bellard
        if (simm != 0)                                                        \
1551 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1552 79aceca5 bellard
    }                                                                         \
1553 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1554 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1555 79aceca5 bellard
}
1556 79aceca5 bellard
1557 9a64fbe4 bellard
#define GEN_LDUF(width, opc)                                                  \
1558 c7d344af bellard
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)              \
1559 79aceca5 bellard
{                                                                             \
1560 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1561 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1562 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1563 4ecc3190 bellard
        return;                                                               \
1564 4ecc3190 bellard
    }                                                                         \
1565 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1566 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1567 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1568 9fddaa0c bellard
        return;                                                               \
1569 9a64fbe4 bellard
    }                                                                         \
1570 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1571 9a64fbe4 bellard
    if (simm != 0)                                                            \
1572 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1573 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1574 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1575 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1576 79aceca5 bellard
}
1577 79aceca5 bellard
1578 9a64fbe4 bellard
#define GEN_LDUXF(width, opc)                                                 \
1579 c7d344af bellard
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT)             \
1580 79aceca5 bellard
{                                                                             \
1581 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1582 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1583 4ecc3190 bellard
        return;                                                               \
1584 4ecc3190 bellard
    }                                                                         \
1585 79aceca5 bellard
    if (rA(ctx->opcode) == 0 ||                                               \
1586 9a64fbe4 bellard
        rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1587 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1588 9fddaa0c bellard
        return;                                                               \
1589 9a64fbe4 bellard
    }                                                                         \
1590 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1591 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1592 9a64fbe4 bellard
    gen_op_add();                                                             \
1593 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1594 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1595 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1596 79aceca5 bellard
}
1597 79aceca5 bellard
1598 9a64fbe4 bellard
#define GEN_LDXF(width, opc2, opc3)                                           \
1599 c7d344af bellard
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT)             \
1600 79aceca5 bellard
{                                                                             \
1601 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1602 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1603 4ecc3190 bellard
        return;                                                               \
1604 4ecc3190 bellard
    }                                                                         \
1605 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1606 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1607 79aceca5 bellard
    } else {                                                                  \
1608 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1609 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1610 9a64fbe4 bellard
        gen_op_add();                                                         \
1611 79aceca5 bellard
    }                                                                         \
1612 9a64fbe4 bellard
    op_ldst(l##width);                                                        \
1613 9a64fbe4 bellard
    gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1614 79aceca5 bellard
}
1615 79aceca5 bellard
1616 9a64fbe4 bellard
#define GEN_LDFS(width, op)                                                   \
1617 9a64fbe4 bellard
OP_LD_TABLE(width);                                                           \
1618 9a64fbe4 bellard
GEN_LDF(width, op | 0x20);                                                    \
1619 9a64fbe4 bellard
GEN_LDUF(width, op | 0x21);                                                   \
1620 9a64fbe4 bellard
GEN_LDUXF(width, op | 0x01);                                                  \
1621 9a64fbe4 bellard
GEN_LDXF(width, 0x17, op | 0x00)
1622 79aceca5 bellard
1623 79aceca5 bellard
/* lfd lfdu lfdux lfdx */
1624 9a64fbe4 bellard
GEN_LDFS(fd, 0x12);
1625 79aceca5 bellard
/* lfs lfsu lfsux lfsx */
1626 9a64fbe4 bellard
GEN_LDFS(fs, 0x10);
1627 79aceca5 bellard
1628 79aceca5 bellard
/***                         Floating-point store                          ***/
1629 79aceca5 bellard
#define GEN_STF(width, opc)                                                   \
1630 c7d344af bellard
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)                \
1631 79aceca5 bellard
{                                                                             \
1632 79aceca5 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1633 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1634 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1635 4ecc3190 bellard
        return;                                                               \
1636 4ecc3190 bellard
    }                                                                         \
1637 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1638 9a64fbe4 bellard
        gen_op_set_T0(simm);                                                  \
1639 79aceca5 bellard
    } else {                                                                  \
1640 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1641 9a64fbe4 bellard
        if (simm != 0)                                                        \
1642 9a64fbe4 bellard
            gen_op_addi(simm);                                                \
1643 79aceca5 bellard
    }                                                                         \
1644 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1645 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1646 79aceca5 bellard
}
1647 79aceca5 bellard
1648 9a64fbe4 bellard
#define GEN_STUF(width, opc)                                                  \
1649 c7d344af bellard
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)             \
1650 79aceca5 bellard
{                                                                             \
1651 9a64fbe4 bellard
    uint32_t simm = SIMM(ctx->opcode);                                        \
1652 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1653 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1654 4ecc3190 bellard
        return;                                                               \
1655 4ecc3190 bellard
    }                                                                         \
1656 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1657 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1658 9fddaa0c bellard
        return;                                                               \
1659 9a64fbe4 bellard
    }                                                                         \
1660 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1661 9a64fbe4 bellard
    if (simm != 0)                                                            \
1662 9a64fbe4 bellard
        gen_op_addi(simm);                                                    \
1663 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1664 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1665 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1666 79aceca5 bellard
}
1667 79aceca5 bellard
1668 9a64fbe4 bellard
#define GEN_STUXF(width, opc)                                                 \
1669 c7d344af bellard
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT)            \
1670 79aceca5 bellard
{                                                                             \
1671 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1672 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1673 4ecc3190 bellard
        return;                                                               \
1674 4ecc3190 bellard
    }                                                                         \
1675 9a64fbe4 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1676 9fddaa0c bellard
        RET_INVAL(ctx);                                                       \
1677 9fddaa0c bellard
        return;                                                               \
1678 9a64fbe4 bellard
    }                                                                         \
1679 79aceca5 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1680 79aceca5 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1681 9a64fbe4 bellard
    gen_op_add();                                                             \
1682 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1683 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1684 79aceca5 bellard
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1685 79aceca5 bellard
}
1686 79aceca5 bellard
1687 9a64fbe4 bellard
#define GEN_STXF(width, opc2, opc3)                                           \
1688 c7d344af bellard
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT)            \
1689 79aceca5 bellard
{                                                                             \
1690 4ecc3190 bellard
    if (!ctx->fpu_enabled) {                                                  \
1691 4ecc3190 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1692 4ecc3190 bellard
        return;                                                               \
1693 4ecc3190 bellard
    }                                                                         \
1694 79aceca5 bellard
    if (rA(ctx->opcode) == 0) {                                               \
1695 79aceca5 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1696 79aceca5 bellard
    } else {                                                                  \
1697 79aceca5 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1698 79aceca5 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1699 9a64fbe4 bellard
        gen_op_add();                                                         \
1700 79aceca5 bellard
    }                                                                         \
1701 9a64fbe4 bellard
    gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1702 9a64fbe4 bellard
    op_ldst(st##width);                                                       \
1703 79aceca5 bellard
}
1704 79aceca5 bellard
1705 9a64fbe4 bellard
#define GEN_STFS(width, op)                                                   \
1706 9a64fbe4 bellard
OP_ST_TABLE(width);                                                           \
1707 9a64fbe4 bellard
GEN_STF(width, op | 0x20);                                                    \
1708 9a64fbe4 bellard
GEN_STUF(width, op | 0x21);                                                   \
1709 9a64fbe4 bellard
GEN_STUXF(width, op | 0x01);                                                  \
1710 9a64fbe4 bellard
GEN_STXF(width, 0x17, op | 0x00)
1711 79aceca5 bellard
1712 79aceca5 bellard
/* stfd stfdu stfdux stfdx */
1713 9a64fbe4 bellard
GEN_STFS(fd, 0x16);
1714 79aceca5 bellard
/* stfs stfsu stfsux stfsx */
1715 9a64fbe4 bellard
GEN_STFS(fs, 0x14);
1716 79aceca5 bellard
1717 79aceca5 bellard
/* Optional: */
1718 79aceca5 bellard
/* stfiwx */
1719 79aceca5 bellard
GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1720 79aceca5 bellard
{
1721 3cc62370 bellard
    if (!ctx->fpu_enabled) {
1722 3cc62370 bellard
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1723 3cc62370 bellard
        return;
1724 3cc62370 bellard
    }
1725 9fddaa0c bellard
    RET_INVAL(ctx);
1726 79aceca5 bellard
}
1727 79aceca5 bellard
1728 79aceca5 bellard
/***                                Branch                                 ***/
1729 79aceca5 bellard
1730 c1942362 bellard
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1731 c1942362 bellard
{
1732 c1942362 bellard
    TranslationBlock *tb;
1733 c1942362 bellard
    tb = ctx->tb;
1734 c1942362 bellard
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1735 c1942362 bellard
        if (n == 0)
1736 c1942362 bellard
            gen_op_goto_tb0(TBPARAM(tb));
1737 c1942362 bellard
        else
1738 c1942362 bellard
            gen_op_goto_tb1(TBPARAM(tb));
1739 c1942362 bellard
        gen_op_set_T1(dest);
1740 c1942362 bellard
        gen_op_b_T1();
1741 c1942362 bellard
        gen_op_set_T0((long)tb + n);
1742 ea4e754f bellard
        if (ctx->singlestep_enabled)
1743 ea4e754f bellard
            gen_op_debug();
1744 c1942362 bellard
        gen_op_exit_tb();
1745 c1942362 bellard
    } else {
1746 c1942362 bellard
        gen_op_set_T1(dest);
1747 c1942362 bellard
        gen_op_b_T1();
1748 ea4e754f bellard
        if (ctx->singlestep_enabled)
1749 ea4e754f bellard
            gen_op_debug();
1750 c1942362 bellard
        gen_op_set_T0(0);
1751 c1942362 bellard
        gen_op_exit_tb();
1752 c1942362 bellard
    }
1753 c53be334 bellard
}
1754 c53be334 bellard
1755 79aceca5 bellard
/* b ba bl bla */
1756 79aceca5 bellard
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1757 79aceca5 bellard
{
1758 38a64f9d bellard
    uint32_t li, target;
1759 38a64f9d bellard
1760 38a64f9d bellard
    /* sign extend LI */
1761 38a64f9d bellard
    li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
1762 79aceca5 bellard
1763 79aceca5 bellard
    if (AA(ctx->opcode) == 0)
1764 046d6672 bellard
        target = ctx->nip + li - 4;
1765 79aceca5 bellard
    else
1766 9a64fbe4 bellard
        target = li;
1767 9a64fbe4 bellard
    if (LK(ctx->opcode)) {
1768 046d6672 bellard
        gen_op_setlr(ctx->nip);
1769 9a64fbe4 bellard
    }
1770 c1942362 bellard
    gen_goto_tb(ctx, 0, target);
1771 9a64fbe4 bellard
    ctx->exception = EXCP_BRANCH;
1772 79aceca5 bellard
}
1773 79aceca5 bellard
1774 e98a6e40 bellard
#define BCOND_IM  0
1775 e98a6e40 bellard
#define BCOND_LR  1
1776 e98a6e40 bellard
#define BCOND_CTR 2
1777 e98a6e40 bellard
1778 e98a6e40 bellard
static inline void gen_bcond(DisasContext *ctx, int type) 
1779 e98a6e40 bellard
{                                                                             
1780 e98a6e40 bellard
    uint32_t target = 0;
1781 e98a6e40 bellard
    uint32_t bo = BO(ctx->opcode);                                            
1782 e98a6e40 bellard
    uint32_t bi = BI(ctx->opcode);                                            
1783 e98a6e40 bellard
    uint32_t mask;                                                            
1784 e98a6e40 bellard
    uint32_t li;
1785 e98a6e40 bellard
1786 e98a6e40 bellard
    if ((bo & 0x4) == 0)
1787 e98a6e40 bellard
        gen_op_dec_ctr();                                                     
1788 e98a6e40 bellard
    switch(type) {
1789 e98a6e40 bellard
    case BCOND_IM:
1790 18fba28c bellard
        li = (int32_t)((int16_t)(BD(ctx->opcode)));
1791 e98a6e40 bellard
        if (AA(ctx->opcode) == 0) {
1792 046d6672 bellard
            target = ctx->nip + li - 4;
1793 e98a6e40 bellard
        } else {
1794 e98a6e40 bellard
            target = li;
1795 e98a6e40 bellard
        }
1796 e98a6e40 bellard
        break;
1797 e98a6e40 bellard
    case BCOND_CTR:
1798 e98a6e40 bellard
        gen_op_movl_T1_ctr();
1799 e98a6e40 bellard
        break;
1800 e98a6e40 bellard
    default:
1801 e98a6e40 bellard
    case BCOND_LR:
1802 e98a6e40 bellard
        gen_op_movl_T1_lr();
1803 e98a6e40 bellard
        break;
1804 e98a6e40 bellard
    }
1805 e98a6e40 bellard
    if (LK(ctx->opcode)) {                                        
1806 046d6672 bellard
        gen_op_setlr(ctx->nip);
1807 e98a6e40 bellard
    }
1808 e98a6e40 bellard
    if (bo & 0x10) {
1809 e98a6e40 bellard
        /* No CR condition */                                                 
1810 e98a6e40 bellard
        switch (bo & 0x6) {                                                   
1811 e98a6e40 bellard
        case 0:                                                               
1812 e98a6e40 bellard
            gen_op_test_ctr();
1813 e98a6e40 bellard
            break;
1814 e98a6e40 bellard
        case 2:                                                               
1815 e98a6e40 bellard
            gen_op_test_ctrz();
1816 e98a6e40 bellard
            break;                                                            
1817 e98a6e40 bellard
        default:
1818 e98a6e40 bellard
        case 4:                                                               
1819 e98a6e40 bellard
        case 6:                                                               
1820 e98a6e40 bellard
            if (type == BCOND_IM) {
1821 c1942362 bellard
                gen_goto_tb(ctx, 0, target);
1822 e98a6e40 bellard
            } else {
1823 e98a6e40 bellard
                gen_op_b_T1();
1824 e98a6e40 bellard
            }
1825 e98a6e40 bellard
            goto no_test;
1826 e98a6e40 bellard
        }
1827 e98a6e40 bellard
    } else {                                                                  
1828 e98a6e40 bellard
        mask = 1 << (3 - (bi & 0x03));                                        
1829 e98a6e40 bellard
        gen_op_load_crf_T0(bi >> 2);                                          
1830 e98a6e40 bellard
        if (bo & 0x8) {                                                       
1831 e98a6e40 bellard
            switch (bo & 0x6) {                                               
1832 e98a6e40 bellard
            case 0:                                                           
1833 e98a6e40 bellard
                gen_op_test_ctr_true(mask);
1834 e98a6e40 bellard
                break;                                                        
1835 e98a6e40 bellard
            case 2:                                                           
1836 e98a6e40 bellard
                gen_op_test_ctrz_true(mask);
1837 e98a6e40 bellard
                break;                                                        
1838 e98a6e40 bellard
            default:                                                          
1839 e98a6e40 bellard
            case 4:                                                           
1840 e98a6e40 bellard
            case 6:                                                           
1841 e98a6e40 bellard
                gen_op_test_true(mask);
1842 e98a6e40 bellard
                break;                                                        
1843 e98a6e40 bellard
            }                                                                 
1844 e98a6e40 bellard
        } else {                                                              
1845 e98a6e40 bellard
            switch (bo & 0x6) {                                               
1846 e98a6e40 bellard
            case 0:                                                           
1847 e98a6e40 bellard
                gen_op_test_ctr_false(mask);
1848 e98a6e40 bellard
                break;                                                        
1849 e98a6e40 bellard
            case 2:                                                           
1850 e98a6e40 bellard
                gen_op_test_ctrz_false(mask);
1851 e98a6e40 bellard
                break;                                                        
1852 e98a6e40 bellard
            default:
1853 e98a6e40 bellard
            case 4:                                                           
1854 e98a6e40 bellard
            case 6:                                                           
1855 e98a6e40 bellard
                gen_op_test_false(mask);
1856 e98a6e40 bellard
                break;                                                        
1857 e98a6e40 bellard
            }                                                                 
1858 e98a6e40 bellard
        }                                                                     
1859 e98a6e40 bellard
    }                                                                         
1860 e98a6e40 bellard
    if (type == BCOND_IM) {
1861 c53be334 bellard
        int l1 = gen_new_label();
1862 c53be334 bellard
        gen_op_jz_T0(l1);
1863 c1942362 bellard
        gen_goto_tb(ctx, 0, target);
1864 c53be334 bellard
        gen_set_label(l1);
1865 c1942362 bellard
        gen_goto_tb(ctx, 1, ctx->nip);
1866 e98a6e40 bellard
    } else {
1867 046d6672 bellard
        gen_op_btest_T1(ctx->nip);
1868 e98a6e40 bellard
    }
1869 e98a6e40 bellard
 no_test:
1870 e98a6e40 bellard
    ctx->exception = EXCP_BRANCH;                                             
1871 e98a6e40 bellard
}
1872 e98a6e40 bellard
1873 e98a6e40 bellard
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1874 e98a6e40 bellard
{                                                                             
1875 e98a6e40 bellard
    gen_bcond(ctx, BCOND_IM);
1876 e98a6e40 bellard
}
1877 e98a6e40 bellard
1878 e98a6e40 bellard
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1879 e98a6e40 bellard
{                                                                             
1880 e98a6e40 bellard
    gen_bcond(ctx, BCOND_CTR);
1881 e98a6e40 bellard
}
1882 e98a6e40 bellard
1883 e98a6e40 bellard
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1884 e98a6e40 bellard
{                                                                             
1885 e98a6e40 bellard
    gen_bcond(ctx, BCOND_LR);
1886 e98a6e40 bellard
}
1887 79aceca5 bellard
1888 79aceca5 bellard
/***                      Condition register logical                       ***/
1889 79aceca5 bellard
#define GEN_CRLOGIC(op, opc)                                                  \
1890 79aceca5 bellard
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
1891 79aceca5 bellard
{                                                                             \
1892 79aceca5 bellard
    gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
1893 79aceca5 bellard
    gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03));                         \
1894 79aceca5 bellard
    gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
1895 79aceca5 bellard
    gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03));                         \
1896 79aceca5 bellard
    gen_op_##op();                                                            \
1897 79aceca5 bellard
    gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
1898 79aceca5 bellard
    gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))),                \
1899 79aceca5 bellard
                     3 - (crbD(ctx->opcode) & 0x03));                         \
1900 79aceca5 bellard
    gen_op_store_T1_crf(crbD(ctx->opcode) >> 2);                              \
1901 79aceca5 bellard
}
1902 79aceca5 bellard
1903 79aceca5 bellard
/* crand */
1904 79aceca5 bellard
GEN_CRLOGIC(and, 0x08)
1905 79aceca5 bellard
/* crandc */
1906 79aceca5 bellard
GEN_CRLOGIC(andc, 0x04)
1907 79aceca5 bellard
/* creqv */
1908 79aceca5 bellard
GEN_CRLOGIC(eqv, 0x09)
1909 79aceca5 bellard
/* crnand */
1910 79aceca5 bellard
GEN_CRLOGIC(nand, 0x07)
1911 79aceca5 bellard
/* crnor */
1912 79aceca5 bellard
GEN_CRLOGIC(nor, 0x01)
1913 79aceca5 bellard
/* cror */
1914 79aceca5 bellard
GEN_CRLOGIC(or, 0x0E)
1915 79aceca5 bellard
/* crorc */
1916 79aceca5 bellard
GEN_CRLOGIC(orc, 0x0D)
1917 79aceca5 bellard
/* crxor */
1918 79aceca5 bellard
GEN_CRLOGIC(xor, 0x06)
1919 79aceca5 bellard
/* mcrf */
1920 79aceca5 bellard
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1921 79aceca5 bellard
{
1922 79aceca5 bellard
    gen_op_load_crf_T0(crfS(ctx->opcode));
1923 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
1924 79aceca5 bellard
}
1925 79aceca5 bellard
1926 79aceca5 bellard
/***                           System linkage                              ***/
1927 79aceca5 bellard
/* rfi (supervisor only) */
1928 79aceca5 bellard
GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1929 79aceca5 bellard
{
1930 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1931 9fddaa0c bellard
    RET_PRIVOPC(ctx);
1932 9a64fbe4 bellard
#else
1933 9a64fbe4 bellard
    /* Restore CPU state */
1934 9a64fbe4 bellard
    if (!ctx->supervisor) {
1935 9fddaa0c bellard
        RET_PRIVOPC(ctx);
1936 9fddaa0c bellard
        return;
1937 9a64fbe4 bellard
    }
1938 9a64fbe4 bellard
    gen_op_rfi();
1939 2be0071f bellard
    RET_CHG_FLOW(ctx);
1940 9a64fbe4 bellard
#endif
1941 79aceca5 bellard
}
1942 79aceca5 bellard
1943 79aceca5 bellard
/* sc */
1944 79aceca5 bellard
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1945 79aceca5 bellard
{
1946 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1947 9fddaa0c bellard
    RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1948 9a64fbe4 bellard
#else
1949 9fddaa0c bellard
    RET_EXCP(ctx, EXCP_SYSCALL, 0);
1950 9a64fbe4 bellard
#endif
1951 79aceca5 bellard
}
1952 79aceca5 bellard
1953 79aceca5 bellard
/***                                Trap                                   ***/
1954 79aceca5 bellard
/* tw */
1955 79aceca5 bellard
GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1956 79aceca5 bellard
{
1957 9a64fbe4 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
1958 9a64fbe4 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));
1959 9a64fbe4 bellard
    gen_op_tw(TO(ctx->opcode));
1960 79aceca5 bellard
}
1961 79aceca5 bellard
1962 79aceca5 bellard
/* twi */
1963 79aceca5 bellard
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1964 79aceca5 bellard
{
1965 9a64fbe4 bellard
    gen_op_load_gpr_T0(rA(ctx->opcode));
1966 9a64fbe4 bellard
#if 0
1967 9a64fbe4 bellard
    printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1968 9a64fbe4 bellard
           SIMM(ctx->opcode), TO(ctx->opcode));
1969 9a64fbe4 bellard
#endif
1970 9a64fbe4 bellard
    gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1971 79aceca5 bellard
}
1972 79aceca5 bellard
1973 79aceca5 bellard
/***                          Processor control                            ***/
1974 79aceca5 bellard
static inline int check_spr_access (int spr, int rw, int supervisor)
1975 79aceca5 bellard
{
1976 79aceca5 bellard
    uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1977 79aceca5 bellard
1978 9a64fbe4 bellard
#if 0
1979 9a64fbe4 bellard
    if (spr != LR && spr != CTR) {
1980 9a64fbe4 bellard
    if (loglevel > 0) {
1981 9a64fbe4 bellard
        fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1982 9a64fbe4 bellard
                SPR_ENCODE(spr), supervisor, rw, rights,
1983 9a64fbe4 bellard
                (rights >> ((2 * supervisor) + rw)) & 1);
1984 9a64fbe4 bellard
    } else {
1985 9a64fbe4 bellard
        printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1986 9a64fbe4 bellard
               SPR_ENCODE(spr), supervisor, rw, rights,
1987 9a64fbe4 bellard
               (rights >> ((2 * supervisor) + rw)) & 1);
1988 9a64fbe4 bellard
    }
1989 9a64fbe4 bellard
    }
1990 9a64fbe4 bellard
#endif
1991 9a64fbe4 bellard
    if (rights == 0)
1992 9a64fbe4 bellard
        return -1;
1993 79aceca5 bellard
    rights = rights >> (2 * supervisor);
1994 79aceca5 bellard
    rights = rights >> rw;
1995 79aceca5 bellard
1996 79aceca5 bellard
    return rights & 1;
1997 79aceca5 bellard
}
1998 79aceca5 bellard
1999 79aceca5 bellard
/* mcrxr */
2000 79aceca5 bellard
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
2001 79aceca5 bellard
{
2002 79aceca5 bellard
    gen_op_load_xer_cr();
2003 79aceca5 bellard
    gen_op_store_T0_crf(crfD(ctx->opcode));
2004 79aceca5 bellard
    gen_op_clear_xer_cr();
2005 79aceca5 bellard
}
2006 79aceca5 bellard
2007 79aceca5 bellard
/* mfcr */
2008 79aceca5 bellard
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
2009 79aceca5 bellard
{
2010 79aceca5 bellard
    gen_op_load_cr();
2011 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
2012 79aceca5 bellard
}
2013 79aceca5 bellard
2014 79aceca5 bellard
/* mfmsr */
2015 79aceca5 bellard
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
2016 79aceca5 bellard
{
2017 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2018 9fddaa0c bellard
    RET_PRIVREG(ctx);
2019 9a64fbe4 bellard
#else
2020 9a64fbe4 bellard
    if (!ctx->supervisor) {
2021 9fddaa0c bellard
        RET_PRIVREG(ctx);
2022 9fddaa0c bellard
        return;
2023 9a64fbe4 bellard
    }
2024 79aceca5 bellard
    gen_op_load_msr();
2025 79aceca5 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
2026 9a64fbe4 bellard
#endif
2027 79aceca5 bellard
}
2028 79aceca5 bellard
2029 3fc6c082 bellard
#if 0
2030 3fc6c082 bellard
#define SPR_NOACCESS ((void *)(-1))
2031 3fc6c082 bellard
#else
2032 3fc6c082 bellard
static void spr_noaccess (void *opaque, int sprn)
2033 3fc6c082 bellard
{
2034 3fc6c082 bellard
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
2035 3fc6c082 bellard
    printf("ERROR: try to access SPR %d !\n", sprn);
2036 3fc6c082 bellard
}
2037 3fc6c082 bellard
#define SPR_NOACCESS (&spr_noaccess)
2038 3fc6c082 bellard
#endif
2039 3fc6c082 bellard
2040 79aceca5 bellard
/* mfspr */
2041 3fc6c082 bellard
static inline void gen_op_mfspr (DisasContext *ctx)
2042 79aceca5 bellard
{
2043 3fc6c082 bellard
    void (*read_cb)(void *opaque, int sprn);
2044 79aceca5 bellard
    uint32_t sprn = SPR(ctx->opcode);
2045 79aceca5 bellard
2046 3fc6c082 bellard
#if !defined(CONFIG_USER_ONLY)
2047 3fc6c082 bellard
    if (ctx->supervisor)
2048 3fc6c082 bellard
        read_cb = ctx->spr_cb[sprn].oea_read;
2049 3fc6c082 bellard
    else
2050 9a64fbe4 bellard
#endif
2051 3fc6c082 bellard
        read_cb = ctx->spr_cb[sprn].uea_read;
2052 3fc6c082 bellard
    if (read_cb != NULL) {
2053 3fc6c082 bellard
        if (read_cb != SPR_NOACCESS) {
2054 3fc6c082 bellard
            (*read_cb)(ctx, sprn);
2055 3fc6c082 bellard
            gen_op_store_T0_gpr(rD(ctx->opcode));
2056 3fc6c082 bellard
        } else {
2057 3fc6c082 bellard
            /* Privilege exception */
2058 f24e5695 bellard
            if (loglevel) {
2059 f24e5695 bellard
                fprintf(logfile, "Trying to read priviledged spr %d %03x\n",
2060 f24e5695 bellard
                        sprn, sprn);
2061 f24e5695 bellard
            }
2062 3fc6c082 bellard
            printf("Trying to read priviledged spr %d %03x\n", sprn, sprn);
2063 9fddaa0c bellard
        RET_PRIVREG(ctx);
2064 79aceca5 bellard
        }
2065 3fc6c082 bellard
    } else {
2066 3fc6c082 bellard
        /* Not defined */
2067 f24e5695 bellard
        if (loglevel) {
2068 f24e5695 bellard
            fprintf(logfile, "Trying to read invalid spr %d %03x\n",
2069 f24e5695 bellard
                    sprn, sprn);
2070 f24e5695 bellard
        }
2071 3fc6c082 bellard
        printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
2072 3fc6c082 bellard
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2073 79aceca5 bellard
    }
2074 79aceca5 bellard
}
2075 79aceca5 bellard
2076 3fc6c082 bellard
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
2077 79aceca5 bellard
{
2078 3fc6c082 bellard
    gen_op_mfspr(ctx);
2079 79aceca5 bellard
    }
2080 3fc6c082 bellard
2081 3fc6c082 bellard
/* mftb */
2082 3fc6c082 bellard
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_TB)
2083 3fc6c082 bellard
{
2084 3fc6c082 bellard
    gen_op_mfspr(ctx);
2085 79aceca5 bellard
}
2086 79aceca5 bellard
2087 79aceca5 bellard
/* mtcrf */
2088 8dd4983c bellard
/* The mask should be 0x00100801, but Mac OS X 10.4 use an alternate form */
2089 8dd4983c bellard
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
2090 79aceca5 bellard
{
2091 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2092 79aceca5 bellard
    gen_op_store_cr(CRM(ctx->opcode));
2093 79aceca5 bellard
}
2094 79aceca5 bellard
2095 79aceca5 bellard
/* mtmsr */
2096 79aceca5 bellard
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2097 79aceca5 bellard
{
2098 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2099 9fddaa0c bellard
    RET_PRIVREG(ctx);
2100 9a64fbe4 bellard
#else
2101 9a64fbe4 bellard
    if (!ctx->supervisor) {
2102 9fddaa0c bellard
        RET_PRIVREG(ctx);
2103 9fddaa0c bellard
        return;
2104 9a64fbe4 bellard
    }
2105 e80e1cc4 bellard
    gen_op_update_nip((ctx)->nip);
2106 79aceca5 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2107 79aceca5 bellard
    gen_op_store_msr();
2108 79aceca5 bellard
    /* Must stop the translation as machine state (may have) changed */
2109 e80e1cc4 bellard
    RET_CHG_FLOW(ctx);
2110 9a64fbe4 bellard
#endif
2111 79aceca5 bellard
}
2112 79aceca5 bellard
2113 79aceca5 bellard
/* mtspr */
2114 79aceca5 bellard
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2115 79aceca5 bellard
{
2116 3fc6c082 bellard
    void (*write_cb)(void *opaque, int sprn);
2117 79aceca5 bellard
    uint32_t sprn = SPR(ctx->opcode);
2118 79aceca5 bellard
2119 3fc6c082 bellard
#if !defined(CONFIG_USER_ONLY)
2120 3fc6c082 bellard
    if (ctx->supervisor)
2121 3fc6c082 bellard
        write_cb = ctx->spr_cb[sprn].oea_write;
2122 3fc6c082 bellard
    else
2123 9a64fbe4 bellard
#endif
2124 3fc6c082 bellard
        write_cb = ctx->spr_cb[sprn].uea_write;
2125 3fc6c082 bellard
    if (write_cb != NULL) {
2126 3fc6c082 bellard
        if (write_cb != SPR_NOACCESS) {
2127 3fc6c082 bellard
            gen_op_load_gpr_T0(rS(ctx->opcode));
2128 3fc6c082 bellard
            (*write_cb)(ctx, sprn);
2129 3fc6c082 bellard
        } else {
2130 3fc6c082 bellard
            /* Privilege exception */
2131 f24e5695 bellard
            if (loglevel) {
2132 f24e5695 bellard
                fprintf(logfile, "Trying to write priviledged spr %d %03x\n",
2133 f24e5695 bellard
                        sprn, sprn);
2134 f24e5695 bellard
            }
2135 3fc6c082 bellard
            printf("Trying to write priviledged spr %d %03x\n", sprn, sprn);
2136 9fddaa0c bellard
        RET_PRIVREG(ctx);
2137 9a64fbe4 bellard
    }
2138 3fc6c082 bellard
    } else {
2139 3fc6c082 bellard
        /* Not defined */
2140 f24e5695 bellard
        if (loglevel) {
2141 f24e5695 bellard
            fprintf(logfile, "Trying to write invalid spr %d %03x\n",
2142 f24e5695 bellard
                    sprn, sprn);
2143 f24e5695 bellard
        }
2144 3fc6c082 bellard
        printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
2145 3fc6c082 bellard
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2146 79aceca5 bellard
    }
2147 79aceca5 bellard
}
2148 79aceca5 bellard
2149 79aceca5 bellard
/***                         Cache management                              ***/
2150 79aceca5 bellard
/* For now, all those will be implemented as nop:
2151 79aceca5 bellard
 * this is valid, regarding the PowerPC specs...
2152 9a64fbe4 bellard
 * We just have to flush tb while invalidating instruction cache lines...
2153 79aceca5 bellard
 */
2154 79aceca5 bellard
/* dcbf */
2155 9a64fbe4 bellard
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2156 79aceca5 bellard
{
2157 a541f297 bellard
    if (rA(ctx->opcode) == 0) {
2158 a541f297 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
2159 a541f297 bellard
    } else {
2160 a541f297 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
2161 a541f297 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
2162 a541f297 bellard
        gen_op_add();
2163 a541f297 bellard
    }
2164 a541f297 bellard
    op_ldst(lbz);
2165 79aceca5 bellard
}
2166 79aceca5 bellard
2167 79aceca5 bellard
/* dcbi (Supervisor only) */
2168 9a64fbe4 bellard
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2169 79aceca5 bellard
{
2170 a541f297 bellard
#if defined(CONFIG_USER_ONLY)
2171 9fddaa0c bellard
    RET_PRIVOPC(ctx);
2172 a541f297 bellard
#else
2173 a541f297 bellard
    if (!ctx->supervisor) {
2174 9fddaa0c bellard
        RET_PRIVOPC(ctx);
2175 9fddaa0c bellard
        return;
2176 9a64fbe4 bellard
    }
2177 a541f297 bellard
    if (rA(ctx->opcode) == 0) {
2178 a541f297 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
2179 a541f297 bellard
    } else {
2180 a541f297 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
2181 a541f297 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
2182 a541f297 bellard
        gen_op_add();
2183 a541f297 bellard
    }
2184 a541f297 bellard
    op_ldst(lbz);
2185 a541f297 bellard
    op_ldst(stb);
2186 a541f297 bellard
#endif
2187 79aceca5 bellard
}
2188 79aceca5 bellard
2189 79aceca5 bellard
/* dcdst */
2190 9a64fbe4 bellard
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2191 79aceca5 bellard
{
2192 a541f297 bellard
    if (rA(ctx->opcode) == 0) {
2193 a541f297 bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
2194 a541f297 bellard
    } else {
2195 a541f297 bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
2196 a541f297 bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
2197 a541f297 bellard
        gen_op_add();
2198 a541f297 bellard
    }
2199 a541f297 bellard
    op_ldst(lbz);
2200 79aceca5 bellard
}
2201 79aceca5 bellard
2202 79aceca5 bellard
/* dcbt */
2203 9a64fbe4 bellard
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2204 79aceca5 bellard
{
2205 79aceca5 bellard
}
2206 79aceca5 bellard
2207 79aceca5 bellard
/* dcbtst */
2208 9a64fbe4 bellard
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2209 79aceca5 bellard
{
2210 79aceca5 bellard
}
2211 79aceca5 bellard
2212 79aceca5 bellard
/* dcbz */
2213 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2214 9a64fbe4 bellard
#define op_dcbz() gen_op_dcbz_raw()
2215 9a64fbe4 bellard
#else
2216 9a64fbe4 bellard
#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2217 9a64fbe4 bellard
static GenOpFunc *gen_op_dcbz[] = {
2218 9a64fbe4 bellard
    &gen_op_dcbz_user,
2219 2d5262f9 bellard
    &gen_op_dcbz_user,
2220 2d5262f9 bellard
    &gen_op_dcbz_kernel,
2221 9a64fbe4 bellard
    &gen_op_dcbz_kernel,
2222 9a64fbe4 bellard
};
2223 9a64fbe4 bellard
#endif
2224 9a64fbe4 bellard
2225 9a64fbe4 bellard
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2226 79aceca5 bellard
{
2227 fb0eaffc bellard
    if (rA(ctx->opcode) == 0) {
2228 fb0eaffc bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
2229 fb0eaffc bellard
    } else {
2230 fb0eaffc bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
2231 fb0eaffc bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
2232 9a64fbe4 bellard
        gen_op_add();
2233 fb0eaffc bellard
    }
2234 9a64fbe4 bellard
    op_dcbz();
2235 4b3686fa bellard
    gen_op_check_reservation();
2236 79aceca5 bellard
}
2237 79aceca5 bellard
2238 79aceca5 bellard
/* icbi */
2239 9a64fbe4 bellard
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2240 79aceca5 bellard
{
2241 fb0eaffc bellard
    if (rA(ctx->opcode) == 0) {
2242 fb0eaffc bellard
        gen_op_load_gpr_T0(rB(ctx->opcode));
2243 fb0eaffc bellard
    } else {
2244 fb0eaffc bellard
        gen_op_load_gpr_T0(rA(ctx->opcode));
2245 fb0eaffc bellard
        gen_op_load_gpr_T1(rB(ctx->opcode));
2246 9a64fbe4 bellard
        gen_op_add();
2247 fb0eaffc bellard
    }
2248 9a64fbe4 bellard
    gen_op_icbi();
2249 79aceca5 bellard
}
2250 79aceca5 bellard
2251 79aceca5 bellard
/* Optional: */
2252 79aceca5 bellard
/* dcba */
2253 c7d344af bellard
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
2254 79aceca5 bellard
{
2255 79aceca5 bellard
}
2256 79aceca5 bellard
2257 79aceca5 bellard
/***                    Segment register manipulation                      ***/
2258 79aceca5 bellard
/* Supervisor only: */
2259 79aceca5 bellard
/* mfsr */
2260 79aceca5 bellard
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2261 79aceca5 bellard
{
2262 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2263 9fddaa0c bellard
    RET_PRIVREG(ctx);
2264 9a64fbe4 bellard
#else
2265 9a64fbe4 bellard
    if (!ctx->supervisor) {
2266 9fddaa0c bellard
        RET_PRIVREG(ctx);
2267 9fddaa0c bellard
        return;
2268 9a64fbe4 bellard
    }
2269 9a64fbe4 bellard
    gen_op_load_sr(SR(ctx->opcode));
2270 9a64fbe4 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
2271 9a64fbe4 bellard
#endif
2272 79aceca5 bellard
}
2273 79aceca5 bellard
2274 79aceca5 bellard
/* mfsrin */
2275 9a64fbe4 bellard
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2276 79aceca5 bellard
{
2277 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2278 9fddaa0c bellard
    RET_PRIVREG(ctx);
2279 9a64fbe4 bellard
#else
2280 9a64fbe4 bellard
    if (!ctx->supervisor) {
2281 9fddaa0c bellard
        RET_PRIVREG(ctx);
2282 9fddaa0c bellard
        return;
2283 9a64fbe4 bellard
    }
2284 9a64fbe4 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));
2285 9a64fbe4 bellard
    gen_op_load_srin();
2286 9a64fbe4 bellard
    gen_op_store_T0_gpr(rD(ctx->opcode));
2287 9a64fbe4 bellard
#endif
2288 79aceca5 bellard
}
2289 79aceca5 bellard
2290 79aceca5 bellard
/* mtsr */
2291 e63c59cb bellard
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
2292 79aceca5 bellard
{
2293 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2294 9fddaa0c bellard
    RET_PRIVREG(ctx);
2295 9a64fbe4 bellard
#else
2296 9a64fbe4 bellard
    if (!ctx->supervisor) {
2297 9fddaa0c bellard
        RET_PRIVREG(ctx);
2298 9fddaa0c bellard
        return;
2299 9a64fbe4 bellard
    }
2300 9a64fbe4 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2301 9a64fbe4 bellard
    gen_op_store_sr(SR(ctx->opcode));
2302 f24e5695 bellard
    RET_STOP(ctx);
2303 9a64fbe4 bellard
#endif
2304 79aceca5 bellard
}
2305 79aceca5 bellard
2306 79aceca5 bellard
/* mtsrin */
2307 9a64fbe4 bellard
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
2308 79aceca5 bellard
{
2309 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2310 9fddaa0c bellard
    RET_PRIVREG(ctx);
2311 9a64fbe4 bellard
#else
2312 9a64fbe4 bellard
    if (!ctx->supervisor) {
2313 9fddaa0c bellard
        RET_PRIVREG(ctx);
2314 9fddaa0c bellard
        return;
2315 9a64fbe4 bellard
    }
2316 9a64fbe4 bellard
    gen_op_load_gpr_T0(rS(ctx->opcode));
2317 9a64fbe4 bellard
    gen_op_load_gpr_T1(rB(ctx->opcode));
2318 9a64fbe4 bellard
    gen_op_store_srin();
2319 f24e5695 bellard
    RET_STOP(ctx);
2320 9a64fbe4 bellard
#endif
2321 79aceca5 bellard
}
2322 79aceca5 bellard
2323 79aceca5 bellard
/***                      Lookaside buffer management                      ***/
2324 79aceca5 bellard
/* Optional & supervisor only: */
2325 79aceca5 bellard
/* tlbia */
2326 3fc6c082 bellard
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
2327 79aceca5 bellard
{
2328 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
2329 9fddaa0c bellard
    RET_PRIVOPC(ctx);
2330 9a64fbe4 bellard
#else