Archipelago » qemu

/*

 *  PowerPC emulation for qemu: main translation routines.

 * 

 *  Copyright (c) 2003-2005 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

//#define DO_SINGLE_STEP

//#define PPC_DEBUG_DISAS

#ifdef USE_DIRECT_JUMP

#define TBPARAM(x)

#else

#define TBPARAM(x) (long)(x)

#endif

enum {

#define DEF(s, n, copy_size) INDEX_op_ ## s,

#include "opc.h"

#undef DEF

    NB_OPS,

};

static uint16_t *gen_opc_ptr;

static uint32_t *gen_opparam_ptr;

#include "gen-op.h"

#define GEN8(func, NAME) \

static GenOpFunc *NAME ## _table [8] = {                                      \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

};                                                                            \

static inline void func(int n)                                                \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

#define GEN16(func, NAME)                                                     \

static GenOpFunc *NAME ## _table [16] = {                                     \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

};                                                                            \

static inline void func(int n)                                                \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

#define GEN32(func, NAME) \

static GenOpFunc *NAME ## _table [32] = {                                     \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \

NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \

NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \

NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \

};                                                                            \

static inline void func(int n)                                                \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

/* Condition register moves */

GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);

GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);

GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);

GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);

/* Floating point condition and status register moves */

GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);

GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);

GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);

static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {

    &gen_op_store_T0_fpscri_fpscr0,

    &gen_op_store_T0_fpscri_fpscr1,

    &gen_op_store_T0_fpscri_fpscr2,

    &gen_op_store_T0_fpscri_fpscr3,

    &gen_op_store_T0_fpscri_fpscr4,

    &gen_op_store_T0_fpscri_fpscr5,

    &gen_op_store_T0_fpscri_fpscr6,

    &gen_op_store_T0_fpscri_fpscr7,

};

static inline void gen_op_store_T0_fpscri(int n, uint8_t param)

{

    (*gen_op_store_T0_fpscri_fpscr_table[n])(param);

}

/* Segment register moves */

GEN16(gen_op_load_sr, gen_op_load_sr);

GEN16(gen_op_store_sr, gen_op_store_sr);

/* General purpose registers moves */

GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);

GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);

GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);

GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);

GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);

GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);

/* floating point registers moves */

GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);

GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);

GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);

GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);

GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);

GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);

static uint8_t  spr_access[1024 / 2];

/* internal defines */

typedef struct DisasContext {

    struct TranslationBlock *tb;

    target_ulong nip;

    uint32_t opcode;

    uint32_t exception;

    /* Routine used to access memory */

    int mem_idx;

    /* Translation flags */

#if !defined(CONFIG_USER_ONLY)

    int supervisor;

#endif

    int fpu_enabled;

    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */

    int singlestep_enabled;

} DisasContext;

struct opc_handler_t {

    /* invalid bits */

    uint32_t inval;

    /* instruction type */

    uint32_t type;

    /* handler */

    void (*handler)(DisasContext *ctx);

};

#define RET_EXCP(ctx, excp, error)                                            \

do {                                                                          \

    if ((ctx)->exception == EXCP_NONE) {                                      \

        gen_op_update_nip((ctx)->nip);                                        \

    }                                                                         \

    gen_op_raise_exception_err((excp), (error));                              \

    ctx->exception = (excp);                                                  \

} while (0)

#define RET_INVAL(ctx)                                                        \

RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)

#define RET_PRIVOPC(ctx)                                                      \

RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)

#define RET_PRIVREG(ctx)                                                      \

RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)

/* Stop translation */

static inline void RET_STOP (DisasContext *ctx)

{

    gen_op_update_nip((ctx)->nip);

    ctx->exception = EXCP_MTMSR;

}

/* No need to update nip here, as execution flow will change */

static inline void RET_CHG_FLOW (DisasContext *ctx)

{

    ctx->exception = EXCP_MTMSR;

}

#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \

static void gen_##name (DisasContext *ctx);                                   \

GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \

static void gen_##name (DisasContext *ctx)

typedef struct opcode_t {

    unsigned char opc1, opc2, opc3;

#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */

    unsigned char pad[5];

#else

    unsigned char pad[1];

#endif

    opc_handler_t handler;

    const unsigned char *oname;

} opcode_t;

/***                           Instruction decoding                        ***/

#define EXTRACT_HELPER(name, shift, nb)                                       \

static inline uint32_t name (uint32_t opcode)                                 \

{                                                                             \

    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \

}

#define EXTRACT_SHELPER(name, shift, nb)                                      \

static inline int32_t name (uint32_t opcode)                                  \

{                                                                             \

    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \

}

/* Opcode part 1 */

EXTRACT_HELPER(opc1, 26, 6);

/* Opcode part 2 */

EXTRACT_HELPER(opc2, 1, 5);

/* Opcode part 3 */

EXTRACT_HELPER(opc3, 6, 5);

/* Update Cr0 flags */

EXTRACT_HELPER(Rc, 0, 1);

/* Destination */

EXTRACT_HELPER(rD, 21, 5);

/* Source */

EXTRACT_HELPER(rS, 21, 5);

/* First operand */

EXTRACT_HELPER(rA, 16, 5);

/* Second operand */

EXTRACT_HELPER(rB, 11, 5);

/* Third operand */

EXTRACT_HELPER(rC, 6, 5);

/***                               Get CRn                                 ***/

EXTRACT_HELPER(crfD, 23, 3);

EXTRACT_HELPER(crfS, 18, 3);

EXTRACT_HELPER(crbD, 21, 5);

EXTRACT_HELPER(crbA, 16, 5);

EXTRACT_HELPER(crbB, 11, 5);

/* SPR / TBL */

EXTRACT_HELPER(_SPR, 11, 10);

static inline uint32_t SPR (uint32_t opcode)

{

    uint32_t sprn = _SPR(opcode);

    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);

}

/***                              Get constants                            ***/

EXTRACT_HELPER(IMM, 12, 8);

/* 16 bits signed immediate value */

EXTRACT_SHELPER(SIMM, 0, 16);

/* 16 bits unsigned immediate value */

EXTRACT_HELPER(UIMM, 0, 16);

/* Bit count */

EXTRACT_HELPER(NB, 11, 5);

/* Shift count */

EXTRACT_HELPER(SH, 11, 5);

/* Mask start */

EXTRACT_HELPER(MB, 6, 5);

/* Mask end */

EXTRACT_HELPER(ME, 1, 5);

/* Trap operand */

EXTRACT_HELPER(TO, 21, 5);

EXTRACT_HELPER(CRM, 12, 8);

EXTRACT_HELPER(FM, 17, 8);

EXTRACT_HELPER(SR, 16, 4);

EXTRACT_HELPER(FPIMM, 20, 4);

/***                            Jump target decoding                       ***/

/* Displacement */

EXTRACT_SHELPER(d, 0, 16);

/* Immediate address */

static inline uint32_t LI (uint32_t opcode)

{

    return (opcode >> 0) & 0x03FFFFFC;

}

static inline uint32_t BD (uint32_t opcode)

{

    return (opcode >> 0) & 0xFFFC;

}

EXTRACT_HELPER(BO, 21, 5);

EXTRACT_HELPER(BI, 16, 5);

/* Absolute/relative address */

EXTRACT_HELPER(AA, 1, 1);

/* Link */

EXTRACT_HELPER(LK, 0, 1);

/* Create a mask between <start> and <end> bits */

static inline uint32_t MASK (uint32_t start, uint32_t end)

{

    uint32_t ret;

    ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);

    if (start > end)

        return ~ret;

    return ret;

}

#if HOST_LONG_BITS == 64

#define OPC_ALIGN 8

#else

#define OPC_ALIGN 4

#endif

#if defined(__APPLE__)

#define OPCODES_SECTION \

    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))

#else

#define OPCODES_SECTION \

    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))

#endif

#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE_MARK(name)                                                 \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = 0xFF,                                                             \

    .opc2 = 0xFF,                                                             \

    .opc3 = 0xFF,                                                             \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = 0x00000000,                                                \

        .type = 0x00,                                                         \

        .handler = NULL,                                                      \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

/* Start opcode list */

GEN_OPCODE_MARK(start);

/* Invalid instruction */

GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)

{

    RET_INVAL(ctx);

}

static opc_handler_t invalid_handler = {

    .inval   = 0xFFFFFFFF,

    .type    = PPC_NONE,

    .handler = gen_invalid,

};

/***                           Integer arithmetic                          ***/

#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval)                       \

GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    if (Rc(ctx->opcode) != 0)                                                 \

        gen_op_set_Rc0();                                                     \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

}

#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval)                     \

GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    if (Rc(ctx->opcode) != 0)                                                 \

        gen_op_set_Rc0();                                                     \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

}

#define __GEN_INT_ARITH1(name, opc1, opc2, opc3)                              \

GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    if (Rc(ctx->opcode) != 0)                                                 \

        gen_op_set_Rc0();                                                     \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

}

#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3)                            \

GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    if (Rc(ctx->opcode) != 0)                                                 \

        gen_op_set_Rc0();                                                     \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

}

/* Two operands arithmetic functions */

#define GEN_INT_ARITH2(name, opc1, opc2, opc3)                                \

__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000)                          \

__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)

/* Two operands arithmetic functions with no overflow allowed */

#define GEN_INT_ARITHN(name, opc1, opc2, opc3)                                \

__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)

/* One operand arithmetic functions */

#define GEN_INT_ARITH1(name, opc1, opc2, opc3)                                \

__GEN_INT_ARITH1(name, opc1, opc2, opc3)                                      \

__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)

/* add    add.    addo    addo.    */

GEN_INT_ARITH2 (add,    0x1F, 0x0A, 0x08);

/* addc   addc.   addco   addco.   */

GEN_INT_ARITH2 (addc,   0x1F, 0x0A, 0x00);

/* adde   adde.   addeo   addeo.   */

GEN_INT_ARITH2 (adde,   0x1F, 0x0A, 0x04);

/* addme  addme.  addmeo  addmeo.  */

GEN_INT_ARITH1 (addme,  0x1F, 0x0A, 0x07);

/* addze  addze.  addzeo  addzeo.  */

GEN_INT_ARITH1 (addze,  0x1F, 0x0A, 0x06);

/* divw   divw.   divwo   divwo.   */

GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F);

/* divwu  divwu.  divwuo  divwuo.  */

GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E);

/* mulhw  mulhw.                   */

GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02);

/* mulhwu mulhwu.                  */

GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);

/* mullw  mullw.  mullwo  mullwo.  */

GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07);

/* neg    neg.    nego    nego.    */

GEN_INT_ARITH1 (neg,    0x1F, 0x08, 0x03);

/* subf   subf.   subfo   subfo.   */

GEN_INT_ARITH2 (subf,   0x1F, 0x08, 0x01);

/* subfc  subfc.  subfco  subfco.  */

GEN_INT_ARITH2 (subfc,  0x1F, 0x08, 0x00);

/* subfe  subfe.  subfeo  subfeo.  */

GEN_INT_ARITH2 (subfe,  0x1F, 0x08, 0x04);

/* subfme subfme. subfmeo subfmeo. */

GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);

/* subfze subfze. subfzeo subfzeo. */

GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);

/* addi */

GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    int32_t simm = SIMM(ctx->opcode);

    if (rA(ctx->opcode) == 0) {

        gen_op_set_T0(simm);

    } else {

        gen_op_load_gpr_T0(rA(ctx->opcode));

        gen_op_addi(simm);

    }

    gen_op_store_T0_gpr(rD(ctx->opcode));

}

/* addic */

GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rA(ctx->opcode));

    gen_op_addic(SIMM(ctx->opcode));

    gen_op_store_T0_gpr(rD(ctx->opcode));

}

/* addic. */

GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rA(ctx->opcode));

    gen_op_addic(SIMM(ctx->opcode));

    gen_op_set_Rc0();

    gen_op_store_T0_gpr(rD(ctx->opcode));

}

/* addis */

GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    int32_t simm = SIMM(ctx->opcode);

    if (rA(ctx->opcode) == 0) {

        gen_op_set_T0(simm << 16);

    } else {

        gen_op_load_gpr_T0(rA(ctx->opcode));

        gen_op_addi(simm << 16);

    }

    gen_op_store_T0_gpr(rD(ctx->opcode));

}

/* mulli */

GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rA(ctx->opcode));

    gen_op_mulli(SIMM(ctx->opcode));

    gen_op_store_T0_gpr(rD(ctx->opcode));

}

/* subfic */

GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rA(ctx->opcode));

    gen_op_subfic(SIMM(ctx->opcode));

    gen_op_store_T0_gpr(rD(ctx->opcode));

}

/***                           Integer comparison                          ***/

#define GEN_CMP(name, opc)                                                    \

GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER)                   \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \

}

/* cmp */

GEN_CMP(cmp, 0x00);

/* cmpi */

GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rA(ctx->opcode));

    gen_op_cmpi(SIMM(ctx->opcode));

    gen_op_store_T0_crf(crfD(ctx->opcode));

}

/* cmpl */

GEN_CMP(cmpl, 0x01);

/* cmpli */

GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rA(ctx->opcode));

    gen_op_cmpli(UIMM(ctx->opcode));

    gen_op_store_T0_crf(crfD(ctx->opcode));

}

/***                            Integer logical                            ***/

#define __GEN_LOGICAL2(name, opc2, opc3)                                      \

GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER)                  \

{                                                                             \

    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \

    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    if (Rc(ctx->opcode) != 0)                                                 \

        gen_op_set_Rc0();                                                     \

    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \

}

#define GEN_LOGICAL2(name, opc)                                               \

__GEN_LOGICAL2(name, 0x1C, opc)

#define GEN_LOGICAL1(name, opc)                                               \

GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER)                   \

{                                                                             \

    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    if (Rc(ctx->opcode) != 0)                                                 \

        gen_op_set_Rc0();                                                     \

    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \

}

/* and & and. */

GEN_LOGICAL2(and, 0x00);

/* andc & andc. */

GEN_LOGICAL2(andc, 0x01);

/* andi. */

GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rS(ctx->opcode));

    gen_op_andi_(UIMM(ctx->opcode));

    gen_op_set_Rc0();

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* andis. */

GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rS(ctx->opcode));

    gen_op_andi_(UIMM(ctx->opcode) << 16);

    gen_op_set_Rc0();

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* cntlzw */

GEN_LOGICAL1(cntlzw, 0x00);

/* eqv & eqv. */

GEN_LOGICAL2(eqv, 0x08);

/* extsb & extsb. */

GEN_LOGICAL1(extsb, 0x1D);

/* extsh & extsh. */

GEN_LOGICAL1(extsh, 0x1C);

/* nand & nand. */

GEN_LOGICAL2(nand, 0x0E);

/* nor & nor. */

GEN_LOGICAL2(nor, 0x03);

/* or & or. */

GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rS(ctx->opcode));

    /* Optimisation for mr case */

    if (rS(ctx->opcode) != rB(ctx->opcode)) {

        gen_op_load_gpr_T1(rB(ctx->opcode));

        gen_op_or();

    }

    if (Rc(ctx->opcode) != 0)

        gen_op_set_Rc0();

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* orc & orc. */

GEN_LOGICAL2(orc, 0x0C);

/* xor & xor. */

GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rS(ctx->opcode));

    /* Optimisation for "set to zero" case */

    if (rS(ctx->opcode) != rB(ctx->opcode)) {

        gen_op_load_gpr_T1(rB(ctx->opcode));

        gen_op_xor();

    } else {

        gen_op_set_T0(0);

    }

    if (Rc(ctx->opcode) != 0)

        gen_op_set_Rc0();

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* ori */

GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    uint32_t uimm = UIMM(ctx->opcode);

    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {

        /* NOP */

        return;

        }

        gen_op_load_gpr_T0(rS(ctx->opcode));

    if (uimm != 0)

        gen_op_ori(uimm);

        gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* oris */

GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    uint32_t uimm = UIMM(ctx->opcode);

    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {

        /* NOP */

        return;

        }

        gen_op_load_gpr_T0(rS(ctx->opcode));

    if (uimm != 0)

        gen_op_ori(uimm << 16);

        gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* xori */

GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    uint32_t uimm = UIMM(ctx->opcode);

    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {

        /* NOP */

        return;

    }

    gen_op_load_gpr_T0(rS(ctx->opcode));

    if (uimm != 0)

    gen_op_xori(uimm);

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* xoris */

GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    uint32_t uimm = UIMM(ctx->opcode);

    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {

        /* NOP */

        return;

    }

    gen_op_load_gpr_T0(rS(ctx->opcode));

    if (uimm != 0)

    gen_op_xori(uimm << 16);

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/***                             Integer rotate                            ***/

/* rlwimi & rlwimi. */

GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    uint32_t mb, me;

    mb = MB(ctx->opcode);

    me = ME(ctx->opcode);

    gen_op_load_gpr_T0(rS(ctx->opcode));

    gen_op_load_gpr_T1(rA(ctx->opcode));

    gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));

    if (Rc(ctx->opcode) != 0)

        gen_op_set_Rc0();

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* rlwinm & rlwinm. */

GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    uint32_t mb, me, sh;

    sh = SH(ctx->opcode);

    mb = MB(ctx->opcode);

    me = ME(ctx->opcode);

    gen_op_load_gpr_T0(rS(ctx->opcode));

#if 1 // TRY

    if (sh == 0) {

        gen_op_andi_(MASK(mb, me));

        goto store;

    }

#endif

    if (mb == 0) {

        if (me == 31) {

            gen_op_rotlwi(sh);

            goto store;

#if 0

        } else if (me == (31 - sh)) {

            gen_op_slwi(sh);

            goto store;

#endif

        }

    } else if (me == 31) {

#if 0

        if (sh == (32 - mb)) {

            gen_op_srwi(mb);

            goto store;

        }

#endif

    }

    gen_op_rlwinm(sh, MASK(mb, me));

store:

    if (Rc(ctx->opcode) != 0)

        gen_op_set_Rc0();

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* rlwnm & rlwnm. */

GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

{

    uint32_t mb, me;

    mb = MB(ctx->opcode);

    me = ME(ctx->opcode);

    gen_op_load_gpr_T0(rS(ctx->opcode));

    gen_op_load_gpr_T1(rB(ctx->opcode));

    if (mb == 0 && me == 31) {

        gen_op_rotl();

    } else

    {

        gen_op_rlwnm(MASK(mb, me));

    }

    if (Rc(ctx->opcode) != 0)

        gen_op_set_Rc0();

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/***                             Integer shift                             ***/

/* slw & slw. */

__GEN_LOGICAL2(slw, 0x18, 0x00);

/* sraw & sraw. */

__GEN_LOGICAL2(sraw, 0x18, 0x18);

/* srawi & srawi. */

GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)

{

    gen_op_load_gpr_T0(rS(ctx->opcode));

    if (SH(ctx->opcode) != 0)

    gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));

    if (Rc(ctx->opcode) != 0)

        gen_op_set_Rc0();

    gen_op_store_T0_gpr(rA(ctx->opcode));

}

/* srw & srw. */

__GEN_LOGICAL2(srw, 0x18, 0x10);

/***                       Floating-Point arithmetic                       ***/

#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat)                           \

GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT)                   \

{                                                                             \

    if (!ctx->fpu_enabled) {                                                  \

        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \

        return;                                                               \

    }                                                                         \

    gen_op_reset_scrfx();                                                     \

    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \

    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \

    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \

    gen_op_f##op();                                                           \

    if (isfloat) {                                                            \

        gen_op_frsp();                                                        \

    }                                                                         \

    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \

    if (Rc(ctx->opcode))                                                      \

        gen_op_set_Rc1();                                                     \

}

#define GEN_FLOAT_ACB(name, op2)                                              \

_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0);                                     \

_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);

#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat)                     \

GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \

{                                                                             \

    if (!ctx->fpu_enabled) {                                                  \

        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \

        return;                                                               \

    }                                                                         \

    gen_op_reset_scrfx();                                                     \

    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \

    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \

    gen_op_f##op();                                                           \

    if (isfloat) {                                                            \

        gen_op_frsp();                                                        \

    }                                                                         \

    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \

    if (Rc(ctx->opcode))                                                      \

        gen_op_set_Rc1();                                                     \

}

#define GEN_FLOAT_AB(name, op2, inval)                                        \

_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0);                               \

_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);

#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat)                     \

GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \

{                                                                             \

    if (!ctx->fpu_enabled) {                                                  \

        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \

        return;                                                               \

    }                                                                         \

    gen_op_reset_scrfx();                                                     \

    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \

    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \

    gen_op_f##op();                                                           \

    if (isfloat) {                                                            \

        gen_op_frsp();                                                        \

    }                                                                         \

    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \

    if (Rc(ctx->opcode))                                                      \

        gen_op_set_Rc1();                                                     \

}

#define GEN_FLOAT_AC(name, op2, inval)                                        \

_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0);                               \

_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);

#define GEN_FLOAT_B(name, op2, op3)                                           \

GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT)                   \

{                                                                             \

    if (!ctx->fpu_enabled) {                                                  \

        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \

        return;                                                               \

    }                                                                         \

    gen_op_reset_scrfx();                                                     \

    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \

    gen_op_f##name();                                                         \

    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \

    if (Rc(ctx->opcode))                                                      \

        gen_op_set_Rc1();                                                     \

}

#define GEN_FLOAT_BS(name, op1, op2)                                          \

GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT)                   \

{                                                                             \

    if (!ctx->fpu_enabled) {                                                  \

        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \

        return;                                                               \

    }                                                                         \

    gen_op_reset_scrfx();                                                     \

    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \

    gen_op_f##name();                                                         \

    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \

    if (Rc(ctx->opcode))                                                      \

        gen_op_set_Rc1();                                                     \

}

/* fadd - fadds */

GEN_FLOAT_AB(add, 0x15, 0x000007C0);

/* fdiv - fdivs */

GEN_FLOAT_AB(div, 0x12, 0x000007C0);

/* fmul - fmuls */