root / target-ppc / translate_init.c @ 26a76461
History | View | Annotate | Download (59.1 kB)
1 | 3fc6c082 | bellard | /*
|
---|---|---|---|
2 | 3fc6c082 | bellard | * PowerPC CPU initialization for qemu.
|
3 | 3fc6c082 | bellard | *
|
4 | 3fc6c082 | bellard | * Copyright (c) 2003-2005 Jocelyn Mayer
|
5 | 3fc6c082 | bellard | *
|
6 | 3fc6c082 | bellard | * This library is free software; you can redistribute it and/or
|
7 | 3fc6c082 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 3fc6c082 | bellard | * License as published by the Free Software Foundation; either
|
9 | 3fc6c082 | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 3fc6c082 | bellard | *
|
11 | 3fc6c082 | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 3fc6c082 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 3fc6c082 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 3fc6c082 | bellard | * Lesser General Public License for more details.
|
15 | 3fc6c082 | bellard | *
|
16 | 3fc6c082 | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 3fc6c082 | bellard | * License along with this library; if not, write to the Free Software
|
18 | 3fc6c082 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 3fc6c082 | bellard | */
|
20 | 3fc6c082 | bellard | |
21 | 3fc6c082 | bellard | /* A lot of PowerPC definition have been included here.
|
22 | 3fc6c082 | bellard | * Most of them are not usable for now but have been kept
|
23 | 3fc6c082 | bellard | * inside "#if defined(TODO) ... #endif" statements to make tests easier.
|
24 | 3fc6c082 | bellard | */
|
25 | 3fc6c082 | bellard | |
26 | 3fc6c082 | bellard | //#define PPC_DUMP_CPU
|
27 | 3fc6c082 | bellard | //#define PPC_DEBUG_SPR
|
28 | 3fc6c082 | bellard | |
29 | 3fc6c082 | bellard | struct ppc_def_t {
|
30 | 3fc6c082 | bellard | const unsigned char *name; |
31 | 3fc6c082 | bellard | uint32_t pvr; |
32 | 3fc6c082 | bellard | uint32_t pvr_mask; |
33 | 3fc6c082 | bellard | uint32_t insns_flags; |
34 | 3fc6c082 | bellard | uint32_t flags; |
35 | 3fc6c082 | bellard | uint64_t msr_mask; |
36 | 3fc6c082 | bellard | }; |
37 | 3fc6c082 | bellard | |
38 | 3fc6c082 | bellard | /* Generic callbacks:
|
39 | 3fc6c082 | bellard | * do nothing but store/retrieve spr value
|
40 | 3fc6c082 | bellard | */
|
41 | 3fc6c082 | bellard | static void spr_read_generic (void *opaque, int sprn) |
42 | 3fc6c082 | bellard | { |
43 | 3fc6c082 | bellard | gen_op_load_spr(sprn); |
44 | 3fc6c082 | bellard | } |
45 | 3fc6c082 | bellard | |
46 | 3fc6c082 | bellard | static void spr_write_generic (void *opaque, int sprn) |
47 | 3fc6c082 | bellard | { |
48 | 3fc6c082 | bellard | gen_op_store_spr(sprn); |
49 | 3fc6c082 | bellard | } |
50 | 3fc6c082 | bellard | |
51 | 3fc6c082 | bellard | /* SPR common to all PPC */
|
52 | 3fc6c082 | bellard | /* XER */
|
53 | 3fc6c082 | bellard | static void spr_read_xer (void *opaque, int sprn) |
54 | 3fc6c082 | bellard | { |
55 | 3fc6c082 | bellard | gen_op_load_xer(); |
56 | 3fc6c082 | bellard | } |
57 | 3fc6c082 | bellard | |
58 | 3fc6c082 | bellard | static void spr_write_xer (void *opaque, int sprn) |
59 | 3fc6c082 | bellard | { |
60 | 3fc6c082 | bellard | gen_op_store_xer(); |
61 | 3fc6c082 | bellard | } |
62 | 3fc6c082 | bellard | |
63 | 3fc6c082 | bellard | /* LR */
|
64 | 3fc6c082 | bellard | static void spr_read_lr (void *opaque, int sprn) |
65 | 3fc6c082 | bellard | { |
66 | 3fc6c082 | bellard | gen_op_load_lr(); |
67 | 3fc6c082 | bellard | } |
68 | 3fc6c082 | bellard | |
69 | 3fc6c082 | bellard | static void spr_write_lr (void *opaque, int sprn) |
70 | 3fc6c082 | bellard | { |
71 | 3fc6c082 | bellard | gen_op_store_lr(); |
72 | 3fc6c082 | bellard | } |
73 | 3fc6c082 | bellard | |
74 | 3fc6c082 | bellard | /* CTR */
|
75 | 3fc6c082 | bellard | static void spr_read_ctr (void *opaque, int sprn) |
76 | 3fc6c082 | bellard | { |
77 | 3fc6c082 | bellard | gen_op_load_ctr(); |
78 | 3fc6c082 | bellard | } |
79 | 3fc6c082 | bellard | |
80 | 3fc6c082 | bellard | static void spr_write_ctr (void *opaque, int sprn) |
81 | 3fc6c082 | bellard | { |
82 | 3fc6c082 | bellard | gen_op_store_ctr(); |
83 | 3fc6c082 | bellard | } |
84 | 3fc6c082 | bellard | |
85 | 3fc6c082 | bellard | /* User read access to SPR */
|
86 | 3fc6c082 | bellard | /* USPRx */
|
87 | 3fc6c082 | bellard | /* UMMCRx */
|
88 | 3fc6c082 | bellard | /* UPMCx */
|
89 | 3fc6c082 | bellard | /* USIA */
|
90 | 3fc6c082 | bellard | /* UDECR */
|
91 | 3fc6c082 | bellard | static void spr_read_ureg (void *opaque, int sprn) |
92 | 3fc6c082 | bellard | { |
93 | 3fc6c082 | bellard | gen_op_load_spr(sprn + 0x10);
|
94 | 3fc6c082 | bellard | } |
95 | 3fc6c082 | bellard | |
96 | 3fc6c082 | bellard | /* SPR common to all non-embedded PPC (ie not 4xx) */
|
97 | 3fc6c082 | bellard | /* DECR */
|
98 | 3fc6c082 | bellard | static void spr_read_decr (void *opaque, int sprn) |
99 | 3fc6c082 | bellard | { |
100 | 3fc6c082 | bellard | gen_op_load_decr(); |
101 | 3fc6c082 | bellard | } |
102 | 3fc6c082 | bellard | |
103 | 3fc6c082 | bellard | static void spr_write_decr (void *opaque, int sprn) |
104 | 3fc6c082 | bellard | { |
105 | 3fc6c082 | bellard | gen_op_store_decr(); |
106 | 3fc6c082 | bellard | } |
107 | 3fc6c082 | bellard | |
108 | 3fc6c082 | bellard | /* SPR common to all non-embedded PPC, except 601 */
|
109 | 3fc6c082 | bellard | /* Time base */
|
110 | 3fc6c082 | bellard | static void spr_read_tbl (void *opaque, int sprn) |
111 | 3fc6c082 | bellard | { |
112 | 3fc6c082 | bellard | gen_op_load_tbl(); |
113 | 3fc6c082 | bellard | } |
114 | 3fc6c082 | bellard | |
115 | 3fc6c082 | bellard | static void spr_write_tbl (void *opaque, int sprn) |
116 | 3fc6c082 | bellard | { |
117 | 3fc6c082 | bellard | gen_op_store_tbl(); |
118 | 3fc6c082 | bellard | } |
119 | 3fc6c082 | bellard | |
120 | 3fc6c082 | bellard | static void spr_read_tbu (void *opaque, int sprn) |
121 | 3fc6c082 | bellard | { |
122 | 3fc6c082 | bellard | gen_op_load_tbu(); |
123 | 3fc6c082 | bellard | } |
124 | 3fc6c082 | bellard | |
125 | 3fc6c082 | bellard | static void spr_write_tbu (void *opaque, int sprn) |
126 | 3fc6c082 | bellard | { |
127 | 3fc6c082 | bellard | gen_op_store_tbu(); |
128 | 3fc6c082 | bellard | } |
129 | 3fc6c082 | bellard | |
130 | 3fc6c082 | bellard | /* IBAT0U...IBAT0U */
|
131 | 3fc6c082 | bellard | /* IBAT0L...IBAT7L */
|
132 | 3fc6c082 | bellard | static void spr_read_ibat (void *opaque, int sprn) |
133 | 3fc6c082 | bellard | { |
134 | 3fc6c082 | bellard | gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2); |
135 | 3fc6c082 | bellard | } |
136 | 3fc6c082 | bellard | |
137 | 3fc6c082 | bellard | static void spr_read_ibat_h (void *opaque, int sprn) |
138 | 3fc6c082 | bellard | { |
139 | 3fc6c082 | bellard | gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2); |
140 | 3fc6c082 | bellard | } |
141 | 3fc6c082 | bellard | |
142 | 3fc6c082 | bellard | static void spr_write_ibatu (void *opaque, int sprn) |
143 | 3fc6c082 | bellard | { |
144 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
145 | 3fc6c082 | bellard | |
146 | 3fc6c082 | bellard | gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
|
147 | 3fc6c082 | bellard | RET_STOP(ctx); |
148 | 3fc6c082 | bellard | } |
149 | 3fc6c082 | bellard | |
150 | 3fc6c082 | bellard | static void spr_write_ibatu_h (void *opaque, int sprn) |
151 | 3fc6c082 | bellard | { |
152 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
153 | 3fc6c082 | bellard | |
154 | 3fc6c082 | bellard | gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
|
155 | 3fc6c082 | bellard | RET_STOP(ctx); |
156 | 3fc6c082 | bellard | } |
157 | 3fc6c082 | bellard | |
158 | 3fc6c082 | bellard | static void spr_write_ibatl (void *opaque, int sprn) |
159 | 3fc6c082 | bellard | { |
160 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
161 | 3fc6c082 | bellard | |
162 | 3fc6c082 | bellard | gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
|
163 | 3fc6c082 | bellard | RET_STOP(ctx); |
164 | 3fc6c082 | bellard | } |
165 | 3fc6c082 | bellard | |
166 | 3fc6c082 | bellard | static void spr_write_ibatl_h (void *opaque, int sprn) |
167 | 3fc6c082 | bellard | { |
168 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
169 | 3fc6c082 | bellard | |
170 | 3fc6c082 | bellard | gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
|
171 | 3fc6c082 | bellard | RET_STOP(ctx); |
172 | 3fc6c082 | bellard | } |
173 | 3fc6c082 | bellard | |
174 | 3fc6c082 | bellard | /* DBAT0U...DBAT7U */
|
175 | 3fc6c082 | bellard | /* DBAT0L...DBAT7L */
|
176 | 3fc6c082 | bellard | static void spr_read_dbat (void *opaque, int sprn) |
177 | 3fc6c082 | bellard | { |
178 | 3fc6c082 | bellard | gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2); |
179 | 3fc6c082 | bellard | } |
180 | 3fc6c082 | bellard | |
181 | 3fc6c082 | bellard | static void spr_read_dbat_h (void *opaque, int sprn) |
182 | 3fc6c082 | bellard | { |
183 | 3fc6c082 | bellard | gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2); |
184 | 3fc6c082 | bellard | } |
185 | 3fc6c082 | bellard | |
186 | 3fc6c082 | bellard | static void spr_write_dbatu (void *opaque, int sprn) |
187 | 3fc6c082 | bellard | { |
188 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
189 | 3fc6c082 | bellard | |
190 | 3fc6c082 | bellard | gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
|
191 | 3fc6c082 | bellard | RET_STOP(ctx); |
192 | 3fc6c082 | bellard | } |
193 | 3fc6c082 | bellard | |
194 | 3fc6c082 | bellard | static void spr_write_dbatu_h (void *opaque, int sprn) |
195 | 3fc6c082 | bellard | { |
196 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
197 | 3fc6c082 | bellard | |
198 | 3fc6c082 | bellard | gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
|
199 | 3fc6c082 | bellard | RET_STOP(ctx); |
200 | 3fc6c082 | bellard | } |
201 | 3fc6c082 | bellard | |
202 | 3fc6c082 | bellard | static void spr_write_dbatl (void *opaque, int sprn) |
203 | 3fc6c082 | bellard | { |
204 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
205 | 3fc6c082 | bellard | |
206 | 3fc6c082 | bellard | gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
|
207 | 3fc6c082 | bellard | RET_STOP(ctx); |
208 | 3fc6c082 | bellard | } |
209 | 3fc6c082 | bellard | |
210 | 3fc6c082 | bellard | static void spr_write_dbatl_h (void *opaque, int sprn) |
211 | 3fc6c082 | bellard | { |
212 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
213 | 3fc6c082 | bellard | |
214 | 3fc6c082 | bellard | gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
|
215 | 3fc6c082 | bellard | RET_STOP(ctx); |
216 | 3fc6c082 | bellard | } |
217 | 3fc6c082 | bellard | |
218 | 3fc6c082 | bellard | /* SDR1 */
|
219 | 3fc6c082 | bellard | static void spr_read_sdr1 (void *opaque, int sprn) |
220 | 3fc6c082 | bellard | { |
221 | 3fc6c082 | bellard | gen_op_load_sdr1(); |
222 | 3fc6c082 | bellard | } |
223 | 3fc6c082 | bellard | |
224 | 3fc6c082 | bellard | static void spr_write_sdr1 (void *opaque, int sprn) |
225 | 3fc6c082 | bellard | { |
226 | 3fc6c082 | bellard | DisasContext *ctx = opaque; |
227 | 3fc6c082 | bellard | |
228 | 3fc6c082 | bellard | gen_op_store_sdr1(); |
229 | 3fc6c082 | bellard | RET_STOP(ctx); |
230 | 3fc6c082 | bellard | } |
231 | 3fc6c082 | bellard | |
232 | 3fc6c082 | bellard | static void spr_write_pir (void *opaque, int sprn) |
233 | 3fc6c082 | bellard | { |
234 | 3fc6c082 | bellard | gen_op_store_pir(); |
235 | 3fc6c082 | bellard | } |
236 | 3fc6c082 | bellard | |
237 | 3fc6c082 | bellard | static inline void spr_register (CPUPPCState *env, int num, |
238 | 3fc6c082 | bellard | const unsigned char *name, |
239 | 3fc6c082 | bellard | void (*uea_read)(void *opaque, int sprn), |
240 | 3fc6c082 | bellard | void (*uea_write)(void *opaque, int sprn), |
241 | 3fc6c082 | bellard | void (*oea_read)(void *opaque, int sprn), |
242 | 3fc6c082 | bellard | void (*oea_write)(void *opaque, int sprn), |
243 | 3fc6c082 | bellard | target_ulong initial_value) |
244 | 3fc6c082 | bellard | { |
245 | 3fc6c082 | bellard | ppc_spr_t *spr; |
246 | 3fc6c082 | bellard | |
247 | 3fc6c082 | bellard | spr = &env->spr_cb[num]; |
248 | 3fc6c082 | bellard | if (spr->name != NULL ||env-> spr[num] != 0x00000000 || |
249 | 3fc6c082 | bellard | spr->uea_read != NULL || spr->uea_write != NULL || |
250 | 3fc6c082 | bellard | spr->oea_read != NULL || spr->oea_write != NULL) { |
251 | 3fc6c082 | bellard | printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
|
252 | 3fc6c082 | bellard | exit(1);
|
253 | 3fc6c082 | bellard | } |
254 | 3fc6c082 | bellard | #if defined(PPC_DEBUG_SPR)
|
255 | 26a76461 | bellard | printf("*** register spr %d (%03x) %s val %08" PRIx64 "\n", num, num, name, |
256 | 3fc6c082 | bellard | (unsigned long long)initial_value); |
257 | 3fc6c082 | bellard | #endif
|
258 | 3fc6c082 | bellard | spr->name = name; |
259 | 3fc6c082 | bellard | spr->uea_read = uea_read; |
260 | 3fc6c082 | bellard | spr->uea_write = uea_write; |
261 | 3fc6c082 | bellard | spr->oea_read = oea_read; |
262 | 3fc6c082 | bellard | spr->oea_write = oea_write; |
263 | 3fc6c082 | bellard | env->spr[num] = initial_value; |
264 | 3fc6c082 | bellard | } |
265 | 3fc6c082 | bellard | |
266 | 3fc6c082 | bellard | /* Generic PowerPC SPRs */
|
267 | 3fc6c082 | bellard | static void gen_spr_generic (CPUPPCState *env) |
268 | 3fc6c082 | bellard | { |
269 | 3fc6c082 | bellard | /* Integer processing */
|
270 | 3fc6c082 | bellard | spr_register(env, SPR_XER, "XER",
|
271 | 3fc6c082 | bellard | &spr_read_xer, &spr_write_xer, |
272 | 3fc6c082 | bellard | &spr_read_xer, &spr_write_xer, |
273 | 3fc6c082 | bellard | 0x00000000);
|
274 | 3fc6c082 | bellard | /* Branch contol */
|
275 | 3fc6c082 | bellard | spr_register(env, SPR_LR, "LR",
|
276 | 3fc6c082 | bellard | &spr_read_lr, &spr_write_lr, |
277 | 3fc6c082 | bellard | &spr_read_lr, &spr_write_lr, |
278 | 3fc6c082 | bellard | 0x00000000);
|
279 | 3fc6c082 | bellard | spr_register(env, SPR_CTR, "CTR",
|
280 | 3fc6c082 | bellard | &spr_read_ctr, &spr_write_ctr, |
281 | 3fc6c082 | bellard | &spr_read_ctr, &spr_write_ctr, |
282 | 3fc6c082 | bellard | 0x00000000);
|
283 | 3fc6c082 | bellard | /* Interrupt processing */
|
284 | 3fc6c082 | bellard | spr_register(env, SPR_SRR0, "SRR0",
|
285 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
286 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
287 | 3fc6c082 | bellard | 0x00000000);
|
288 | 3fc6c082 | bellard | spr_register(env, SPR_SRR1, "SRR1",
|
289 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
290 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
291 | 3fc6c082 | bellard | 0x00000000);
|
292 | 3fc6c082 | bellard | /* Processor control */
|
293 | 3fc6c082 | bellard | spr_register(env, SPR_SPRG0, "SPRG0",
|
294 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
295 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
296 | 3fc6c082 | bellard | 0x00000000);
|
297 | 3fc6c082 | bellard | spr_register(env, SPR_SPRG1, "SPRG1",
|
298 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
299 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
300 | 3fc6c082 | bellard | 0x00000000);
|
301 | 3fc6c082 | bellard | spr_register(env, SPR_SPRG2, "SPRG2",
|
302 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
303 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
304 | 3fc6c082 | bellard | 0x00000000);
|
305 | 3fc6c082 | bellard | spr_register(env, SPR_SPRG3, "SPRG3",
|
306 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
307 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
308 | 3fc6c082 | bellard | 0x00000000);
|
309 | 3fc6c082 | bellard | } |
310 | 3fc6c082 | bellard | |
311 | 3fc6c082 | bellard | /* SPR common to all non-embedded PowerPC, including 601 */
|
312 | 3fc6c082 | bellard | static void gen_spr_ne_601 (CPUPPCState *env) |
313 | 3fc6c082 | bellard | { |
314 | 3fc6c082 | bellard | /* Exception processing */
|
315 | 3fc6c082 | bellard | spr_register(env, SPR_DSISR, "DSISR",
|
316 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
317 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
318 | 3fc6c082 | bellard | 0x00000000);
|
319 | 3fc6c082 | bellard | spr_register(env, SPR_DAR, "DAR",
|
320 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
321 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
322 | 3fc6c082 | bellard | 0x00000000);
|
323 | 3fc6c082 | bellard | /* Timer */
|
324 | 3fc6c082 | bellard | spr_register(env, SPR_DECR, "DECR",
|
325 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
326 | 3fc6c082 | bellard | &spr_read_decr, &spr_write_decr, |
327 | 3fc6c082 | bellard | 0x00000000);
|
328 | 3fc6c082 | bellard | /* Memory management */
|
329 | 3fc6c082 | bellard | spr_register(env, SPR_SDR1, "SDR1",
|
330 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
331 | 3fc6c082 | bellard | &spr_read_sdr1, &spr_write_sdr1, |
332 | 3fc6c082 | bellard | 0x00000000);
|
333 | 3fc6c082 | bellard | } |
334 | 3fc6c082 | bellard | |
335 | 3fc6c082 | bellard | /* BATs 0-3 */
|
336 | 3fc6c082 | bellard | static void gen_low_BATs (CPUPPCState *env) |
337 | 3fc6c082 | bellard | { |
338 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT0U, "IBAT0U",
|
339 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
340 | 3fc6c082 | bellard | &spr_read_ibat, &spr_write_ibatu, |
341 | 3fc6c082 | bellard | 0x00000000);
|
342 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT0L, "IBAT0L",
|
343 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
344 | 3fc6c082 | bellard | &spr_read_ibat, &spr_write_ibatl, |
345 | 3fc6c082 | bellard | 0x00000000);
|
346 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT1U, "IBAT1U",
|
347 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
348 | 3fc6c082 | bellard | &spr_read_ibat, &spr_write_ibatu, |
349 | 3fc6c082 | bellard | 0x00000000);
|
350 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT1L, "IBAT1L",
|
351 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
352 | 3fc6c082 | bellard | &spr_read_ibat, &spr_write_ibatl, |
353 | 3fc6c082 | bellard | 0x00000000);
|
354 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT2U, "IBAT2U",
|
355 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
356 | 3fc6c082 | bellard | &spr_read_ibat, &spr_write_ibatu, |
357 | 3fc6c082 | bellard | 0x00000000);
|
358 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT2L, "IBAT2L",
|
359 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
360 | 3fc6c082 | bellard | &spr_read_ibat, &spr_write_ibatl, |
361 | 3fc6c082 | bellard | 0x00000000);
|
362 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT3U, "IBAT3U",
|
363 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
364 | 3fc6c082 | bellard | &spr_read_ibat, &spr_write_ibatu, |
365 | 3fc6c082 | bellard | 0x00000000);
|
366 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT3L, "IBAT3L",
|
367 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
368 | 3fc6c082 | bellard | &spr_read_ibat, &spr_write_ibatl, |
369 | 3fc6c082 | bellard | 0x00000000);
|
370 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT0U, "DBAT0U",
|
371 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
372 | 3fc6c082 | bellard | &spr_read_dbat, &spr_write_dbatu, |
373 | 3fc6c082 | bellard | 0x00000000);
|
374 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT0L, "DBAT0L",
|
375 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
376 | 3fc6c082 | bellard | &spr_read_dbat, &spr_write_dbatl, |
377 | 3fc6c082 | bellard | 0x00000000);
|
378 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT1U, "DBAT1U",
|
379 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
380 | 3fc6c082 | bellard | &spr_read_dbat, &spr_write_dbatu, |
381 | 3fc6c082 | bellard | 0x00000000);
|
382 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT1L, "DBAT1L",
|
383 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
384 | 3fc6c082 | bellard | &spr_read_dbat, &spr_write_dbatl, |
385 | 3fc6c082 | bellard | 0x00000000);
|
386 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT2U, "DBAT2U",
|
387 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
388 | 3fc6c082 | bellard | &spr_read_dbat, &spr_write_dbatu, |
389 | 3fc6c082 | bellard | 0x00000000);
|
390 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT2L, "DBAT2L",
|
391 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
392 | 3fc6c082 | bellard | &spr_read_dbat, &spr_write_dbatl, |
393 | 3fc6c082 | bellard | 0x00000000);
|
394 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT3U, "DBAT3U",
|
395 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
396 | 3fc6c082 | bellard | &spr_read_dbat, &spr_write_dbatu, |
397 | 3fc6c082 | bellard | 0x00000000);
|
398 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT3L, "DBAT3L",
|
399 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
400 | 3fc6c082 | bellard | &spr_read_dbat, &spr_write_dbatl, |
401 | 3fc6c082 | bellard | 0x00000000);
|
402 | 3fc6c082 | bellard | env->nb_BATs = 4;
|
403 | 3fc6c082 | bellard | } |
404 | 3fc6c082 | bellard | |
405 | 3fc6c082 | bellard | /* BATs 4-7 */
|
406 | 3fc6c082 | bellard | static void gen_high_BATs (CPUPPCState *env) |
407 | 3fc6c082 | bellard | { |
408 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT4U, "IBAT4U",
|
409 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
410 | 3fc6c082 | bellard | &spr_read_ibat_h, &spr_write_ibatu_h, |
411 | 3fc6c082 | bellard | 0x00000000);
|
412 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT4L, "IBAT4L",
|
413 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
414 | 3fc6c082 | bellard | &spr_read_ibat_h, &spr_write_ibatl_h, |
415 | 3fc6c082 | bellard | 0x00000000);
|
416 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT5U, "IBAT5U",
|
417 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
418 | 3fc6c082 | bellard | &spr_read_ibat_h, &spr_write_ibatu_h, |
419 | 3fc6c082 | bellard | 0x00000000);
|
420 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT5L, "IBAT5L",
|
421 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
422 | 3fc6c082 | bellard | &spr_read_ibat_h, &spr_write_ibatl_h, |
423 | 3fc6c082 | bellard | 0x00000000);
|
424 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT6U, "IBAT6U",
|
425 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
426 | 3fc6c082 | bellard | &spr_read_ibat_h, &spr_write_ibatu_h, |
427 | 3fc6c082 | bellard | 0x00000000);
|
428 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT6L, "IBAT6L",
|
429 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
430 | 3fc6c082 | bellard | &spr_read_ibat_h, &spr_write_ibatl_h, |
431 | 3fc6c082 | bellard | 0x00000000);
|
432 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT7U, "IBAT7U",
|
433 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
434 | 3fc6c082 | bellard | &spr_read_ibat_h, &spr_write_ibatu_h, |
435 | 3fc6c082 | bellard | 0x00000000);
|
436 | 3fc6c082 | bellard | spr_register(env, SPR_IBAT7L, "IBAT7L",
|
437 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
438 | 3fc6c082 | bellard | &spr_read_ibat_h, &spr_write_ibatl_h, |
439 | 3fc6c082 | bellard | 0x00000000);
|
440 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT4U, "DBAT4U",
|
441 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
442 | 3fc6c082 | bellard | &spr_read_dbat_h, &spr_write_dbatu_h, |
443 | 3fc6c082 | bellard | 0x00000000);
|
444 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT4L, "DBAT4L",
|
445 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
446 | 3fc6c082 | bellard | &spr_read_dbat_h, &spr_write_dbatl_h, |
447 | 3fc6c082 | bellard | 0x00000000);
|
448 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT5U, "DBAT5U",
|
449 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
450 | 3fc6c082 | bellard | &spr_read_dbat_h, &spr_write_dbatu_h, |
451 | 3fc6c082 | bellard | 0x00000000);
|
452 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT5L, "DBAT5L",
|
453 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
454 | 3fc6c082 | bellard | &spr_read_dbat_h, &spr_write_dbatl_h, |
455 | 3fc6c082 | bellard | 0x00000000);
|
456 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT6U, "DBAT6U",
|
457 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
458 | 3fc6c082 | bellard | &spr_read_dbat_h, &spr_write_dbatu_h, |
459 | 3fc6c082 | bellard | 0x00000000);
|
460 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT6L, "DBAT6L",
|
461 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
462 | 3fc6c082 | bellard | &spr_read_dbat_h, &spr_write_dbatl_h, |
463 | 3fc6c082 | bellard | 0x00000000);
|
464 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT7U, "DBAT7U",
|
465 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
466 | 3fc6c082 | bellard | &spr_read_dbat_h, &spr_write_dbatu_h, |
467 | 3fc6c082 | bellard | 0x00000000);
|
468 | 3fc6c082 | bellard | spr_register(env, SPR_DBAT7L, "DBAT7L",
|
469 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
470 | 3fc6c082 | bellard | &spr_read_dbat_h, &spr_write_dbatl_h, |
471 | 3fc6c082 | bellard | 0x00000000);
|
472 | 3fc6c082 | bellard | env->nb_BATs = 8;
|
473 | 3fc6c082 | bellard | } |
474 | 3fc6c082 | bellard | |
475 | 3fc6c082 | bellard | /* Generic PowerPC time base */
|
476 | 3fc6c082 | bellard | static void gen_tbl (CPUPPCState *env) |
477 | 3fc6c082 | bellard | { |
478 | 3fc6c082 | bellard | spr_register(env, SPR_VTBL, "TBL",
|
479 | 3fc6c082 | bellard | &spr_read_tbl, SPR_NOACCESS, |
480 | 3fc6c082 | bellard | &spr_read_tbl, SPR_NOACCESS, |
481 | 3fc6c082 | bellard | 0x00000000);
|
482 | 3fc6c082 | bellard | spr_register(env, SPR_TBL, "TBL",
|
483 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
484 | 3fc6c082 | bellard | SPR_NOACCESS, &spr_write_tbl, |
485 | 3fc6c082 | bellard | 0x00000000);
|
486 | 3fc6c082 | bellard | spr_register(env, SPR_VTBU, "TBU",
|
487 | 3fc6c082 | bellard | &spr_read_tbu, SPR_NOACCESS, |
488 | 3fc6c082 | bellard | &spr_read_tbu, SPR_NOACCESS, |
489 | 3fc6c082 | bellard | 0x00000000);
|
490 | 3fc6c082 | bellard | spr_register(env, SPR_TBU, "TBU",
|
491 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
492 | 3fc6c082 | bellard | SPR_NOACCESS, &spr_write_tbu, |
493 | 3fc6c082 | bellard | 0x00000000);
|
494 | 3fc6c082 | bellard | } |
495 | 3fc6c082 | bellard | |
496 | 3fc6c082 | bellard | /* SPR common to all 7xx PowerPC implementations */
|
497 | 3fc6c082 | bellard | static void gen_spr_7xx (CPUPPCState *env) |
498 | 3fc6c082 | bellard | { |
499 | 3fc6c082 | bellard | /* Breakpoints */
|
500 | 3fc6c082 | bellard | /* XXX : not implemented */
|
501 | 3fc6c082 | bellard | spr_register(env, SPR_DABR, "DABR",
|
502 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
503 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
504 | 3fc6c082 | bellard | 0x00000000);
|
505 | 3fc6c082 | bellard | /* XXX : not implemented */
|
506 | 3fc6c082 | bellard | spr_register(env, SPR_IABR, "IABR",
|
507 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
508 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
509 | 3fc6c082 | bellard | 0x00000000);
|
510 | 3fc6c082 | bellard | /* Cache management */
|
511 | 3fc6c082 | bellard | /* XXX : not implemented */
|
512 | 3fc6c082 | bellard | spr_register(env, SPR_ICTC, "ICTC",
|
513 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
514 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
515 | 3fc6c082 | bellard | 0x00000000);
|
516 | 3fc6c082 | bellard | /* Performance monitors */
|
517 | 3fc6c082 | bellard | /* XXX : not implemented */
|
518 | 3fc6c082 | bellard | spr_register(env, SPR_MMCR0, "MMCR0",
|
519 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
520 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
521 | 3fc6c082 | bellard | 0x00000000);
|
522 | 3fc6c082 | bellard | /* XXX : not implemented */
|
523 | 3fc6c082 | bellard | spr_register(env, SPR_MMCR1, "MMCR1",
|
524 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
525 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
526 | 3fc6c082 | bellard | 0x00000000);
|
527 | 3fc6c082 | bellard | /* XXX : not implemented */
|
528 | 3fc6c082 | bellard | spr_register(env, SPR_PMC1, "PMC1",
|
529 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
530 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
531 | 3fc6c082 | bellard | 0x00000000);
|
532 | 3fc6c082 | bellard | /* XXX : not implemented */
|
533 | 3fc6c082 | bellard | spr_register(env, SPR_PMC2, "PMC2",
|
534 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
535 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
536 | 3fc6c082 | bellard | 0x00000000);
|
537 | 3fc6c082 | bellard | /* XXX : not implemented */
|
538 | 3fc6c082 | bellard | spr_register(env, SPR_PMC3, "PMC3",
|
539 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
540 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
541 | 3fc6c082 | bellard | 0x00000000);
|
542 | 3fc6c082 | bellard | /* XXX : not implemented */
|
543 | 3fc6c082 | bellard | spr_register(env, SPR_PMC4, "PMC4",
|
544 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
545 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
546 | 3fc6c082 | bellard | 0x00000000);
|
547 | 3fc6c082 | bellard | /* XXX : not implemented */
|
548 | 3fc6c082 | bellard | spr_register(env, SPR_SIA, "SIA",
|
549 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
550 | 3fc6c082 | bellard | &spr_read_generic, SPR_NOACCESS, |
551 | 3fc6c082 | bellard | 0x00000000);
|
552 | 3fc6c082 | bellard | spr_register(env, SPR_UMMCR0, "UMMCR0",
|
553 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
554 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
555 | 3fc6c082 | bellard | 0x00000000);
|
556 | 3fc6c082 | bellard | spr_register(env, SPR_UMMCR1, "UMMCR1",
|
557 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
558 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
559 | 3fc6c082 | bellard | 0x00000000);
|
560 | 3fc6c082 | bellard | spr_register(env, SPR_UPMC1, "UPMC1",
|
561 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
562 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
563 | 3fc6c082 | bellard | 0x00000000);
|
564 | 3fc6c082 | bellard | spr_register(env, SPR_UPMC2, "UPMC2",
|
565 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
566 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
567 | 3fc6c082 | bellard | 0x00000000);
|
568 | 3fc6c082 | bellard | spr_register(env, SPR_UPMC3, "UPMC3",
|
569 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
570 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
571 | 3fc6c082 | bellard | 0x00000000);
|
572 | 3fc6c082 | bellard | spr_register(env, SPR_UPMC4, "UPMC4",
|
573 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
574 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
575 | 3fc6c082 | bellard | 0x00000000);
|
576 | 3fc6c082 | bellard | spr_register(env, SPR_USIA, "USIA",
|
577 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
578 | 3fc6c082 | bellard | &spr_read_ureg, SPR_NOACCESS, |
579 | 3fc6c082 | bellard | 0x00000000);
|
580 | 3fc6c082 | bellard | /* Thermal management */
|
581 | 3fc6c082 | bellard | /* XXX : not implemented */
|
582 | 3fc6c082 | bellard | spr_register(env, SPR_THRM1, "THRM1",
|
583 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
584 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
585 | 3fc6c082 | bellard | 0x00000000);
|
586 | 3fc6c082 | bellard | /* XXX : not implemented */
|
587 | 3fc6c082 | bellard | spr_register(env, SPR_THRM2, "THRM2",
|
588 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
589 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
590 | 3fc6c082 | bellard | 0x00000000);
|
591 | 3fc6c082 | bellard | /* XXX : not implemented */
|
592 | 3fc6c082 | bellard | spr_register(env, SPR_THRM3, "THRM3",
|
593 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
594 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
595 | 3fc6c082 | bellard | 0x00000000);
|
596 | 3fc6c082 | bellard | /* External access control */
|
597 | 3fc6c082 | bellard | /* XXX : not implemented */
|
598 | 3fc6c082 | bellard | spr_register(env, SPR_EAR, "EAR",
|
599 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
600 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
601 | 3fc6c082 | bellard | 0x00000000);
|
602 | 3fc6c082 | bellard | } |
603 | 3fc6c082 | bellard | |
604 | 3fc6c082 | bellard | /* SPR specific to PowerPC 604 implementation */
|
605 | 3fc6c082 | bellard | static void gen_spr_604 (CPUPPCState *env) |
606 | 3fc6c082 | bellard | { |
607 | 3fc6c082 | bellard | /* Processor identification */
|
608 | 3fc6c082 | bellard | spr_register(env, SPR_PIR, "PIR",
|
609 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
610 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_pir, |
611 | 3fc6c082 | bellard | 0x00000000);
|
612 | 3fc6c082 | bellard | /* Breakpoints */
|
613 | 3fc6c082 | bellard | /* XXX : not implemented */
|
614 | 3fc6c082 | bellard | spr_register(env, SPR_IABR, "IABR",
|
615 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
616 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
617 | 3fc6c082 | bellard | 0x00000000);
|
618 | 3fc6c082 | bellard | /* XXX : not implemented */
|
619 | 3fc6c082 | bellard | spr_register(env, SPR_DABR, "DABR",
|
620 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
621 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
622 | 3fc6c082 | bellard | 0x00000000);
|
623 | 3fc6c082 | bellard | /* Performance counters */
|
624 | 3fc6c082 | bellard | /* XXX : not implemented */
|
625 | 3fc6c082 | bellard | spr_register(env, SPR_MMCR0, "MMCR0",
|
626 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
627 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
628 | 3fc6c082 | bellard | 0x00000000);
|
629 | 3fc6c082 | bellard | /* XXX : not implemented */
|
630 | 3fc6c082 | bellard | spr_register(env, SPR_MMCR1, "MMCR1",
|
631 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
632 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
633 | 3fc6c082 | bellard | 0x00000000);
|
634 | 3fc6c082 | bellard | /* XXX : not implemented */
|
635 | 3fc6c082 | bellard | spr_register(env, SPR_PMC1, "PMC1",
|
636 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
637 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
638 | 3fc6c082 | bellard | 0x00000000);
|
639 | 3fc6c082 | bellard | /* XXX : not implemented */
|
640 | 3fc6c082 | bellard | spr_register(env, SPR_PMC2, "PMC2",
|
641 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
642 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
643 | 3fc6c082 | bellard | 0x00000000);
|
644 | 3fc6c082 | bellard | /* XXX : not implemented */
|
645 | 3fc6c082 | bellard | spr_register(env, SPR_PMC3, "PMC3",
|
646 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
647 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
648 | 3fc6c082 | bellard | 0x00000000);
|
649 | 3fc6c082 | bellard | /* XXX : not implemented */
|
650 | 3fc6c082 | bellard | spr_register(env, SPR_PMC4, "PMC4",
|
651 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
652 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
653 | 3fc6c082 | bellard | 0x00000000);
|
654 | 3fc6c082 | bellard | /* XXX : not implemented */
|
655 | 3fc6c082 | bellard | spr_register(env, SPR_SIA, "SIA",
|
656 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
657 | 3fc6c082 | bellard | &spr_read_generic, SPR_NOACCESS, |
658 | 3fc6c082 | bellard | 0x00000000);
|
659 | 3fc6c082 | bellard | /* XXX : not implemented */
|
660 | 3fc6c082 | bellard | spr_register(env, SPR_SDA, "SDA",
|
661 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
662 | 3fc6c082 | bellard | &spr_read_generic, SPR_NOACCESS, |
663 | 3fc6c082 | bellard | 0x00000000);
|
664 | 3fc6c082 | bellard | /* External access control */
|
665 | 3fc6c082 | bellard | /* XXX : not implemented */
|
666 | 3fc6c082 | bellard | spr_register(env, SPR_EAR, "EAR",
|
667 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
668 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
669 | 3fc6c082 | bellard | 0x00000000);
|
670 | 3fc6c082 | bellard | } |
671 | 3fc6c082 | bellard | |
672 | 3fc6c082 | bellard | // XXX: TODO (64 bits PPC sprs)
|
673 | 3fc6c082 | bellard | /*
|
674 | 3fc6c082 | bellard | * ASR => SPR 280 (64 bits)
|
675 | 3fc6c082 | bellard | * FPECR => SPR 1022 (?)
|
676 | 3fc6c082 | bellard | * VRSAVE => SPR 256 (Altivec)
|
677 | 3fc6c082 | bellard | * SCOMC => SPR 276 (64 bits ?)
|
678 | 3fc6c082 | bellard | * SCOMD => SPR 277 (64 bits ?)
|
679 | 3fc6c082 | bellard | * HSPRG0 => SPR 304 (hypervisor)
|
680 | 3fc6c082 | bellard | * HSPRG1 => SPR 305 (hypervisor)
|
681 | 3fc6c082 | bellard | * HDEC => SPR 310 (hypervisor)
|
682 | 3fc6c082 | bellard | * HIOR => SPR 311 (hypervisor)
|
683 | 3fc6c082 | bellard | * RMOR => SPR 312 (970)
|
684 | 3fc6c082 | bellard | * HRMOR => SPR 313 (hypervisor)
|
685 | 3fc6c082 | bellard | * HSRR0 => SPR 314 (hypervisor)
|
686 | 3fc6c082 | bellard | * HSRR1 => SPR 315 (hypervisor)
|
687 | 3fc6c082 | bellard | * LPCR => SPR 316 (970)
|
688 | 3fc6c082 | bellard | * LPIDR => SPR 317 (970)
|
689 | 3fc6c082 | bellard | * ... and more (thermal management, performance counters, ...)
|
690 | 3fc6c082 | bellard | */
|
691 | 3fc6c082 | bellard | |
692 | 3fc6c082 | bellard | static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) |
693 | 3fc6c082 | bellard | { |
694 | 3fc6c082 | bellard | /* Default MMU definitions */
|
695 | 3fc6c082 | bellard | env->nb_BATs = -1;
|
696 | 3fc6c082 | bellard | env->nb_tlb = 0;
|
697 | 3fc6c082 | bellard | env->nb_ways = 0;
|
698 | 3fc6c082 | bellard | /* XXX: missing:
|
699 | 3fc6c082 | bellard | * 32 bits PPC:
|
700 | 3fc6c082 | bellard | * - MPC5xx(x)
|
701 | 3fc6c082 | bellard | * - MPC8xx(x)
|
702 | 3fc6c082 | bellard | * - RCPU (MPC5xx)
|
703 | 3fc6c082 | bellard | */
|
704 | 3fc6c082 | bellard | spr_register(env, SPR_PVR, "PVR",
|
705 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
706 | 3fc6c082 | bellard | &spr_read_generic, SPR_NOACCESS, |
707 | 3fc6c082 | bellard | def->pvr); |
708 | 3fc6c082 | bellard | switch (def->pvr & def->pvr_mask) {
|
709 | 3fc6c082 | bellard | case CPU_PPC_604: /* PPC 604 */ |
710 | 3fc6c082 | bellard | case CPU_PPC_604E: /* PPC 604e */ |
711 | 3fc6c082 | bellard | case CPU_PPC_604R: /* PPC 604r */ |
712 | 3fc6c082 | bellard | gen_spr_generic(env); |
713 | 3fc6c082 | bellard | gen_spr_ne_601(env); |
714 | 3fc6c082 | bellard | /* Memory management */
|
715 | 3fc6c082 | bellard | gen_low_BATs(env); |
716 | 3fc6c082 | bellard | /* Time base */
|
717 | 3fc6c082 | bellard | gen_tbl(env); |
718 | 3fc6c082 | bellard | gen_spr_604(env); |
719 | 3fc6c082 | bellard | /* Hardware implementation registers */
|
720 | 3fc6c082 | bellard | /* XXX : not implemented */
|
721 | 3fc6c082 | bellard | spr_register(env, SPR_HID0, "HID0",
|
722 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
723 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
724 | 3fc6c082 | bellard | 0x00000000);
|
725 | 3fc6c082 | bellard | /* XXX : not implemented */
|
726 | 3fc6c082 | bellard | spr_register(env, SPR_HID1, "HID1",
|
727 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
728 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
729 | 3fc6c082 | bellard | 0x00000000);
|
730 | 3fc6c082 | bellard | break;
|
731 | 3fc6c082 | bellard | |
732 | 3fc6c082 | bellard | case CPU_PPC_74x: /* PPC 740 / 750 */ |
733 | 3fc6c082 | bellard | case CPU_PPC_74xP: /* PPC 740P / 750P */ |
734 | 3fc6c082 | bellard | case CPU_PPC_750CXE: /* IBM PPC 750cxe */ |
735 | 3fc6c082 | bellard | gen_spr_generic(env); |
736 | 3fc6c082 | bellard | gen_spr_ne_601(env); |
737 | 3fc6c082 | bellard | /* Memory management */
|
738 | 3fc6c082 | bellard | gen_low_BATs(env); |
739 | 3fc6c082 | bellard | /* Time base */
|
740 | 3fc6c082 | bellard | gen_tbl(env); |
741 | 3fc6c082 | bellard | gen_spr_7xx(env); |
742 | 3fc6c082 | bellard | /* XXX : not implemented */
|
743 | 3fc6c082 | bellard | spr_register(env, SPR_L2CR, "L2CR",
|
744 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
745 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
746 | 3fc6c082 | bellard | 0x00000000);
|
747 | 3fc6c082 | bellard | /* Hardware implementation registers */
|
748 | 3fc6c082 | bellard | /* XXX : not implemented */
|
749 | 3fc6c082 | bellard | spr_register(env, SPR_HID0, "HID0",
|
750 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
751 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
752 | 3fc6c082 | bellard | 0x00000000);
|
753 | 3fc6c082 | bellard | /* XXX : not implemented */
|
754 | 3fc6c082 | bellard | spr_register(env, SPR_HID1, "HID1",
|
755 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
756 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
757 | 3fc6c082 | bellard | 0x00000000);
|
758 | 3fc6c082 | bellard | break;
|
759 | 3fc6c082 | bellard | |
760 | 3fc6c082 | bellard | case CPU_PPC_750FX: /* IBM PPC 750 FX */ |
761 | 3fc6c082 | bellard | case CPU_PPC_750GX: /* IBM PPC 750 GX */ |
762 | 3fc6c082 | bellard | gen_spr_generic(env); |
763 | 3fc6c082 | bellard | gen_spr_ne_601(env); |
764 | 3fc6c082 | bellard | /* Memory management */
|
765 | 3fc6c082 | bellard | gen_low_BATs(env); |
766 | 3fc6c082 | bellard | /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
|
767 | 3fc6c082 | bellard | gen_high_BATs(env); |
768 | 3fc6c082 | bellard | /* Time base */
|
769 | 3fc6c082 | bellard | gen_tbl(env); |
770 | 3fc6c082 | bellard | gen_spr_7xx(env); |
771 | 3fc6c082 | bellard | /* XXX : not implemented */
|
772 | 3fc6c082 | bellard | spr_register(env, SPR_L2CR, "L2CR",
|
773 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
774 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
775 | 3fc6c082 | bellard | 0x00000000);
|
776 | 3fc6c082 | bellard | /* Hardware implementation registers */
|
777 | 3fc6c082 | bellard | /* XXX : not implemented */
|
778 | 3fc6c082 | bellard | spr_register(env, SPR_HID0, "HID0",
|
779 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
780 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
781 | 3fc6c082 | bellard | 0x00000000);
|
782 | 3fc6c082 | bellard | /* XXX : not implemented */
|
783 | 3fc6c082 | bellard | spr_register(env, SPR_HID1, "HID1",
|
784 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
785 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
786 | 3fc6c082 | bellard | 0x00000000);
|
787 | 3fc6c082 | bellard | /* XXX : not implemented */
|
788 | 3fc6c082 | bellard | spr_register(env, SPR_750_HID2, "HID2",
|
789 | 3fc6c082 | bellard | SPR_NOACCESS, SPR_NOACCESS, |
790 | 3fc6c082 | bellard | &spr_read_generic, &spr_write_generic, |
791 | 3fc6c082 | bellard | 0x00000000);
|
792 | 3fc6c082 | bellard | break;
|
793 | 3fc6c082 | bellard | |
794 | 3fc6c082 | bellard | default:
|
795 | 3fc6c082 | bellard | gen_spr_generic(env); |
796 | 3fc6c082 | bellard | break;
|
797 | 3fc6c082 | bellard | } |
798 | 3fc6c082 | bellard | if (env->nb_BATs == -1) |
799 | 3fc6c082 | bellard | env->nb_BATs = 4;
|
800 | 3fc6c082 | bellard | } |
801 | 3fc6c082 | bellard | |
802 | 3fc6c082 | bellard | #if defined(PPC_DUMP_CPU)
|
803 | 3fc6c082 | bellard | static void dump_sprs (CPUPPCState *env) |
804 | 3fc6c082 | bellard | { |
805 | 3fc6c082 | bellard | ppc_spr_t *spr; |
806 | 3fc6c082 | bellard | uint32_t pvr = env->spr[SPR_PVR]; |
807 | 3fc6c082 | bellard | uint32_t sr, sw, ur, uw; |
808 | 3fc6c082 | bellard | int i, j, n;
|
809 | 3fc6c082 | bellard | |
810 | 3fc6c082 | bellard | printf("* SPRs for PVR=%08x\n", pvr);
|
811 | 3fc6c082 | bellard | for (i = 0; i < 32; i++) { |
812 | 3fc6c082 | bellard | for (j = 0; j < 32; j++) { |
813 | 3fc6c082 | bellard | n = (i << 5) | j;
|
814 | 3fc6c082 | bellard | spr = &env->spr_cb[n]; |
815 | 3fc6c082 | bellard | sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
|
816 | 3fc6c082 | bellard | sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
|
817 | 3fc6c082 | bellard | uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
|
818 | 3fc6c082 | bellard | ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
|
819 | 3fc6c082 | bellard | if (sw || sr || uw || ur) {
|
820 | 3fc6c082 | bellard | printf("%4d (%03x) %8s s%c%c u%c%c\n",
|
821 | 3fc6c082 | bellard | (i << 5) | j, (i << 5) | j, spr->name, |
822 | 3fc6c082 | bellard | sw ? 'w' : '-', sr ? 'r' : '-', |
823 | 3fc6c082 | bellard | uw ? 'w' : '-', ur ? 'r' : '-'); |
824 | 3fc6c082 | bellard | } |
825 | 3fc6c082 | bellard | } |
826 | 3fc6c082 | bellard | } |
827 | 3fc6c082 | bellard | fflush(stdout); |
828 | 3fc6c082 | bellard | fflush(stderr); |
829 | 3fc6c082 | bellard | } |
830 | 3fc6c082 | bellard | #endif
|
831 | 3fc6c082 | bellard | |
832 | 3fc6c082 | bellard | /*****************************************************************************/
|
833 | 3fc6c082 | bellard | #include <stdlib.h> |
834 | 3fc6c082 | bellard | #include <string.h> |
835 | 3fc6c082 | bellard | |
836 | 3fc6c082 | bellard | int fflush (FILE *stream);
|
837 | 3fc6c082 | bellard | |
838 | 3fc6c082 | bellard | /* Opcode types */
|
839 | 3fc6c082 | bellard | enum {
|
840 | 3fc6c082 | bellard | PPC_DIRECT = 0, /* Opcode routine */ |
841 | 3fc6c082 | bellard | PPC_INDIRECT = 1, /* Indirect opcode table */ |
842 | 3fc6c082 | bellard | }; |
843 | 3fc6c082 | bellard | |
844 | 3fc6c082 | bellard | static inline int is_indirect_opcode (void *handler) |
845 | 3fc6c082 | bellard | { |
846 | 3fc6c082 | bellard | return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
847 | 3fc6c082 | bellard | } |
848 | 3fc6c082 | bellard | |
849 | 3fc6c082 | bellard | static inline opc_handler_t **ind_table(void *handler) |
850 | 3fc6c082 | bellard | { |
851 | 3fc6c082 | bellard | return (opc_handler_t **)((unsigned long)handler & ~3); |
852 | 3fc6c082 | bellard | } |
853 | 3fc6c082 | bellard | |
854 | 3fc6c082 | bellard | /* Instruction table creation */
|
855 | 3fc6c082 | bellard | /* Opcodes tables creation */
|
856 | 3fc6c082 | bellard | static void fill_new_table (opc_handler_t **table, int len) |
857 | 3fc6c082 | bellard | { |
858 | 3fc6c082 | bellard | int i;
|
859 | 3fc6c082 | bellard | |
860 | 3fc6c082 | bellard | for (i = 0; i < len; i++) |
861 | 3fc6c082 | bellard | table[i] = &invalid_handler; |
862 | 3fc6c082 | bellard | } |
863 | 3fc6c082 | bellard | |
864 | 3fc6c082 | bellard | static int create_new_table (opc_handler_t **table, unsigned char idx) |
865 | 3fc6c082 | bellard | { |
866 | 3fc6c082 | bellard | opc_handler_t **tmp; |
867 | 3fc6c082 | bellard | |
868 | 3fc6c082 | bellard | tmp = malloc(0x20 * sizeof(opc_handler_t)); |
869 | 3fc6c082 | bellard | if (tmp == NULL) |
870 | 3fc6c082 | bellard | return -1; |
871 | 3fc6c082 | bellard | fill_new_table(tmp, 0x20);
|
872 | 3fc6c082 | bellard | table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
873 | 3fc6c082 | bellard | |
874 | 3fc6c082 | bellard | return 0; |
875 | 3fc6c082 | bellard | } |
876 | 3fc6c082 | bellard | |
877 | 3fc6c082 | bellard | static int insert_in_table (opc_handler_t **table, unsigned char idx, |
878 | 3fc6c082 | bellard | opc_handler_t *handler) |
879 | 3fc6c082 | bellard | { |
880 | 3fc6c082 | bellard | if (table[idx] != &invalid_handler)
|
881 | 3fc6c082 | bellard | return -1; |
882 | 3fc6c082 | bellard | table[idx] = handler; |
883 | 3fc6c082 | bellard | |
884 | 3fc6c082 | bellard | return 0; |
885 | 3fc6c082 | bellard | } |
886 | 3fc6c082 | bellard | |
887 | 3fc6c082 | bellard | static int register_direct_insn (opc_handler_t **ppc_opcodes, |
888 | 3fc6c082 | bellard | unsigned char idx, opc_handler_t *handler) |
889 | 3fc6c082 | bellard | { |
890 | 3fc6c082 | bellard | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { |
891 | 3fc6c082 | bellard | printf("*** ERROR: opcode %02x already assigned in main "
|
892 | 3fc6c082 | bellard | "opcode table\n", idx);
|
893 | 3fc6c082 | bellard | return -1; |
894 | 3fc6c082 | bellard | } |
895 | 3fc6c082 | bellard | |
896 | 3fc6c082 | bellard | return 0; |
897 | 3fc6c082 | bellard | } |
898 | 3fc6c082 | bellard | |
899 | 3fc6c082 | bellard | static int register_ind_in_table (opc_handler_t **table, |
900 | 3fc6c082 | bellard | unsigned char idx1, unsigned char idx2, |
901 | 3fc6c082 | bellard | opc_handler_t *handler) |
902 | 3fc6c082 | bellard | { |
903 | 3fc6c082 | bellard | if (table[idx1] == &invalid_handler) {
|
904 | 3fc6c082 | bellard | if (create_new_table(table, idx1) < 0) { |
905 | 3fc6c082 | bellard | printf("*** ERROR: unable to create indirect table "
|
906 | 3fc6c082 | bellard | "idx=%02x\n", idx1);
|
907 | 3fc6c082 | bellard | return -1; |
908 | 3fc6c082 | bellard | } |
909 | 3fc6c082 | bellard | } else {
|
910 | 3fc6c082 | bellard | if (!is_indirect_opcode(table[idx1])) {
|
911 | 3fc6c082 | bellard | printf("*** ERROR: idx %02x already assigned to a direct "
|
912 | 3fc6c082 | bellard | "opcode\n", idx1);
|
913 | 3fc6c082 | bellard | return -1; |
914 | 3fc6c082 | bellard | } |
915 | 3fc6c082 | bellard | } |
916 | 3fc6c082 | bellard | if (handler != NULL && |
917 | 3fc6c082 | bellard | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
918 | 3fc6c082 | bellard | printf("*** ERROR: opcode %02x already assigned in "
|
919 | 3fc6c082 | bellard | "opcode table %02x\n", idx2, idx1);
|
920 | 3fc6c082 | bellard | return -1; |
921 | 3fc6c082 | bellard | } |
922 | 3fc6c082 | bellard | |
923 | 3fc6c082 | bellard | return 0; |
924 | 3fc6c082 | bellard | } |
925 | 3fc6c082 | bellard | |
926 | 3fc6c082 | bellard | static int register_ind_insn (opc_handler_t **ppc_opcodes, |
927 | 3fc6c082 | bellard | unsigned char idx1, unsigned char idx2, |
928 | 3fc6c082 | bellard | opc_handler_t *handler) |
929 | 3fc6c082 | bellard | { |
930 | 3fc6c082 | bellard | int ret;
|
931 | 3fc6c082 | bellard | |
932 | 3fc6c082 | bellard | ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
933 | 3fc6c082 | bellard | |
934 | 3fc6c082 | bellard | return ret;
|
935 | 3fc6c082 | bellard | } |
936 | 3fc6c082 | bellard | |
937 | 3fc6c082 | bellard | static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
938 | 3fc6c082 | bellard | unsigned char idx1, unsigned char idx2, |
939 | 3fc6c082 | bellard | unsigned char idx3, opc_handler_t *handler) |
940 | 3fc6c082 | bellard | { |
941 | 3fc6c082 | bellard | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { |
942 | 3fc6c082 | bellard | printf("*** ERROR: unable to join indirect table idx "
|
943 | 3fc6c082 | bellard | "[%02x-%02x]\n", idx1, idx2);
|
944 | 3fc6c082 | bellard | return -1; |
945 | 3fc6c082 | bellard | } |
946 | 3fc6c082 | bellard | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
|
947 | 3fc6c082 | bellard | handler) < 0) {
|
948 | 3fc6c082 | bellard | printf("*** ERROR: unable to insert opcode "
|
949 | 3fc6c082 | bellard | "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
|
950 | 3fc6c082 | bellard | return -1; |
951 | 3fc6c082 | bellard | } |
952 | 3fc6c082 | bellard | |
953 | 3fc6c082 | bellard | return 0; |
954 | 3fc6c082 | bellard | } |
955 | 3fc6c082 | bellard | |
956 | 3fc6c082 | bellard | static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
957 | 3fc6c082 | bellard | { |
958 | 3fc6c082 | bellard | if (insn->opc2 != 0xFF) { |
959 | 3fc6c082 | bellard | if (insn->opc3 != 0xFF) { |
960 | 3fc6c082 | bellard | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
|
961 | 3fc6c082 | bellard | insn->opc3, &insn->handler) < 0)
|
962 | 3fc6c082 | bellard | return -1; |
963 | 3fc6c082 | bellard | } else {
|
964 | 3fc6c082 | bellard | if (register_ind_insn(ppc_opcodes, insn->opc1,
|
965 | 3fc6c082 | bellard | insn->opc2, &insn->handler) < 0)
|
966 | 3fc6c082 | bellard | return -1; |
967 | 3fc6c082 | bellard | } |
968 | 3fc6c082 | bellard | } else {
|
969 | 3fc6c082 | bellard | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
970 | 3fc6c082 | bellard | return -1; |
971 | 3fc6c082 | bellard | } |
972 | 3fc6c082 | bellard | |
973 | 3fc6c082 | bellard | return 0; |
974 | 3fc6c082 | bellard | } |
975 | 3fc6c082 | bellard | |
976 | 3fc6c082 | bellard | static int test_opcode_table (opc_handler_t **table, int len) |
977 | 3fc6c082 | bellard | { |
978 | 3fc6c082 | bellard | int i, count, tmp;
|
979 | 3fc6c082 | bellard | |
980 | 3fc6c082 | bellard | for (i = 0, count = 0; i < len; i++) { |
981 | 3fc6c082 | bellard | /* Consistency fixup */
|
982 | 3fc6c082 | bellard | if (table[i] == NULL) |
983 | 3fc6c082 | bellard | table[i] = &invalid_handler; |
984 | 3fc6c082 | bellard | if (table[i] != &invalid_handler) {
|
985 | 3fc6c082 | bellard | if (is_indirect_opcode(table[i])) {
|
986 | 3fc6c082 | bellard | tmp = test_opcode_table(ind_table(table[i]), 0x20);
|
987 | 3fc6c082 | bellard | if (tmp == 0) { |
988 | 3fc6c082 | bellard | free(table[i]); |
989 | 3fc6c082 | bellard | table[i] = &invalid_handler; |
990 | 3fc6c082 | bellard | } else {
|
991 | 3fc6c082 | bellard | count++; |
992 | 3fc6c082 | bellard | } |
993 | 3fc6c082 | bellard | } else {
|
994 | 3fc6c082 | bellard | count++; |
995 | 3fc6c082 | bellard | } |
996 | 3fc6c082 | bellard | } |
997 | 3fc6c082 | bellard | } |
998 | 3fc6c082 | bellard | |
999 | 3fc6c082 | bellard | return count;
|
1000 | 3fc6c082 | bellard | } |
1001 | 3fc6c082 | bellard | |
1002 | 3fc6c082 | bellard | static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
1003 | 3fc6c082 | bellard | { |
1004 | 3fc6c082 | bellard | if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
1005 | 3fc6c082 | bellard | printf("*** WARNING: no opcode defined !\n");
|
1006 | 3fc6c082 | bellard | } |
1007 | 3fc6c082 | bellard | |
1008 | 3fc6c082 | bellard | /*****************************************************************************/
|
1009 | 3fc6c082 | bellard | static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) |
1010 | 3fc6c082 | bellard | { |
1011 | 3fc6c082 | bellard | opcode_t *opc, *start, *end; |
1012 | 3fc6c082 | bellard | |
1013 | 3fc6c082 | bellard | fill_new_table(env->opcodes, 0x40);
|
1014 | 3fc6c082 | bellard | #if defined(PPC_DUMP_CPU)
|
1015 | 3fc6c082 | bellard | printf("* PPC instructions for PVR %08x: %s\n", def->pvr, def->name);
|
1016 | 3fc6c082 | bellard | #endif
|
1017 | 3fc6c082 | bellard | if (&opc_start < &opc_end) {
|
1018 | 3fc6c082 | bellard | start = &opc_start; |
1019 | 3fc6c082 | bellard | end = &opc_end; |
1020 | 3fc6c082 | bellard | } else {
|
1021 | 3fc6c082 | bellard | start = &opc_end; |
1022 | 3fc6c082 | bellard | end = &opc_start; |
1023 | 3fc6c082 | bellard | } |
1024 | 3fc6c082 | bellard | for (opc = start + 1; opc != end; opc++) { |
1025 | 3fc6c082 | bellard | if ((opc->handler.type & def->insns_flags) != 0) { |
1026 | 3fc6c082 | bellard | if (register_insn(env->opcodes, opc) < 0) { |
1027 | 3fc6c082 | bellard | printf("*** ERROR initializing PPC instruction "
|
1028 | 3fc6c082 | bellard | "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
|
1029 | 3fc6c082 | bellard | opc->opc3); |
1030 | 3fc6c082 | bellard | return -1; |
1031 | 3fc6c082 | bellard | } |
1032 | 3fc6c082 | bellard | #if defined(PPC_DUMP_CPU)
|
1033 | 3fc6c082 | bellard | if (opc1 != 0x00) { |
1034 | 3fc6c082 | bellard | if (opc->opc3 == 0xFF) { |
1035 | 3fc6c082 | bellard | if (opc->opc2 == 0xFF) { |
1036 | 3fc6c082 | bellard | printf(" %02x -- -- (%2d ----) : %s\n",
|
1037 | 3fc6c082 | bellard | opc->opc1, opc->opc1, opc->oname); |
1038 | 3fc6c082 | bellard | } else {
|
1039 | 3fc6c082 | bellard | printf(" %02x %02x -- (%2d %4d) : %s\n",
|
1040 | 3fc6c082 | bellard | opc->opc1, opc->opc2, opc->opc1, opc->opc2, |
1041 | 3fc6c082 | bellard | opc->oname); |
1042 | 3fc6c082 | bellard | } |
1043 | 3fc6c082 | bellard | } else {
|
1044 | 3fc6c082 | bellard | printf(" %02x %02x %02x (%2d %4d) : %s\n",
|
1045 | 3fc6c082 | bellard | opc->opc1, opc->opc2, opc->opc3, |
1046 | 3fc6c082 | bellard | opc->opc1, (opc->opc3 << 5) | opc->opc2,
|
1047 | 3fc6c082 | bellard | opc->oname); |
1048 | 3fc6c082 | bellard | } |
1049 | 3fc6c082 | bellard | } |
1050 | 3fc6c082 | bellard | #endif
|
1051 | 3fc6c082 | bellard | } |
1052 | 3fc6c082 | bellard | } |
1053 | 3fc6c082 | bellard | fix_opcode_tables(env->opcodes); |
1054 | 3fc6c082 | bellard | fflush(stdout); |
1055 | 3fc6c082 | bellard | fflush(stderr); |
1056 | 3fc6c082 | bellard | |
1057 | 3fc6c082 | bellard | return 0; |
1058 | 3fc6c082 | bellard | } |
1059 | 3fc6c082 | bellard | |
1060 | 3fc6c082 | bellard | int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
|
1061 | 3fc6c082 | bellard | { |
1062 | 3fc6c082 | bellard | env->msr_mask = def->msr_mask; |
1063 | 3fc6c082 | bellard | env->flags = def->flags; |
1064 | 3fc6c082 | bellard | if (create_ppc_opcodes(env, def) < 0) { |
1065 | 3fc6c082 | bellard | printf("Error creating opcodes table\n");
|
1066 | 3fc6c082 | bellard | fflush(stdout); |
1067 | 3fc6c082 | bellard | fflush(stderr); |
1068 | 3fc6c082 | bellard | return -1; |
1069 | 3fc6c082 | bellard | } |
1070 | 3fc6c082 | bellard | init_ppc_proc(env, def); |
1071 | 3fc6c082 | bellard | #if defined(PPC_DUMP_CPU)
|
1072 | 3fc6c082 | bellard | dump_sprs(env); |
1073 | 3fc6c082 | bellard | #endif
|
1074 | 3fc6c082 | bellard | fflush(stdout); |
1075 | 3fc6c082 | bellard | fflush(stderr); |
1076 | 3fc6c082 | bellard | |
1077 | 3fc6c082 | bellard | return 0; |
1078 | 3fc6c082 | bellard | } |
1079 | 3fc6c082 | bellard | |
1080 | 3fc6c082 | bellard | CPUPPCState *cpu_ppc_init(void)
|
1081 | 3fc6c082 | bellard | { |
1082 | 3fc6c082 | bellard | CPUPPCState *env; |
1083 | 3fc6c082 | bellard | |
1084 | 3fc6c082 | bellard | env = qemu_mallocz(sizeof(CPUPPCState));
|
1085 | 3fc6c082 | bellard | if (!env)
|
1086 | 3fc6c082 | bellard | return NULL; |
1087 | 173d6cfe | bellard | cpu_exec_init(env); |
1088 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1089 | 3fc6c082 | bellard | #if defined (DO_SINGLE_STEP) && 0 |
1090 | 3fc6c082 | bellard | /* Single step trace mode */
|
1091 | 3fc6c082 | bellard | msr_se = 1;
|
1092 | 3fc6c082 | bellard | msr_be = 1;
|
1093 | 3fc6c082 | bellard | #endif
|
1094 | 3fc6c082 | bellard | msr_fp = 1; /* Allow floating point exceptions */ |
1095 | 3fc6c082 | bellard | msr_me = 1; /* Allow machine check exceptions */ |
1096 | 3fc6c082 | bellard | #if defined(CONFIG_USER_ONLY)
|
1097 | 3fc6c082 | bellard | msr_pr = 1;
|
1098 | 3fc6c082 | bellard | #else
|
1099 | 3fc6c082 | bellard | env->nip = 0xFFFFFFFC;
|
1100 | 3fc6c082 | bellard | #endif
|
1101 | 3fc6c082 | bellard | do_compute_hflags(env); |
1102 | 3fc6c082 | bellard | env->reserve = -1;
|
1103 | 3fc6c082 | bellard | return env;
|
1104 | 3fc6c082 | bellard | } |
1105 | 3fc6c082 | bellard | |
1106 | 3fc6c082 | bellard | void cpu_ppc_close(CPUPPCState *env)
|
1107 | 3fc6c082 | bellard | { |
1108 | 3fc6c082 | bellard | /* Should also remove all opcode tables... */
|
1109 | 3fc6c082 | bellard | free(env); |
1110 | 3fc6c082 | bellard | } |
1111 | 3fc6c082 | bellard | |
1112 | 3fc6c082 | bellard | /*****************************************************************************/
|
1113 | 3fc6c082 | bellard | /* PowerPC CPU definitions */
|
1114 | 3fc6c082 | bellard | static ppc_def_t ppc_defs[] =
|
1115 | 3fc6c082 | bellard | { |
1116 | 3fc6c082 | bellard | /* Embedded PPC */
|
1117 | 3fc6c082 | bellard | #if defined (TODO)
|
1118 | 3fc6c082 | bellard | /* PPC 401 */
|
1119 | 3fc6c082 | bellard | { |
1120 | 3fc6c082 | bellard | .name = "401",
|
1121 | 3fc6c082 | bellard | .pvr = CPU_PPC_401, |
1122 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1123 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_401, |
1124 | 3fc6c082 | bellard | .flags = PPC_FLAGS_401, |
1125 | 3fc6c082 | bellard | .msr_mask = xxx, |
1126 | 3fc6c082 | bellard | }, |
1127 | 3fc6c082 | bellard | #endif
|
1128 | 3fc6c082 | bellard | #if defined (TODO)
|
1129 | 3fc6c082 | bellard | /* IOP480 (401 microcontroler) */
|
1130 | 3fc6c082 | bellard | { |
1131 | 3fc6c082 | bellard | .name = "iop480",
|
1132 | 3fc6c082 | bellard | .pvr = CPU_PPC_IOP480, |
1133 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1134 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_401, |
1135 | 3fc6c082 | bellard | .flags = PPC_FLAGS_401, |
1136 | 3fc6c082 | bellard | .msr_mask = xxx, |
1137 | 3fc6c082 | bellard | }, |
1138 | 3fc6c082 | bellard | #endif
|
1139 | 3fc6c082 | bellard | #if defined (TODO)
|
1140 | 3fc6c082 | bellard | /* PPC 403 GA */
|
1141 | 3fc6c082 | bellard | { |
1142 | 3fc6c082 | bellard | .name = "403ga",
|
1143 | 3fc6c082 | bellard | .pvr = CPU_PPC_403GA, |
1144 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFFF00,
|
1145 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_403, |
1146 | 3fc6c082 | bellard | .flags = PPC_FLAGS_403, |
1147 | 3fc6c082 | bellard | .msr_mask = 0x000000000007D23D,
|
1148 | 3fc6c082 | bellard | }, |
1149 | 3fc6c082 | bellard | #endif
|
1150 | 3fc6c082 | bellard | #if defined (TODO)
|
1151 | 3fc6c082 | bellard | /* PPC 403 GB */
|
1152 | 3fc6c082 | bellard | { |
1153 | 3fc6c082 | bellard | .name = "403gb",
|
1154 | 3fc6c082 | bellard | .pvr = CPU_PPC_403GB, |
1155 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFFF00,
|
1156 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_403, |
1157 | 3fc6c082 | bellard | .flags = PPC_FLAGS_403, |
1158 | 3fc6c082 | bellard | .msr_mask = 0x000000000007D23D,
|
1159 | 3fc6c082 | bellard | }, |
1160 | 3fc6c082 | bellard | #endif
|
1161 | 3fc6c082 | bellard | #if defined (TODO)
|
1162 | 3fc6c082 | bellard | /* PPC 403 GC */
|
1163 | 3fc6c082 | bellard | { |
1164 | 3fc6c082 | bellard | .name = "403gc",
|
1165 | 3fc6c082 | bellard | .pvr = CPU_PPC_403GC, |
1166 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFFF00,
|
1167 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_403, |
1168 | 3fc6c082 | bellard | .flags = PPC_FLAGS_403, |
1169 | 3fc6c082 | bellard | .msr_mask = 0x000000000007D23D,
|
1170 | 3fc6c082 | bellard | }, |
1171 | 3fc6c082 | bellard | #endif
|
1172 | 3fc6c082 | bellard | #if defined (TODO)
|
1173 | 3fc6c082 | bellard | /* PPC 403 GCX */
|
1174 | 3fc6c082 | bellard | { |
1175 | 3fc6c082 | bellard | .name = "403gcx",
|
1176 | 3fc6c082 | bellard | .pvr = CPU_PPC_403GCX, |
1177 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFFF00,
|
1178 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_403, |
1179 | 3fc6c082 | bellard | .flags = PPC_FLAGS_403, |
1180 | 3fc6c082 | bellard | .msr_mask = 0x000000000007D23D,
|
1181 | 3fc6c082 | bellard | }, |
1182 | 3fc6c082 | bellard | #endif
|
1183 | 3fc6c082 | bellard | #if defined (TODO)
|
1184 | 3fc6c082 | bellard | /* PPC 405 CR */
|
1185 | 3fc6c082 | bellard | { |
1186 | 3fc6c082 | bellard | .name = "405cr",
|
1187 | 3fc6c082 | bellard | .pvr = CPU_PPC_405, |
1188 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1189 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1190 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1191 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1192 | 3fc6c082 | bellard | }, |
1193 | 3fc6c082 | bellard | #endif
|
1194 | 3fc6c082 | bellard | #if defined (TODO)
|
1195 | 3fc6c082 | bellard | /* PPC 405 GP */
|
1196 | 3fc6c082 | bellard | { |
1197 | 3fc6c082 | bellard | .name = "405gp",
|
1198 | 3fc6c082 | bellard | .pvr = CPU_PPC_405, |
1199 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1200 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1201 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1202 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1203 | 3fc6c082 | bellard | }, |
1204 | 3fc6c082 | bellard | #endif
|
1205 | 3fc6c082 | bellard | #if defined (TODO)
|
1206 | 3fc6c082 | bellard | /* PPC 405 EP */
|
1207 | 3fc6c082 | bellard | { |
1208 | 3fc6c082 | bellard | .name = "405ep",
|
1209 | 3fc6c082 | bellard | .pvr = CPU_PPC_405EP, |
1210 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1211 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1212 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1213 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1214 | 3fc6c082 | bellard | }, |
1215 | 3fc6c082 | bellard | #endif
|
1216 | 3fc6c082 | bellard | #if defined (TODO)
|
1217 | 3fc6c082 | bellard | /* PPC 405 GPR */
|
1218 | 3fc6c082 | bellard | { |
1219 | 3fc6c082 | bellard | .name = "405gpr",
|
1220 | 3fc6c082 | bellard | .pvr = CPU_PPC_405GPR, |
1221 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1222 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1223 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1224 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1225 | 3fc6c082 | bellard | }, |
1226 | 3fc6c082 | bellard | #endif
|
1227 | 3fc6c082 | bellard | #if defined (TODO)
|
1228 | 3fc6c082 | bellard | /* PPC 405 D2 */
|
1229 | 3fc6c082 | bellard | { |
1230 | 3fc6c082 | bellard | .name = "405d2",
|
1231 | 3fc6c082 | bellard | .pvr = CPU_PPC_405D2, |
1232 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1233 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1234 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1235 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1236 | 3fc6c082 | bellard | }, |
1237 | 3fc6c082 | bellard | #endif
|
1238 | 3fc6c082 | bellard | #if defined (TODO)
|
1239 | 3fc6c082 | bellard | /* PPC 405 D4 */
|
1240 | 3fc6c082 | bellard | { |
1241 | 3fc6c082 | bellard | .name = "405d4",
|
1242 | 3fc6c082 | bellard | .pvr = CPU_PPC_405D4, |
1243 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1244 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1245 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1246 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1247 | 3fc6c082 | bellard | }, |
1248 | 3fc6c082 | bellard | #endif
|
1249 | 3fc6c082 | bellard | #if defined (TODO)
|
1250 | 3fc6c082 | bellard | /* Npe405 H */
|
1251 | 3fc6c082 | bellard | { |
1252 | 3fc6c082 | bellard | .name = "Npe405H",
|
1253 | 3fc6c082 | bellard | .pvr = CPU_PPC_NPE405H, |
1254 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1255 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1256 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1257 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1258 | 3fc6c082 | bellard | }, |
1259 | 3fc6c082 | bellard | #endif
|
1260 | 3fc6c082 | bellard | #if defined (TODO)
|
1261 | 3fc6c082 | bellard | /* Npe405 L */
|
1262 | 3fc6c082 | bellard | { |
1263 | 3fc6c082 | bellard | .name = "Npe405L",
|
1264 | 3fc6c082 | bellard | .pvr = CPU_PPC_NPE405L, |
1265 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1266 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1267 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1268 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1269 | 3fc6c082 | bellard | }, |
1270 | 3fc6c082 | bellard | #endif
|
1271 | 3fc6c082 | bellard | #if defined (TODO)
|
1272 | 3fc6c082 | bellard | /* STB03xx */
|
1273 | 3fc6c082 | bellard | { |
1274 | 3fc6c082 | bellard | .name = "STB03",
|
1275 | 3fc6c082 | bellard | .pvr = CPU_PPC_STB03, |
1276 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1277 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1278 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1279 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1280 | 3fc6c082 | bellard | }, |
1281 | 3fc6c082 | bellard | #endif
|
1282 | 3fc6c082 | bellard | #if defined (TODO)
|
1283 | 3fc6c082 | bellard | /* STB04xx */
|
1284 | 3fc6c082 | bellard | { |
1285 | 3fc6c082 | bellard | .name = "STB04",
|
1286 | 3fc6c082 | bellard | .pvr = CPU_PPC_STB04, |
1287 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1288 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1289 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1290 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1291 | 3fc6c082 | bellard | }, |
1292 | 3fc6c082 | bellard | #endif
|
1293 | 3fc6c082 | bellard | #if defined (TODO)
|
1294 | 3fc6c082 | bellard | /* STB25xx */
|
1295 | 3fc6c082 | bellard | { |
1296 | 3fc6c082 | bellard | .name = "STB25",
|
1297 | 3fc6c082 | bellard | .pvr = CPU_PPC_STB25, |
1298 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1299 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1300 | 3fc6c082 | bellard | .flags = PPC_FLAGS_405, |
1301 | 3fc6c082 | bellard | .msr_mask = 0x00000000020EFF30,
|
1302 | 3fc6c082 | bellard | }, |
1303 | 3fc6c082 | bellard | #endif
|
1304 | 3fc6c082 | bellard | #if defined (TODO)
|
1305 | 3fc6c082 | bellard | /* PPC 440 EP */
|
1306 | 3fc6c082 | bellard | { |
1307 | 3fc6c082 | bellard | .name = "440ep",
|
1308 | 3fc6c082 | bellard | .pvr = CPU_PPC_440EP, |
1309 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1310 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_440, |
1311 | 3fc6c082 | bellard | .flags = PPC_FLAGS_440, |
1312 | 3fc6c082 | bellard | .msr_mask = 0x000000000006D630,
|
1313 | 3fc6c082 | bellard | }, |
1314 | 3fc6c082 | bellard | #endif
|
1315 | 3fc6c082 | bellard | #if defined (TODO)
|
1316 | 3fc6c082 | bellard | /* PPC 440 GP */
|
1317 | 3fc6c082 | bellard | { |
1318 | 3fc6c082 | bellard | .name = "440gp",
|
1319 | 3fc6c082 | bellard | .pvr = CPU_PPC_440GP, |
1320 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFFF00,
|
1321 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_440, |
1322 | 3fc6c082 | bellard | .flags = PPC_FLAGS_440, |
1323 | 3fc6c082 | bellard | .msr_mask = 0x000000000006D630,
|
1324 | 3fc6c082 | bellard | }, |
1325 | 3fc6c082 | bellard | #endif
|
1326 | 3fc6c082 | bellard | #if defined (TODO)
|
1327 | 3fc6c082 | bellard | /* PPC 440 GX */
|
1328 | 3fc6c082 | bellard | { |
1329 | 3fc6c082 | bellard | .name = "440gx",
|
1330 | 3fc6c082 | bellard | .pvr = CPU_PPC_440GX, |
1331 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1332 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_405, |
1333 | 3fc6c082 | bellard | .flags = PPC_FLAGS_440, |
1334 | 3fc6c082 | bellard | .msr_mask = 0x000000000006D630,
|
1335 | 3fc6c082 | bellard | }, |
1336 | 3fc6c082 | bellard | #endif
|
1337 | 3fc6c082 | bellard | |
1338 | 3fc6c082 | bellard | /* 32 bits "classic" powerpc */
|
1339 | 3fc6c082 | bellard | #if defined (TODO)
|
1340 | 3fc6c082 | bellard | /* PPC 601 */
|
1341 | 3fc6c082 | bellard | { |
1342 | 3fc6c082 | bellard | .name = "601",
|
1343 | 3fc6c082 | bellard | .pvr = CPU_PPC_601, |
1344 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1345 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_601, |
1346 | 3fc6c082 | bellard | .flags = PPC_FLAGS_601, |
1347 | 3fc6c082 | bellard | .msr_mask = 0x000000000000FD70,
|
1348 | 3fc6c082 | bellard | }, |
1349 | 3fc6c082 | bellard | #endif
|
1350 | 3fc6c082 | bellard | #if defined (TODO)
|
1351 | 3fc6c082 | bellard | /* PPC 602 */
|
1352 | 3fc6c082 | bellard | { |
1353 | 3fc6c082 | bellard | .name = "602",
|
1354 | 3fc6c082 | bellard | .pvr = CPU_PPC_602, |
1355 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1356 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_602, |
1357 | 3fc6c082 | bellard | .flags = PPC_FLAGS_602, |
1358 | 3fc6c082 | bellard | .msr_mask = 0x0000000000C7FF73,
|
1359 | 3fc6c082 | bellard | }, |
1360 | 3fc6c082 | bellard | #endif
|
1361 | 3fc6c082 | bellard | #if defined (TODO)
|
1362 | 3fc6c082 | bellard | /* PPC 603 */
|
1363 | 3fc6c082 | bellard | { |
1364 | 3fc6c082 | bellard | .name = "603",
|
1365 | 3fc6c082 | bellard | .pvr = CPU_PPC_603, |
1366 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1367 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_603, |
1368 | 3fc6c082 | bellard | .flags = PPC_FLAGS_603, |
1369 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF73,
|
1370 | 3fc6c082 | bellard | }, |
1371 | 3fc6c082 | bellard | #endif
|
1372 | 3fc6c082 | bellard | #if defined (TODO)
|
1373 | 3fc6c082 | bellard | /* PPC 603e */
|
1374 | 3fc6c082 | bellard | { |
1375 | 3fc6c082 | bellard | .name = "603e",
|
1376 | 3fc6c082 | bellard | .pvr = CPU_PPC_603E, |
1377 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1378 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_603, |
1379 | 3fc6c082 | bellard | .flags = PPC_FLAGS_603, |
1380 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF73,
|
1381 | 3fc6c082 | bellard | }, |
1382 | 3fc6c082 | bellard | { |
1383 | 3fc6c082 | bellard | .name = "Stretch",
|
1384 | 3fc6c082 | bellard | .pvr = CPU_PPC_603E, |
1385 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1386 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_603, |
1387 | 3fc6c082 | bellard | .flags = PPC_FLAGS_603, |
1388 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF73,
|
1389 | 3fc6c082 | bellard | }, |
1390 | 3fc6c082 | bellard | #endif
|
1391 | 3fc6c082 | bellard | #if defined (TODO)
|
1392 | 3fc6c082 | bellard | /* PPC 603ev */
|
1393 | 3fc6c082 | bellard | { |
1394 | 3fc6c082 | bellard | .name = "603ev",
|
1395 | 3fc6c082 | bellard | .pvr = CPU_PPC_603EV, |
1396 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1397 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_603, |
1398 | 3fc6c082 | bellard | .flags = PPC_FLAGS_603, |
1399 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF73,
|
1400 | 3fc6c082 | bellard | }, |
1401 | 3fc6c082 | bellard | #endif
|
1402 | 3fc6c082 | bellard | #if defined (TODO)
|
1403 | 3fc6c082 | bellard | /* PPC 603r */
|
1404 | 3fc6c082 | bellard | { |
1405 | 3fc6c082 | bellard | .name = "603r",
|
1406 | 3fc6c082 | bellard | .pvr = CPU_PPC_603R, |
1407 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1408 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_603, |
1409 | 3fc6c082 | bellard | .flags = PPC_FLAGS_603, |
1410 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF73,
|
1411 | 3fc6c082 | bellard | }, |
1412 | 3fc6c082 | bellard | { |
1413 | 3fc6c082 | bellard | .name = "Goldeneye",
|
1414 | 3fc6c082 | bellard | .pvr = CPU_PPC_603R, |
1415 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1416 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_603, |
1417 | 3fc6c082 | bellard | .flags = PPC_FLAGS_603, |
1418 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF73,
|
1419 | 3fc6c082 | bellard | }, |
1420 | 3fc6c082 | bellard | #endif
|
1421 | 3fc6c082 | bellard | #if defined (TODO)
|
1422 | 3fc6c082 | bellard | /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
|
1423 | 3fc6c082 | bellard | { |
1424 | 3fc6c082 | bellard | .name = "G2",
|
1425 | 3fc6c082 | bellard | .pvr = CPU_PPC_G2, |
1426 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1427 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_G2, |
1428 | 3fc6c082 | bellard | .flags = PPC_FLAGS_G2, |
1429 | 3fc6c082 | bellard | .msr_mask = 0x000000000006FFF2,
|
1430 | 3fc6c082 | bellard | }, |
1431 | 3fc6c082 | bellard | { /* Same as G2, with LE mode support */
|
1432 | 3fc6c082 | bellard | .name = "G2le",
|
1433 | 3fc6c082 | bellard | .pvr = CPU_PPC_G2LE, |
1434 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1435 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_G2, |
1436 | 3fc6c082 | bellard | .flags = PPC_FLAGS_G2, |
1437 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FFF3,
|
1438 | 3fc6c082 | bellard | }, |
1439 | 3fc6c082 | bellard | #endif
|
1440 | 3fc6c082 | bellard | /* PPC 604 */
|
1441 | 3fc6c082 | bellard | { |
1442 | 3fc6c082 | bellard | .name = "604",
|
1443 | 3fc6c082 | bellard | .pvr = CPU_PPC_604, |
1444 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1445 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_604, |
1446 | 3fc6c082 | bellard | .flags = PPC_FLAGS_604, |
1447 | 3fc6c082 | bellard | .msr_mask = 0x000000000005FF77,
|
1448 | 3fc6c082 | bellard | }, |
1449 | 3fc6c082 | bellard | /* PPC 604e */
|
1450 | 3fc6c082 | bellard | { |
1451 | 3fc6c082 | bellard | .name = "604e",
|
1452 | 3fc6c082 | bellard | .pvr = CPU_PPC_604E, |
1453 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1454 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_604, |
1455 | 3fc6c082 | bellard | .flags = PPC_FLAGS_604, |
1456 | 3fc6c082 | bellard | .msr_mask = 0x000000000005FF77,
|
1457 | 3fc6c082 | bellard | }, |
1458 | 3fc6c082 | bellard | /* PPC 604r */
|
1459 | 3fc6c082 | bellard | { |
1460 | 3fc6c082 | bellard | .name = "604r",
|
1461 | 3fc6c082 | bellard | .pvr = CPU_PPC_604R, |
1462 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1463 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_604, |
1464 | 3fc6c082 | bellard | .flags = PPC_FLAGS_604, |
1465 | 3fc6c082 | bellard | .msr_mask = 0x000000000005FF77,
|
1466 | 3fc6c082 | bellard | }, |
1467 | 3fc6c082 | bellard | /* generic G3 */
|
1468 | 3fc6c082 | bellard | { |
1469 | 3fc6c082 | bellard | .name = "G3",
|
1470 | 3fc6c082 | bellard | .pvr = CPU_PPC_74x, |
1471 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1472 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1473 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1474 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1475 | 3fc6c082 | bellard | }, |
1476 | 3fc6c082 | bellard | #if defined (TODO)
|
1477 | 3fc6c082 | bellard | /* MPC740 (G3) */
|
1478 | 3fc6c082 | bellard | { |
1479 | 3fc6c082 | bellard | .name = "740",
|
1480 | 3fc6c082 | bellard | .pvr = CPU_PPC_74x, |
1481 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1482 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1483 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1484 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1485 | 3fc6c082 | bellard | }, |
1486 | 3fc6c082 | bellard | { |
1487 | 3fc6c082 | bellard | .name = "Arthur",
|
1488 | 3fc6c082 | bellard | .pvr = CPU_PPC_74x, |
1489 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1490 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1491 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1492 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1493 | 3fc6c082 | bellard | }, |
1494 | 3fc6c082 | bellard | #endif
|
1495 | 3fc6c082 | bellard | #if defined (TODO)
|
1496 | 3fc6c082 | bellard | /* MPC745 (G3) */
|
1497 | 3fc6c082 | bellard | { |
1498 | 3fc6c082 | bellard | .name = "745",
|
1499 | 3fc6c082 | bellard | .pvr = CPU_PPC_74x, |
1500 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1501 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x5, |
1502 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x5, |
1503 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1504 | 3fc6c082 | bellard | }, |
1505 | 3fc6c082 | bellard | { |
1506 | 3fc6c082 | bellard | .name = "Goldfinger",
|
1507 | 3fc6c082 | bellard | .pvr = CPU_PPC_74x, |
1508 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1509 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x5, |
1510 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x5, |
1511 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1512 | 3fc6c082 | bellard | }, |
1513 | 3fc6c082 | bellard | #endif
|
1514 | 3fc6c082 | bellard | /* MPC750 (G3) */
|
1515 | 3fc6c082 | bellard | { |
1516 | 3fc6c082 | bellard | .name = "750",
|
1517 | 3fc6c082 | bellard | .pvr = CPU_PPC_74x, |
1518 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1519 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1520 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1521 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1522 | 3fc6c082 | bellard | }, |
1523 | 3fc6c082 | bellard | #if defined (TODO)
|
1524 | 3fc6c082 | bellard | /* MPC755 (G3) */
|
1525 | 3fc6c082 | bellard | { |
1526 | 3fc6c082 | bellard | .name = "755",
|
1527 | 3fc6c082 | bellard | .pvr = CPU_PPC_755, |
1528 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1529 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x5, |
1530 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x5, |
1531 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1532 | 3fc6c082 | bellard | }, |
1533 | 3fc6c082 | bellard | #endif
|
1534 | 3fc6c082 | bellard | #if defined (TODO)
|
1535 | 3fc6c082 | bellard | /* MPC740P (G3) */
|
1536 | 3fc6c082 | bellard | { |
1537 | 3fc6c082 | bellard | .name = "740p",
|
1538 | 3fc6c082 | bellard | .pvr = CPU_PPC_74xP, |
1539 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1540 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1541 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1542 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1543 | 3fc6c082 | bellard | }, |
1544 | 3fc6c082 | bellard | { |
1545 | 3fc6c082 | bellard | .name = "Conan/Doyle",
|
1546 | 3fc6c082 | bellard | .pvr = CPU_PPC_74xP, |
1547 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1548 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1549 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1550 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1551 | 3fc6c082 | bellard | }, |
1552 | 3fc6c082 | bellard | #endif
|
1553 | 3fc6c082 | bellard | #if defined (TODO)
|
1554 | 3fc6c082 | bellard | /* MPC745P (G3) */
|
1555 | 3fc6c082 | bellard | { |
1556 | 3fc6c082 | bellard | .name = "745p",
|
1557 | 3fc6c082 | bellard | .pvr = CPU_PPC_74xP, |
1558 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1559 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x5, |
1560 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x5, |
1561 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1562 | 3fc6c082 | bellard | }, |
1563 | 3fc6c082 | bellard | #endif
|
1564 | 3fc6c082 | bellard | /* MPC750P (G3) */
|
1565 | 3fc6c082 | bellard | { |
1566 | 3fc6c082 | bellard | .name = "750p",
|
1567 | 3fc6c082 | bellard | .pvr = CPU_PPC_74xP, |
1568 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1569 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1570 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1571 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1572 | 3fc6c082 | bellard | }, |
1573 | 3fc6c082 | bellard | #if defined (TODO)
|
1574 | 3fc6c082 | bellard | /* MPC755P (G3) */
|
1575 | 3fc6c082 | bellard | { |
1576 | 3fc6c082 | bellard | .name = "755p",
|
1577 | 3fc6c082 | bellard | .pvr = CPU_PPC_74xP, |
1578 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1579 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x5, |
1580 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x5, |
1581 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1582 | 3fc6c082 | bellard | }, |
1583 | 3fc6c082 | bellard | #endif
|
1584 | 3fc6c082 | bellard | /* IBM 750CXe (G3 embedded) */
|
1585 | 3fc6c082 | bellard | { |
1586 | 3fc6c082 | bellard | .name = "750cxe",
|
1587 | 3fc6c082 | bellard | .pvr = CPU_PPC_750CXE, |
1588 | 3fc6c082 | bellard | .pvr_mask = 0xFFFFF000,
|
1589 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1590 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1591 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1592 | 3fc6c082 | bellard | }, |
1593 | 3fc6c082 | bellard | /* IBM 750FX (G3 embedded) */
|
1594 | 3fc6c082 | bellard | { |
1595 | 3fc6c082 | bellard | .name = "750fx",
|
1596 | 3fc6c082 | bellard | .pvr = CPU_PPC_750FX, |
1597 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1598 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1599 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1600 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1601 | 3fc6c082 | bellard | }, |
1602 | 3fc6c082 | bellard | /* IBM 750GX (G3 embedded) */
|
1603 | 3fc6c082 | bellard | { |
1604 | 3fc6c082 | bellard | .name = "750gx",
|
1605 | 3fc6c082 | bellard | .pvr = CPU_PPC_750GX, |
1606 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1607 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_7x0, |
1608 | 3fc6c082 | bellard | .flags = PPC_FLAGS_7x0, |
1609 | 3fc6c082 | bellard | .msr_mask = 0x000000000007FF77,
|
1610 | 3fc6c082 | bellard | }, |
1611 | 3fc6c082 | bellard | #if defined (TODO)
|
1612 | 3fc6c082 | bellard | /* generic G4 */
|
1613 | 3fc6c082 | bellard | { |
1614 | 3fc6c082 | bellard | .name = "G4",
|
1615 | 3fc6c082 | bellard | .pvr = CPU_PPC_7400, |
1616 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1617 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1618 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1619 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1620 | 3fc6c082 | bellard | }, |
1621 | 3fc6c082 | bellard | #endif
|
1622 | 3fc6c082 | bellard | #if defined (TODO)
|
1623 | 3fc6c082 | bellard | /* PPC 7400 (G4) */
|
1624 | 3fc6c082 | bellard | { |
1625 | 3fc6c082 | bellard | .name = "7400",
|
1626 | 3fc6c082 | bellard | .pvr = CPU_PPC_7400, |
1627 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1628 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1629 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1630 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1631 | 3fc6c082 | bellard | }, |
1632 | 3fc6c082 | bellard | { |
1633 | 3fc6c082 | bellard | .name = "Max",
|
1634 | 3fc6c082 | bellard | .pvr = CPU_PPC_7400, |
1635 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1636 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1637 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1638 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1639 | 3fc6c082 | bellard | }, |
1640 | 3fc6c082 | bellard | #endif
|
1641 | 3fc6c082 | bellard | #if defined (TODO)
|
1642 | 3fc6c082 | bellard | /* PPC 7410 (G4) */
|
1643 | 3fc6c082 | bellard | { |
1644 | 3fc6c082 | bellard | .name = "7410",
|
1645 | 3fc6c082 | bellard | .pvr = CPU_PPC_7410, |
1646 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1647 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1648 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1649 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1650 | 3fc6c082 | bellard | }, |
1651 | 3fc6c082 | bellard | { |
1652 | 3fc6c082 | bellard | .name = "Nitro",
|
1653 | 3fc6c082 | bellard | .pvr = CPU_PPC_7410, |
1654 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1655 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1656 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1657 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1658 | 3fc6c082 | bellard | }, |
1659 | 3fc6c082 | bellard | #endif
|
1660 | 3fc6c082 | bellard | /* XXX: 7441 */
|
1661 | 3fc6c082 | bellard | /* XXX: 7445 */
|
1662 | 3fc6c082 | bellard | /* XXX: 7447 */
|
1663 | 3fc6c082 | bellard | /* XXX: 7447A */
|
1664 | 3fc6c082 | bellard | #if defined (TODO)
|
1665 | 3fc6c082 | bellard | /* PPC 7450 (G4) */
|
1666 | 3fc6c082 | bellard | { |
1667 | 3fc6c082 | bellard | .name = "7450",
|
1668 | 3fc6c082 | bellard | .pvr = CPU_PPC_7450, |
1669 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1670 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1671 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1672 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1673 | 3fc6c082 | bellard | }, |
1674 | 3fc6c082 | bellard | { |
1675 | 3fc6c082 | bellard | .name = "Vger",
|
1676 | 3fc6c082 | bellard | .pvr = CPU_PPC_7450, |
1677 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1678 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1679 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1680 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1681 | 3fc6c082 | bellard | }, |
1682 | 3fc6c082 | bellard | #endif
|
1683 | 3fc6c082 | bellard | /* XXX: 7451 */
|
1684 | 3fc6c082 | bellard | #if defined (TODO)
|
1685 | 3fc6c082 | bellard | /* PPC 7455 (G4) */
|
1686 | 3fc6c082 | bellard | { |
1687 | 3fc6c082 | bellard | .name = "7455",
|
1688 | 3fc6c082 | bellard | .pvr = CPU_PPC_7455, |
1689 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1690 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1691 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1692 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1693 | 3fc6c082 | bellard | }, |
1694 | 3fc6c082 | bellard | { |
1695 | 3fc6c082 | bellard | .name = "Apollo 6",
|
1696 | 3fc6c082 | bellard | .pvr = CPU_PPC_7455, |
1697 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1698 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1699 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1700 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1701 | 3fc6c082 | bellard | }, |
1702 | 3fc6c082 | bellard | #endif
|
1703 | 3fc6c082 | bellard | #if defined (TODO)
|
1704 | 3fc6c082 | bellard | /* PPC 7457 (G4) */
|
1705 | 3fc6c082 | bellard | { |
1706 | 3fc6c082 | bellard | .name = "7457",
|
1707 | 3fc6c082 | bellard | .pvr = CPU_PPC_7457, |
1708 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1709 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1710 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1711 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1712 | 3fc6c082 | bellard | }, |
1713 | 3fc6c082 | bellard | { |
1714 | 3fc6c082 | bellard | .name = "Apollo 7",
|
1715 | 3fc6c082 | bellard | .pvr = CPU_PPC_7457, |
1716 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1717 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1718 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1719 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1720 | 3fc6c082 | bellard | }, |
1721 | 3fc6c082 | bellard | #endif
|
1722 | 3fc6c082 | bellard | #if defined (TODO)
|
1723 | 3fc6c082 | bellard | /* PPC 7457A (G4) */
|
1724 | 3fc6c082 | bellard | { |
1725 | 3fc6c082 | bellard | .name = "7457A",
|
1726 | 3fc6c082 | bellard | .pvr = CPU_PPC_7457A, |
1727 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1728 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1729 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1730 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1731 | 3fc6c082 | bellard | }, |
1732 | 3fc6c082 | bellard | { |
1733 | 3fc6c082 | bellard | .name = "Apollo 7 PM",
|
1734 | 3fc6c082 | bellard | .pvr = CPU_PPC_7457A, |
1735 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1736 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_74xx, |
1737 | 3fc6c082 | bellard | .flags = PPC_FLAGS_74xx, |
1738 | 3fc6c082 | bellard | .msr_mask = 0x000000000205FF77,
|
1739 | 3fc6c082 | bellard | }, |
1740 | 3fc6c082 | bellard | #endif
|
1741 | 3fc6c082 | bellard | /* 64 bits PPC */
|
1742 | 3fc6c082 | bellard | #if defined (TODO)
|
1743 | 3fc6c082 | bellard | /* PPC 620 */
|
1744 | 3fc6c082 | bellard | { |
1745 | 3fc6c082 | bellard | .name = "620",
|
1746 | 3fc6c082 | bellard | .pvr = CPU_PPC_620, |
1747 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1748 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_620, |
1749 | 3fc6c082 | bellard | .flags = PPC_FLAGS_620, |
1750 | 3fc6c082 | bellard | .msr_mask = 0x800000000005FF73,
|
1751 | 3fc6c082 | bellard | }, |
1752 | 3fc6c082 | bellard | #endif
|
1753 | 3fc6c082 | bellard | #if defined (TODO)
|
1754 | 3fc6c082 | bellard | /* PPC 630 (POWER3) */
|
1755 | 3fc6c082 | bellard | { |
1756 | 3fc6c082 | bellard | .name = "630",
|
1757 | 3fc6c082 | bellard | .pvr = CPU_PPC_630, |
1758 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1759 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_630, |
1760 | 3fc6c082 | bellard | .flags = PPC_FLAGS_630, |
1761 | 3fc6c082 | bellard | .msr_mask = xxx, |
1762 | 3fc6c082 | bellard | } |
1763 | 3fc6c082 | bellard | { |
1764 | 3fc6c082 | bellard | .name = "POWER3",
|
1765 | 3fc6c082 | bellard | .pvr = CPU_PPC_630, |
1766 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1767 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_630, |
1768 | 3fc6c082 | bellard | .flags = PPC_FLAGS_630, |
1769 | 3fc6c082 | bellard | .msr_mask = xxx, |
1770 | 3fc6c082 | bellard | } |
1771 | 3fc6c082 | bellard | #endif
|
1772 | 3fc6c082 | bellard | #if defined (TODO)
|
1773 | 3fc6c082 | bellard | /* PPC 631 (Power 3+)*/
|
1774 | 3fc6c082 | bellard | { |
1775 | 3fc6c082 | bellard | .name = "631",
|
1776 | 3fc6c082 | bellard | .pvr = CPU_PPC_631, |
1777 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1778 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_631, |
1779 | 3fc6c082 | bellard | .flags = PPC_FLAGS_631, |
1780 | 3fc6c082 | bellard | .msr_mask = xxx, |
1781 | 3fc6c082 | bellard | }, |
1782 | 3fc6c082 | bellard | { |
1783 | 3fc6c082 | bellard | .name = "POWER3+",
|
1784 | 3fc6c082 | bellard | .pvr = CPU_PPC_631, |
1785 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1786 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_631, |
1787 | 3fc6c082 | bellard | .flags = PPC_FLAGS_631, |
1788 | 3fc6c082 | bellard | .msr_mask = xxx, |
1789 | 3fc6c082 | bellard | }, |
1790 | 3fc6c082 | bellard | #endif
|
1791 | 3fc6c082 | bellard | #if defined (TODO)
|
1792 | 3fc6c082 | bellard | /* POWER4 */
|
1793 | 3fc6c082 | bellard | { |
1794 | 3fc6c082 | bellard | .name = "POWER4",
|
1795 | 3fc6c082 | bellard | .pvr = CPU_PPC_POWER4, |
1796 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1797 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_POWER4, |
1798 | 3fc6c082 | bellard | .flags = PPC_FLAGS_POWER4, |
1799 | 3fc6c082 | bellard | .msr_mask = xxx, |
1800 | 3fc6c082 | bellard | }, |
1801 | 3fc6c082 | bellard | #endif
|
1802 | 3fc6c082 | bellard | #if defined (TODO)
|
1803 | 3fc6c082 | bellard | /* POWER4p */
|
1804 | 3fc6c082 | bellard | { |
1805 | 3fc6c082 | bellard | .name = "POWER4+",
|
1806 | 3fc6c082 | bellard | .pvr = CPU_PPC_POWER4P, |
1807 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1808 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_POWER4, |
1809 | 3fc6c082 | bellard | .flags = PPC_FLAGS_POWER4, |
1810 | 3fc6c082 | bellard | .msr_mask = xxx, |
1811 | 3fc6c082 | bellard | }, |
1812 | 3fc6c082 | bellard | #endif
|
1813 | 3fc6c082 | bellard | #if defined (TODO)
|
1814 | 3fc6c082 | bellard | /* POWER5 */
|
1815 | 3fc6c082 | bellard | { |
1816 | 3fc6c082 | bellard | .name = "POWER5",
|
1817 | 3fc6c082 | bellard | .pvr = CPU_PPC_POWER5, |
1818 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1819 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_POWER5, |
1820 | 3fc6c082 | bellard | .flags = PPC_FLAGS_POWER5, |
1821 | 3fc6c082 | bellard | .msr_mask = xxx, |
1822 | 3fc6c082 | bellard | }, |
1823 | 3fc6c082 | bellard | #endif
|
1824 | 3fc6c082 | bellard | #if defined (TODO)
|
1825 | 3fc6c082 | bellard | /* POWER5+ */
|
1826 | 3fc6c082 | bellard | { |
1827 | 3fc6c082 | bellard | .name = "POWER5+",
|
1828 | 3fc6c082 | bellard | .pvr = CPU_PPC_POWER5P, |
1829 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1830 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_POWER5, |
1831 | 3fc6c082 | bellard | .flags = PPC_FLAGS_POWER5, |
1832 | 3fc6c082 | bellard | .msr_mask = xxx, |
1833 | 3fc6c082 | bellard | }, |
1834 | 3fc6c082 | bellard | #endif
|
1835 | 3fc6c082 | bellard | #if defined (TODO)
|
1836 | 3fc6c082 | bellard | /* PPC 970 */
|
1837 | 3fc6c082 | bellard | { |
1838 | 3fc6c082 | bellard | .name = "970",
|
1839 | 3fc6c082 | bellard | .pvr = CPU_PPC_970, |
1840 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1841 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_970, |
1842 | 3fc6c082 | bellard | .flags = PPC_FLAGS_970, |
1843 | 3fc6c082 | bellard | .msr_mask = 0x900000000204FF36,
|
1844 | 3fc6c082 | bellard | }, |
1845 | 3fc6c082 | bellard | #endif
|
1846 | 3fc6c082 | bellard | #if defined (TODO)
|
1847 | 3fc6c082 | bellard | /* PPC 970FX (G5) */
|
1848 | 3fc6c082 | bellard | { |
1849 | 3fc6c082 | bellard | .name = "970fx",
|
1850 | 3fc6c082 | bellard | .pvr = CPU_PPC_970FX, |
1851 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1852 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_970FX, |
1853 | 3fc6c082 | bellard | .flags = PPC_FLAGS_970FX, |
1854 | 3fc6c082 | bellard | .msr_mask = 0x800000000204FF36,
|
1855 | 3fc6c082 | bellard | }, |
1856 | 3fc6c082 | bellard | #endif
|
1857 | 3fc6c082 | bellard | #if defined (TODO)
|
1858 | 3fc6c082 | bellard | /* RS64 (Apache/A35) */
|
1859 | 3fc6c082 | bellard | /* This one seems to support the whole POWER2 instruction set
|
1860 | 3fc6c082 | bellard | * and the PowerPC 64 one.
|
1861 | 3fc6c082 | bellard | */
|
1862 | 3fc6c082 | bellard | { |
1863 | 3fc6c082 | bellard | .name = "RS64",
|
1864 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64, |
1865 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1866 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1867 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1868 | 3fc6c082 | bellard | .msr_mask = xxx, |
1869 | 3fc6c082 | bellard | }, |
1870 | 3fc6c082 | bellard | { |
1871 | 3fc6c082 | bellard | .name = "Apache",
|
1872 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64, |
1873 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1874 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1875 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1876 | 3fc6c082 | bellard | .msr_mask = xxx, |
1877 | 3fc6c082 | bellard | }, |
1878 | 3fc6c082 | bellard | { |
1879 | 3fc6c082 | bellard | .name = "A35",
|
1880 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64, |
1881 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1882 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1883 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1884 | 3fc6c082 | bellard | .msr_mask = xxx, |
1885 | 3fc6c082 | bellard | }, |
1886 | 3fc6c082 | bellard | #endif
|
1887 | 3fc6c082 | bellard | #if defined (TODO)
|
1888 | 3fc6c082 | bellard | /* RS64-II (NorthStar/A50) */
|
1889 | 3fc6c082 | bellard | { |
1890 | 3fc6c082 | bellard | .name = "RS64-II",
|
1891 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64II, |
1892 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1893 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1894 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1895 | 3fc6c082 | bellard | .msr_mask = xxx, |
1896 | 3fc6c082 | bellard | }, |
1897 | 3fc6c082 | bellard | { |
1898 | 3fc6c082 | bellard | .name = "NortStar",
|
1899 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64II, |
1900 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1901 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1902 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1903 | 3fc6c082 | bellard | .msr_mask = xxx, |
1904 | 3fc6c082 | bellard | }, |
1905 | 3fc6c082 | bellard | { |
1906 | 3fc6c082 | bellard | .name = "A50",
|
1907 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64II, |
1908 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1909 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1910 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1911 | 3fc6c082 | bellard | .msr_mask = xxx, |
1912 | 3fc6c082 | bellard | }, |
1913 | 3fc6c082 | bellard | #endif
|
1914 | 3fc6c082 | bellard | #if defined (TODO)
|
1915 | 3fc6c082 | bellard | /* RS64-III (Pulsar) */
|
1916 | 3fc6c082 | bellard | { |
1917 | 3fc6c082 | bellard | .name = "RS64-III",
|
1918 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64III, |
1919 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1920 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1921 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1922 | 3fc6c082 | bellard | .msr_mask = xxx, |
1923 | 3fc6c082 | bellard | }, |
1924 | 3fc6c082 | bellard | { |
1925 | 3fc6c082 | bellard | .name = "Pulsar",
|
1926 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64III, |
1927 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1928 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1929 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1930 | 3fc6c082 | bellard | .msr_mask = xxx, |
1931 | 3fc6c082 | bellard | }, |
1932 | 3fc6c082 | bellard | #endif
|
1933 | 3fc6c082 | bellard | #if defined (TODO)
|
1934 | 3fc6c082 | bellard | /* RS64-IV (IceStar/IStar/SStar) */
|
1935 | 3fc6c082 | bellard | { |
1936 | 3fc6c082 | bellard | .name = "RS64-IV",
|
1937 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64IV, |
1938 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1939 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1940 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1941 | 3fc6c082 | bellard | .msr_mask = xxx, |
1942 | 3fc6c082 | bellard | }, |
1943 | 3fc6c082 | bellard | { |
1944 | 3fc6c082 | bellard | .name = "IceStar",
|
1945 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64IV, |
1946 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1947 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1948 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1949 | 3fc6c082 | bellard | .msr_mask = xxx, |
1950 | 3fc6c082 | bellard | }, |
1951 | 3fc6c082 | bellard | { |
1952 | 3fc6c082 | bellard | .name = "IStar",
|
1953 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64IV, |
1954 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1955 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1956 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1957 | 3fc6c082 | bellard | .msr_mask = xxx, |
1958 | 3fc6c082 | bellard | }, |
1959 | 3fc6c082 | bellard | { |
1960 | 3fc6c082 | bellard | .name = "SStar",
|
1961 | 3fc6c082 | bellard | .pvr = CPU_PPC_RS64IV, |
1962 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1963 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_RS64, |
1964 | 3fc6c082 | bellard | .flags = PPC_FLAGS_RS64, |
1965 | 3fc6c082 | bellard | .msr_mask = xxx, |
1966 | 3fc6c082 | bellard | }, |
1967 | 3fc6c082 | bellard | #endif
|
1968 | 3fc6c082 | bellard | /* POWER */
|
1969 | 3fc6c082 | bellard | #if defined (TODO)
|
1970 | 3fc6c082 | bellard | /* Original POWER */
|
1971 | 3fc6c082 | bellard | { |
1972 | 3fc6c082 | bellard | .name = "POWER",
|
1973 | 3fc6c082 | bellard | .pvr = CPU_POWER, |
1974 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1975 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_POWER, |
1976 | 3fc6c082 | bellard | .flags = PPC_FLAGS_POWER, |
1977 | 3fc6c082 | bellard | .msr_mask = xxx, |
1978 | 3fc6c082 | bellard | }, |
1979 | 3fc6c082 | bellard | #endif
|
1980 | 3fc6c082 | bellard | #if defined (TODO)
|
1981 | 3fc6c082 | bellard | /* POWER2 */
|
1982 | 3fc6c082 | bellard | { |
1983 | 3fc6c082 | bellard | .name = "POWER2",
|
1984 | 3fc6c082 | bellard | .pvr = CPU_POWER2, |
1985 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1986 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_POWER, |
1987 | 3fc6c082 | bellard | .flags = PPC_FLAGS_POWER, |
1988 | 3fc6c082 | bellard | .msr_mask = xxx, |
1989 | 3fc6c082 | bellard | }, |
1990 | 3fc6c082 | bellard | #endif
|
1991 | 3fc6c082 | bellard | /* Generic PowerPCs */
|
1992 | 3fc6c082 | bellard | #if defined (TODO)
|
1993 | 3fc6c082 | bellard | { |
1994 | 3fc6c082 | bellard | .name = "ppc64",
|
1995 | 3fc6c082 | bellard | .pvr = CPU_PPC_970, |
1996 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
1997 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_PPC64, |
1998 | 3fc6c082 | bellard | .flags = PPC_FLAGS_PPC64, |
1999 | 3fc6c082 | bellard | .msr_mask = 0xA00000000204FF36,
|
2000 | 3fc6c082 | bellard | }, |
2001 | 3fc6c082 | bellard | #endif
|
2002 | 3fc6c082 | bellard | { |
2003 | 3fc6c082 | bellard | .name = "ppc32",
|
2004 | 3fc6c082 | bellard | .pvr = CPU_PPC_604, |
2005 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
2006 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_PPC32, |
2007 | 3fc6c082 | bellard | .flags = PPC_FLAGS_PPC32, |
2008 | 3fc6c082 | bellard | .msr_mask = 0x000000000005FF77,
|
2009 | 3fc6c082 | bellard | }, |
2010 | 3fc6c082 | bellard | /* Fallback */
|
2011 | 3fc6c082 | bellard | { |
2012 | 3fc6c082 | bellard | .name = "ppc",
|
2013 | 3fc6c082 | bellard | .pvr = CPU_PPC_604, |
2014 | 3fc6c082 | bellard | .pvr_mask = 0xFFFF0000,
|
2015 | 3fc6c082 | bellard | .insns_flags = PPC_INSNS_PPC32, |
2016 | 3fc6c082 | bellard | .flags = PPC_FLAGS_PPC32, |
2017 | 3fc6c082 | bellard | .msr_mask = 0x000000000005FF77,
|
2018 | 3fc6c082 | bellard | }, |
2019 | 3fc6c082 | bellard | }; |
2020 | 3fc6c082 | bellard | |
2021 | 3fc6c082 | bellard | int ppc_find_by_name (const unsigned char *name, ppc_def_t **def) |
2022 | 3fc6c082 | bellard | { |
2023 | 3fc6c082 | bellard | int i, ret;
|
2024 | 3fc6c082 | bellard | |
2025 | 3fc6c082 | bellard | ret = -1;
|
2026 | 3fc6c082 | bellard | *def = NULL;
|
2027 | 3fc6c082 | bellard | for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) { |
2028 | 3fc6c082 | bellard | if (strcasecmp(name, ppc_defs[i].name) == 0) { |
2029 | 3fc6c082 | bellard | *def = &ppc_defs[i]; |
2030 | 3fc6c082 | bellard | ret = 0;
|
2031 | 3fc6c082 | bellard | break;
|
2032 | 3fc6c082 | bellard | } |
2033 | 3fc6c082 | bellard | } |
2034 | 3fc6c082 | bellard | |
2035 | 3fc6c082 | bellard | return ret;
|
2036 | 3fc6c082 | bellard | } |
2037 | 3fc6c082 | bellard | |
2038 | 3fc6c082 | bellard | int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
|
2039 | 3fc6c082 | bellard | { |
2040 | 3fc6c082 | bellard | int i, ret;
|
2041 | 3fc6c082 | bellard | |
2042 | 3fc6c082 | bellard | ret = -1;
|
2043 | 3fc6c082 | bellard | *def = NULL;
|
2044 | 3fc6c082 | bellard | for (i = 0; ppc_defs[i].name != NULL; i++) { |
2045 | 3fc6c082 | bellard | if ((pvr & ppc_defs[i].pvr_mask) ==
|
2046 | 3fc6c082 | bellard | (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) { |
2047 | 3fc6c082 | bellard | *def = &ppc_defs[i]; |
2048 | 3fc6c082 | bellard | ret = 0;
|
2049 | 3fc6c082 | bellard | break;
|
2050 | 3fc6c082 | bellard | } |
2051 | 3fc6c082 | bellard | } |
2052 | 3fc6c082 | bellard | |
2053 | 3fc6c082 | bellard | return ret;
|
2054 | 3fc6c082 | bellard | } |
2055 | 3fc6c082 | bellard | |
2056 | 3fc6c082 | bellard | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
2057 | 3fc6c082 | bellard | { |
2058 | 3fc6c082 | bellard | int i;
|
2059 | 3fc6c082 | bellard | |
2060 | 3fc6c082 | bellard | for (i = 0; ; i++) { |
2061 | 3fc6c082 | bellard | (*cpu_fprintf)(f, "PowerPC '%s' PVR %08x mask %08x\n",
|
2062 | 3fc6c082 | bellard | ppc_defs[i].name, |
2063 | 3fc6c082 | bellard | ppc_defs[i].pvr, ppc_defs[i].pvr_mask); |
2064 | 3fc6c082 | bellard | if (strcmp(ppc_defs[i].name, "ppc") == 0) |
2065 | 3fc6c082 | bellard | break;
|
2066 | 3fc6c082 | bellard | } |
2067 | 3fc6c082 | bellard | } |