Archipelago » qemu

    }

    ldebug (

        SW_NAME (sw),

        live, (((int64_t) live << 32) / sw->ratio) << sw->info.shift

        );

    dead = sw->hw->samples - live;

#ifdef DEBUG_OUT

           SW_NAME (sw),

           live, dead, (((int64_t) dead << 32) / sw->ratio) << sw->info.shift);

#endif

    cur_ts = sw->hw->ts_helper;

    old_ts = ts->old_ts;

    if (cur_ts >= old_ts) {

        delta = cur_ts - old_ts;

    bitmap_offset = 512 * s->pagetable[pagetable_index];

    block_offset = bitmap_offset + 512 + (512 * pageentry_index);

//	sector_num, pagetable_index, pageentry_index,

//	bitmap_offset, block_offset);

#elif TARGET_LONG_SIZE == 8

typedef int64_t target_long;

typedef uint64_t target_ulong;

#else

#error TARGET_LONG_SIZE undefined

#endif

    /* Actually, address between memaddr and memaddr + len was

       out of bounds.  */

    (*info->fprintf_func) (info->stream,

}

/* This could be in a separate file, to save miniscule amounts of space

     bfd_vma addr;

     struct disassemble_info *info;

{

}

/* Just return the given address.  */

{

    APICState *s = env->apic_state;

#ifdef DEBUG_APIC

#endif

    s->apicbase = (val & 0xfffff000) | 

        (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));

{

    APICState *s = env->apic_state;

#ifdef DEBUG_APIC

#endif

    return s->apicbase;

}

    }

#if 0

#ifdef DEBUG_CUDA

           s->latch, d, next_time - d);

#endif

#endif

    for (i = 0; i < 16; i++) {

        count = irq_count[i];

        if (count > 0)

    }

#endif

}

	next++;

#if 0

    if (logfile) {

                __func__, now, count, compare, next - now);

    }

#endif

                            );

                    }

                }

            }

            break;

		       s->periph_freq);

    if (next == now)

	next = now + 1;

    fprintf(stderr, "timer will underflow in %f seconds\n",

	    (float) (next - now) / (float) ticks_per_sec);

    for (i = 0; i < 32; i++) {

        count = s->irq_count[i];

        if (count > 0)

    }

#endif

}

    // Convert remaining counter ticks to CPU ticks

    s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);

    if (s->mode != 1)

	pic_set_irq_cpu(s->irq, out, s->cpu);

        perror("/tmp/kqemu.stats");

        exit(1);

    }

    sum = 0;

    for(i = 0; i < nb_pc_records; i++) {

        r = pr[i];

        sum += r->count;

                r->pc, 

                r->count, 

                (double)r->count / (double)total * 100.0,

            term_printf(" ");

            switch(format) {

            case 'o':

                break;

            case 'x':

                break;

            case 'u':

                break;

            case 'd':

                break;

            case 'c':

                term_printc(v);

#else

    switch(format) {

    case 'o':

        break;

    case 'x':

        break;

    case 'u':

        break;

    default:

    case 'd':

        break;

    case 'c':

        term_printc(val);

    total = qemu_time;

    if (total == 0)

        total = 1;

                dev_time, dev_time / (double)ticks_per_sec);

                qemu_time, qemu_time / (double)ticks_per_sec);

                kqemu_time, kqemu_time / (double)ticks_per_sec,

                kqemu_time / (double)total * 100.0,

                kqemu_exec_count,

      case typeDouble:

      {

         writeRegister(getRd(opcode),

	               float64_to_int32(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status));

      }

    v = (uint64_t)a1 * (uint64_t)b1;

    *phigh += v;

#ifdef DEBUG_MULDIV

           a, b, *phigh, *plow);

#endif

}

            a0 = (a0 << 1) | qb;

        }

#if defined(DEBUG_MULDIV)

               *phigh, *plow, b, a0, a1);

#endif

        *plow = a0;

#ifdef TARGET_X86_64

    if (env->hflags & HF_CS64_MASK) {

        cpu_fprintf(f, 

                    env->regs[R_EAX], 

                    env->regs[R_EBX], 

                    env->regs[R_ECX], 

    if (env->hflags & HF_LMA_MASK) {

        for(i = 0; i < 6; i++) {

            SegmentCache *sc = &env->segs[i];

                        seg_name[i],

                        sc->selector,

                        sc->base,

                        sc->limit,

                        sc->flags);

        }

                    env->ldt.selector,

                    env->ldt.base,

                    env->ldt.limit,

                    env->ldt.flags);

                    env->tr.selector,

                    env->tr.base,

                    env->tr.limit,

                    env->tr.flags);

                    env->gdt.base, env->gdt.limit);

                    env->idt.base, env->idt.limit);

                    (uint32_t)env->cr[0], 

                    env->cr[2], 

                    env->cr[3], 

            snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);

#ifdef TARGET_X86_64

        if (env->hflags & HF_CS64_MASK) {

                        env->cc_src, env->cc_dst, 

                        cc_op_name);

        } else 

                } l;

            } tmp;

            tmp.d = env->fpregs[i].d;

                        i, tmp.l.lower, tmp.l.upper);

#else

                        i, env->fpregs[i].mmx.q);

#endif

            if ((i & 1) == 1)

{

#if defined(TARGET_PPC64) || 1

#define FILL ""

#define RGPL  4

#define RFPL  4

#else

#define FILL "        "

#define RGPL  8

#define RFPL  4

#endif

    for (i = 0; i < 32; i++) {

        if ((i & (RFPL - 1)) == 0)

            cpu_fprintf(f, "FPR%02d", i);

        if ((i & (RFPL - 1)) == (RFPL - 1))

            cpu_fprintf(f, "\n");

    }

        exit(1);

    }

#if defined(PPC_DEBUG_SPR)

           (unsigned long long)initial_value);

#endif

    spr->name = name;

		env->dmmuregs[4] = address; /* Fault address register */

		env->exception_index = TT_DFAULT;

#ifdef DEBUG_MMU

#endif

		return 1;

	    }

	}

    }

#ifdef DEBUG_MMU

#endif

    env->exception_index = TT_DMISS;

    return 1;

		env->immuregs[3] |= (is_user << 3) | 1;

		env->exception_index = TT_TFAULT;

#ifdef DEBUG_MMU

#endif

		return 1;

	    }

	}

    }

#ifdef DEBUG_MMU

#endif

    env->exception_index = TT_TMISS;

    return 1;

	virt_addr = address & TARGET_PAGE_MASK;

	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));

#ifdef DEBUG_MMU

#endif

	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);

	return ret;

    unsigned int i;

    const char *mask;

    if ((env->lsu & DMMU_E) == 0) {

	printf("DMMU disabled\n");

    } else {

		break;

	    }

	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {

		       env->dtlb_tag[i] & ~0x1fffULL,

		       env->dtlb_tte[i] & 0x1ffffffe000ULL,

		       mask,

		break;

	    }

	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {

		       env->itlb_tag[i] & ~0x1fffULL,

		       env->itlb_tte[i] & 0x1ffffffe000ULL,

		       mask,

	    // invalid in normal mode

	    if (oldreg != env->lsu) {

#ifdef DEBUG_MMU

		dump_mmu(env);

#endif

		tlb_flush(env, 1);

	    env->immuregs[reg] = T1;

#ifdef DEBUG_MMU

            if (oldreg != env->immuregs[reg]) {

            }

	    dump_mmu(env);

#endif

	    env->dmmuregs[reg] = T1;

#ifdef DEBUG_MMU

            if (oldreg != env->dmmuregs[reg]) {

            }

	    dump_mmu(env);

#endif

#ifdef DEBUG_PCALL

    if (loglevel & CPU_LOG_INT) {

	static int count;

                count, intno,

                env->pc,

                env->npc, env->regwptr[6]);

#define FMTLX "%016lx"

#define X86_64_ONLY(x) x

#else

#define FMTLX "%08lx"

#define X86_64_ONLY(x)

#endif

                delta_max = delta;

            delta_cum += delta;

            if (++count == DISP_FREQ) {

                       muldiv64(delta_min, 1000000, ticks_per_sec),

                       muldiv64(delta_max, 1000000, ticks_per_sec),

                       muldiv64(delta_cum, 1000000 / DISP_FREQ, ticks_per_sec),

}

#define PRId64 "I64d"

#endif

#ifdef QEMU_TOOL