root / target-ppc / kvm.c @ 26b14dc4
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1 | d76d1650 | aurel32 | /*
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2 | d76d1650 | aurel32 | * PowerPC implementation of KVM hooks
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3 | d76d1650 | aurel32 | *
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4 | d76d1650 | aurel32 | * Copyright IBM Corp. 2007
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5 | d76d1650 | aurel32 | *
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6 | d76d1650 | aurel32 | * Authors:
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7 | d76d1650 | aurel32 | * Jerone Young <jyoung5@us.ibm.com>
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8 | d76d1650 | aurel32 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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9 | d76d1650 | aurel32 | * Hollis Blanchard <hollisb@us.ibm.com>
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10 | d76d1650 | aurel32 | *
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11 | d76d1650 | aurel32 | * This work is licensed under the terms of the GNU GPL, version 2 or later.
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12 | d76d1650 | aurel32 | * See the COPYING file in the top-level directory.
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13 | d76d1650 | aurel32 | *
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14 | d76d1650 | aurel32 | */
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15 | d76d1650 | aurel32 | |
16 | d76d1650 | aurel32 | #include <sys/types.h> |
17 | d76d1650 | aurel32 | #include <sys/ioctl.h> |
18 | d76d1650 | aurel32 | #include <sys/mman.h> |
19 | d76d1650 | aurel32 | |
20 | d76d1650 | aurel32 | #include <linux/kvm.h> |
21 | d76d1650 | aurel32 | |
22 | d76d1650 | aurel32 | #include "qemu-common.h" |
23 | d76d1650 | aurel32 | #include "qemu-timer.h" |
24 | d76d1650 | aurel32 | #include "sysemu.h" |
25 | d76d1650 | aurel32 | #include "kvm.h" |
26 | d76d1650 | aurel32 | #include "kvm_ppc.h" |
27 | d76d1650 | aurel32 | #include "cpu.h" |
28 | d76d1650 | aurel32 | #include "device_tree.h" |
29 | d76d1650 | aurel32 | |
30 | d76d1650 | aurel32 | //#define DEBUG_KVM
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31 | d76d1650 | aurel32 | |
32 | d76d1650 | aurel32 | #ifdef DEBUG_KVM
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33 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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34 | d76d1650 | aurel32 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
35 | d76d1650 | aurel32 | #else
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36 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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37 | d76d1650 | aurel32 | do { } while (0) |
38 | d76d1650 | aurel32 | #endif
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39 | d76d1650 | aurel32 | |
40 | c6a94ba5 | Alexander Graf | /* XXX For some odd reason we sometimes hang inside KVM forever. I'd guess it's
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41 | c6a94ba5 | Alexander Graf | * a race condition where we actually have a level triggered interrupt, but
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42 | c6a94ba5 | Alexander Graf | * the infrastructure can't expose that yet, so the guest ACKs it, goes to
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43 | c6a94ba5 | Alexander Graf | * sleep and never gets notified that there's still an interrupt pending.
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44 | c6a94ba5 | Alexander Graf | *
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45 | c6a94ba5 | Alexander Graf | * As a quick workaround, let's just wake up every 500 ms. That way we can
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46 | c6a94ba5 | Alexander Graf | * assure that we're always reinjecting interrupts in time.
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47 | c6a94ba5 | Alexander Graf | */
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48 | c6a94ba5 | Alexander Graf | static QEMUTimer *idle_timer;
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49 | c6a94ba5 | Alexander Graf | |
50 | c6a94ba5 | Alexander Graf | static void do_nothing(void *opaque) |
51 | c6a94ba5 | Alexander Graf | { |
52 | c6a94ba5 | Alexander Graf | qemu_mod_timer(idle_timer, qemu_get_clock(vm_clock) + |
53 | c6a94ba5 | Alexander Graf | (get_ticks_per_sec() / 2));
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54 | c6a94ba5 | Alexander Graf | } |
55 | c6a94ba5 | Alexander Graf | |
56 | d76d1650 | aurel32 | int kvm_arch_init(KVMState *s, int smp_cpus) |
57 | d76d1650 | aurel32 | { |
58 | d76d1650 | aurel32 | return 0; |
59 | d76d1650 | aurel32 | } |
60 | d76d1650 | aurel32 | |
61 | d76d1650 | aurel32 | int kvm_arch_init_vcpu(CPUState *cenv)
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62 | d76d1650 | aurel32 | { |
63 | 861bbc80 | Alexander Graf | int ret = 0; |
64 | 861bbc80 | Alexander Graf | struct kvm_sregs sregs;
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65 | 861bbc80 | Alexander Graf | |
66 | 861bbc80 | Alexander Graf | sregs.pvr = cenv->spr[SPR_PVR]; |
67 | 861bbc80 | Alexander Graf | ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); |
68 | 861bbc80 | Alexander Graf | |
69 | 861bbc80 | Alexander Graf | return ret;
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70 | d76d1650 | aurel32 | } |
71 | d76d1650 | aurel32 | |
72 | caa5af0f | Jan Kiszka | void kvm_arch_reset_vcpu(CPUState *env)
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73 | caa5af0f | Jan Kiszka | { |
74 | caa5af0f | Jan Kiszka | } |
75 | caa5af0f | Jan Kiszka | |
76 | ea375f9a | Jan Kiszka | int kvm_arch_put_registers(CPUState *env, int level) |
77 | d76d1650 | aurel32 | { |
78 | d76d1650 | aurel32 | struct kvm_regs regs;
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79 | d76d1650 | aurel32 | int ret;
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80 | d76d1650 | aurel32 | int i;
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81 | d76d1650 | aurel32 | |
82 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
83 | d76d1650 | aurel32 | if (ret < 0) |
84 | d76d1650 | aurel32 | return ret;
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85 | d76d1650 | aurel32 | |
86 | d76d1650 | aurel32 | regs.ctr = env->ctr; |
87 | d76d1650 | aurel32 | regs.lr = env->lr; |
88 | d76d1650 | aurel32 | regs.xer = env->xer; |
89 | d76d1650 | aurel32 | regs.msr = env->msr; |
90 | d76d1650 | aurel32 | regs.pc = env->nip; |
91 | d76d1650 | aurel32 | |
92 | d76d1650 | aurel32 | regs.srr0 = env->spr[SPR_SRR0]; |
93 | d76d1650 | aurel32 | regs.srr1 = env->spr[SPR_SRR1]; |
94 | d76d1650 | aurel32 | |
95 | d76d1650 | aurel32 | regs.sprg0 = env->spr[SPR_SPRG0]; |
96 | d76d1650 | aurel32 | regs.sprg1 = env->spr[SPR_SPRG1]; |
97 | d76d1650 | aurel32 | regs.sprg2 = env->spr[SPR_SPRG2]; |
98 | d76d1650 | aurel32 | regs.sprg3 = env->spr[SPR_SPRG3]; |
99 | d76d1650 | aurel32 | regs.sprg4 = env->spr[SPR_SPRG4]; |
100 | d76d1650 | aurel32 | regs.sprg5 = env->spr[SPR_SPRG5]; |
101 | d76d1650 | aurel32 | regs.sprg6 = env->spr[SPR_SPRG6]; |
102 | d76d1650 | aurel32 | regs.sprg7 = env->spr[SPR_SPRG7]; |
103 | d76d1650 | aurel32 | |
104 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
105 | d76d1650 | aurel32 | regs.gpr[i] = env->gpr[i]; |
106 | d76d1650 | aurel32 | |
107 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
108 | d76d1650 | aurel32 | if (ret < 0) |
109 | d76d1650 | aurel32 | return ret;
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110 | d76d1650 | aurel32 | |
111 | d76d1650 | aurel32 | return ret;
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112 | d76d1650 | aurel32 | } |
113 | d76d1650 | aurel32 | |
114 | d76d1650 | aurel32 | int kvm_arch_get_registers(CPUState *env)
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115 | d76d1650 | aurel32 | { |
116 | d76d1650 | aurel32 | struct kvm_regs regs;
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117 | ba5e5090 | Alexander Graf | struct kvm_sregs sregs;
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118 | d76d1650 | aurel32 | uint32_t i, ret; |
119 | d76d1650 | aurel32 | |
120 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
121 | d76d1650 | aurel32 | if (ret < 0) |
122 | d76d1650 | aurel32 | return ret;
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123 | d76d1650 | aurel32 | |
124 | ba5e5090 | Alexander Graf | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
125 | ba5e5090 | Alexander Graf | if (ret < 0) |
126 | ba5e5090 | Alexander Graf | return ret;
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127 | ba5e5090 | Alexander Graf | |
128 | d76d1650 | aurel32 | env->ctr = regs.ctr; |
129 | d76d1650 | aurel32 | env->lr = regs.lr; |
130 | d76d1650 | aurel32 | env->xer = regs.xer; |
131 | d76d1650 | aurel32 | env->msr = regs.msr; |
132 | d76d1650 | aurel32 | env->nip = regs.pc; |
133 | d76d1650 | aurel32 | |
134 | d76d1650 | aurel32 | env->spr[SPR_SRR0] = regs.srr0; |
135 | d76d1650 | aurel32 | env->spr[SPR_SRR1] = regs.srr1; |
136 | d76d1650 | aurel32 | |
137 | d76d1650 | aurel32 | env->spr[SPR_SPRG0] = regs.sprg0; |
138 | d76d1650 | aurel32 | env->spr[SPR_SPRG1] = regs.sprg1; |
139 | d76d1650 | aurel32 | env->spr[SPR_SPRG2] = regs.sprg2; |
140 | d76d1650 | aurel32 | env->spr[SPR_SPRG3] = regs.sprg3; |
141 | d76d1650 | aurel32 | env->spr[SPR_SPRG4] = regs.sprg4; |
142 | d76d1650 | aurel32 | env->spr[SPR_SPRG5] = regs.sprg5; |
143 | d76d1650 | aurel32 | env->spr[SPR_SPRG6] = regs.sprg6; |
144 | d76d1650 | aurel32 | env->spr[SPR_SPRG7] = regs.sprg7; |
145 | d76d1650 | aurel32 | |
146 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
147 | d76d1650 | aurel32 | env->gpr[i] = regs.gpr[i]; |
148 | d76d1650 | aurel32 | |
149 | ba5e5090 | Alexander Graf | #ifdef KVM_CAP_PPC_SEGSTATE
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150 | ba5e5090 | Alexander Graf | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {
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151 | ba5e5090 | Alexander Graf | env->sdr1 = sregs.u.s.sdr1; |
152 | ba5e5090 | Alexander Graf | |
153 | ba5e5090 | Alexander Graf | /* Sync SLB */
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154 | 82c09f2f | Alexander Graf | #ifdef TARGET_PPC64
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155 | ba5e5090 | Alexander Graf | for (i = 0; i < 64; i++) { |
156 | ba5e5090 | Alexander Graf | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, |
157 | ba5e5090 | Alexander Graf | sregs.u.s.ppc64.slb[i].slbv); |
158 | ba5e5090 | Alexander Graf | } |
159 | 82c09f2f | Alexander Graf | #endif
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160 | ba5e5090 | Alexander Graf | |
161 | ba5e5090 | Alexander Graf | /* Sync SRs */
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162 | ba5e5090 | Alexander Graf | for (i = 0; i < 16; i++) { |
163 | ba5e5090 | Alexander Graf | env->sr[i] = sregs.u.s.ppc32.sr[i]; |
164 | ba5e5090 | Alexander Graf | } |
165 | ba5e5090 | Alexander Graf | |
166 | ba5e5090 | Alexander Graf | /* Sync BATs */
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167 | ba5e5090 | Alexander Graf | for (i = 0; i < 8; i++) { |
168 | ba5e5090 | Alexander Graf | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; |
169 | ba5e5090 | Alexander Graf | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; |
170 | ba5e5090 | Alexander Graf | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; |
171 | ba5e5090 | Alexander Graf | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; |
172 | ba5e5090 | Alexander Graf | } |
173 | ba5e5090 | Alexander Graf | } |
174 | ba5e5090 | Alexander Graf | #endif
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175 | ba5e5090 | Alexander Graf | |
176 | d76d1650 | aurel32 | return 0; |
177 | d76d1650 | aurel32 | } |
178 | d76d1650 | aurel32 | |
179 | 16415335 | Alexander Graf | #if defined(TARGET_PPCEMB)
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180 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC40x_INPUT_INT
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181 | 16415335 | Alexander Graf | #elif defined(TARGET_PPC64)
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182 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC970_INPUT_INT
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183 | 16415335 | Alexander Graf | #else
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184 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC6xx_INPUT_INT
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185 | 16415335 | Alexander Graf | #endif
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186 | 16415335 | Alexander Graf | |
187 | d76d1650 | aurel32 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
188 | d76d1650 | aurel32 | { |
189 | d76d1650 | aurel32 | int r;
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190 | d76d1650 | aurel32 | unsigned irq;
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191 | d76d1650 | aurel32 | |
192 | c6a94ba5 | Alexander Graf | if (!idle_timer) {
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193 | c6a94ba5 | Alexander Graf | idle_timer = qemu_new_timer(vm_clock, do_nothing, NULL);
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194 | c6a94ba5 | Alexander Graf | qemu_mod_timer(idle_timer, qemu_get_clock(vm_clock) + |
195 | c6a94ba5 | Alexander Graf | (get_ticks_per_sec() / 2));
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196 | c6a94ba5 | Alexander Graf | } |
197 | c6a94ba5 | Alexander Graf | |
198 | d76d1650 | aurel32 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical
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199 | d76d1650 | aurel32 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
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200 | d76d1650 | aurel32 | if (run->ready_for_interrupt_injection &&
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201 | d76d1650 | aurel32 | (env->interrupt_request & CPU_INTERRUPT_HARD) && |
202 | 16415335 | Alexander Graf | (env->irq_input_state & (1<<PPC_INPUT_INT)))
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203 | d76d1650 | aurel32 | { |
204 | d76d1650 | aurel32 | /* For now KVM disregards the 'irq' argument. However, in the
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205 | d76d1650 | aurel32 | * future KVM could cache it in-kernel to avoid a heavyweight exit
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206 | d76d1650 | aurel32 | * when reading the UIC.
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207 | d76d1650 | aurel32 | */
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208 | d76d1650 | aurel32 | irq = -1U;
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209 | d76d1650 | aurel32 | |
210 | d76d1650 | aurel32 | dprintf("injected interrupt %d\n", irq);
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211 | d76d1650 | aurel32 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); |
212 | d76d1650 | aurel32 | if (r < 0) |
213 | d76d1650 | aurel32 | printf("cpu %d fail inject %x\n", env->cpu_index, irq);
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214 | d76d1650 | aurel32 | } |
215 | d76d1650 | aurel32 | |
216 | d76d1650 | aurel32 | /* We don't know if there are more interrupts pending after this. However,
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217 | d76d1650 | aurel32 | * the guest will return to userspace in the course of handling this one
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218 | d76d1650 | aurel32 | * anyways, so we will get a chance to deliver the rest. */
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219 | d76d1650 | aurel32 | return 0; |
220 | d76d1650 | aurel32 | } |
221 | d76d1650 | aurel32 | |
222 | d76d1650 | aurel32 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
223 | d76d1650 | aurel32 | { |
224 | d76d1650 | aurel32 | return 0; |
225 | d76d1650 | aurel32 | } |
226 | d76d1650 | aurel32 | |
227 | d76d1650 | aurel32 | static int kvmppc_handle_halt(CPUState *env) |
228 | d76d1650 | aurel32 | { |
229 | d76d1650 | aurel32 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
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230 | d76d1650 | aurel32 | env->halted = 1;
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231 | d76d1650 | aurel32 | env->exception_index = EXCP_HLT; |
232 | d76d1650 | aurel32 | } |
233 | d76d1650 | aurel32 | |
234 | d76d1650 | aurel32 | return 1; |
235 | d76d1650 | aurel32 | } |
236 | d76d1650 | aurel32 | |
237 | d76d1650 | aurel32 | /* map dcr access to existing qemu dcr emulation */
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238 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) |
239 | d76d1650 | aurel32 | { |
240 | d76d1650 | aurel32 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) |
241 | d76d1650 | aurel32 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
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242 | d76d1650 | aurel32 | |
243 | d76d1650 | aurel32 | return 1; |
244 | d76d1650 | aurel32 | } |
245 | d76d1650 | aurel32 | |
246 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) |
247 | d76d1650 | aurel32 | { |
248 | d76d1650 | aurel32 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) |
249 | d76d1650 | aurel32 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
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250 | d76d1650 | aurel32 | |
251 | d76d1650 | aurel32 | return 1; |
252 | d76d1650 | aurel32 | } |
253 | d76d1650 | aurel32 | |
254 | d76d1650 | aurel32 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
255 | d76d1650 | aurel32 | { |
256 | d76d1650 | aurel32 | int ret = 0; |
257 | d76d1650 | aurel32 | |
258 | d76d1650 | aurel32 | switch (run->exit_reason) {
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259 | d76d1650 | aurel32 | case KVM_EXIT_DCR:
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260 | d76d1650 | aurel32 | if (run->dcr.is_write) {
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261 | d76d1650 | aurel32 | dprintf("handle dcr write\n");
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262 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); |
263 | d76d1650 | aurel32 | } else {
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264 | d76d1650 | aurel32 | dprintf("handle dcr read\n");
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265 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); |
266 | d76d1650 | aurel32 | } |
267 | d76d1650 | aurel32 | break;
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268 | d76d1650 | aurel32 | case KVM_EXIT_HLT:
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269 | d76d1650 | aurel32 | dprintf("handle halt\n");
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270 | d76d1650 | aurel32 | ret = kvmppc_handle_halt(env); |
271 | d76d1650 | aurel32 | break;
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272 | d76d1650 | aurel32 | } |
273 | d76d1650 | aurel32 | |
274 | d76d1650 | aurel32 | return ret;
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275 | d76d1650 | aurel32 | } |
276 | d76d1650 | aurel32 | |
277 | dc333cd6 | Alexander Graf | static int read_cpuinfo(const char *field, char *value, int len) |
278 | dc333cd6 | Alexander Graf | { |
279 | dc333cd6 | Alexander Graf | FILE *f; |
280 | dc333cd6 | Alexander Graf | int ret = -1; |
281 | dc333cd6 | Alexander Graf | int field_len = strlen(field);
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282 | dc333cd6 | Alexander Graf | char line[512]; |
283 | dc333cd6 | Alexander Graf | |
284 | dc333cd6 | Alexander Graf | f = fopen("/proc/cpuinfo", "r"); |
285 | dc333cd6 | Alexander Graf | if (!f) {
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286 | dc333cd6 | Alexander Graf | return -1; |
287 | dc333cd6 | Alexander Graf | } |
288 | dc333cd6 | Alexander Graf | |
289 | dc333cd6 | Alexander Graf | do {
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290 | dc333cd6 | Alexander Graf | if(!fgets(line, sizeof(line), f)) { |
291 | dc333cd6 | Alexander Graf | break;
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292 | dc333cd6 | Alexander Graf | } |
293 | dc333cd6 | Alexander Graf | if (!strncmp(line, field, field_len)) {
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294 | dc333cd6 | Alexander Graf | strncpy(value, line, len); |
295 | dc333cd6 | Alexander Graf | ret = 0;
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296 | dc333cd6 | Alexander Graf | break;
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297 | dc333cd6 | Alexander Graf | } |
298 | dc333cd6 | Alexander Graf | } while(*line);
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299 | dc333cd6 | Alexander Graf | |
300 | dc333cd6 | Alexander Graf | fclose(f); |
301 | dc333cd6 | Alexander Graf | |
302 | dc333cd6 | Alexander Graf | return ret;
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303 | dc333cd6 | Alexander Graf | } |
304 | dc333cd6 | Alexander Graf | |
305 | dc333cd6 | Alexander Graf | uint32_t kvmppc_get_tbfreq(void)
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306 | dc333cd6 | Alexander Graf | { |
307 | dc333cd6 | Alexander Graf | char line[512]; |
308 | dc333cd6 | Alexander Graf | char *ns;
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309 | dc333cd6 | Alexander Graf | uint32_t retval = get_ticks_per_sec(); |
310 | dc333cd6 | Alexander Graf | |
311 | dc333cd6 | Alexander Graf | if (read_cpuinfo("timebase", line, sizeof(line))) { |
312 | dc333cd6 | Alexander Graf | return retval;
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313 | dc333cd6 | Alexander Graf | } |
314 | dc333cd6 | Alexander Graf | |
315 | dc333cd6 | Alexander Graf | if (!(ns = strchr(line, ':'))) { |
316 | dc333cd6 | Alexander Graf | return retval;
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317 | dc333cd6 | Alexander Graf | } |
318 | dc333cd6 | Alexander Graf | |
319 | dc333cd6 | Alexander Graf | ns++; |
320 | dc333cd6 | Alexander Graf | |
321 | dc333cd6 | Alexander Graf | retval = atoi(ns); |
322 | dc333cd6 | Alexander Graf | return retval;
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323 | dc333cd6 | Alexander Graf | } |