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root / target-ppc @ 26b14dc4

# Date Author Comment
26b14dc4 03/11/2010 10:22 pm Aurelien Jarno

target-ppc: fix evsrwu and evsrws

Signed-off-by: Aurelien Jarno <>

e29ef9fa 03/11/2010 10:14 pm Aurelien Jarno

target-ppc: fix evslw instruction

Signed-off-by: Aurelien Jarno <>

ea375f9a 03/04/2010 05:29 am Jan Kiszka

KVM: Rework VCPU state writeback API

This grand cleanup drops all reset and vmsave/load related
synchronization points in favor of four(!) generic hooks:

- cpu_synchronize_all_states in qemu_savevm_state_complete
(initial sync from kernel before vmsave)...

db9a231d 02/28/2010 05:36 pm Aurelien Jarno

Revert "target-ppc: stop translation after a trap instruction"

This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.

6c712321 02/28/2010 05:36 pm Aurelien Jarno

target-ppc: don't print invalid opcode messages on the console

Invalid opcode messages can be perfectly normal, for example if this
code is never executed. Don't print an error message on the console,
but keep the message in the log for debugging purposes....

6454e7be 02/28/2010 03:11 pm Aurelien Jarno

target-ppc: stop translation after a trap instruction

Signed-off-by: Aurelien Jarno <>

ae01847f 02/27/2010 05:10 pm Nathan Froyd

target-ppc: fix SPE evsplat* instructions

The shifts in the gen_evsplat* functions were expecting rA to be masked,
not extracted, and so used the wrong shift amounts to sign-extend or pad
with zeroes.

Signed-off-by: Nathan Froyd <>...

e6bba2ef 02/27/2010 05:10 pm Nathan Froyd

target-ppc: fix SPE evcmp* instructions

The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position. Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position....

dc333cd6 02/14/2010 04:10 pm Alexander Graf

PPC: tell the guest about the time base frequency

Our guest systems need to know by how much the timebase increases every second,
so there usually is a "timebase-frequency" property in the cpu leaf of the
device tree.

This property is missing in OpenBIOS....

b2eca445 02/14/2010 04:10 pm Alexander Graf

PPC: Fix large pages

We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviously
that breaks, so let's just ignore 1TB SLB entries for now and instead do
16MB pages correctly.

This fixes PPC64 Linux boot with -m above 256.

Signed-off-by: Alexander Graf <>...

c6a94ba5 02/14/2010 04:10 pm Alexander Graf

PPC: Add timer when running KVM

For some odd reason we sometimes hang inside KVM forever. I'd guess it's
a race condition where we actually have a level triggered interrupt, but
the infrastructure can't expose that yet, so the guest ACKs it, goes to
sleep and never gets notified that there's still an interrupt pending....

95ff895f 02/06/2010 06:14 pm Aurelien Jarno

target-ppc: change DCR helpers to target_long arguments

The recent transition to always have the DCR helper functions take 32 bit
values broke the PPC64 target, as target_long became 64 bits there.

This patch changes DCR helpers to target_long arguments, and cast the values...

49a945a3 01/20/2010 12:31 am Paolo Bonzini

kill regs_to_env and env_to_regs

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Anthony Liguori <>

dcbc9a70 01/14/2010 03:42 pm Edgar E. Iglesias

ppc-40x: Correct ESR for zone protection faults.

Raise the zone protection fault in ESR for TLB faults caused by
zone protection bits.

Signed-off-by: Edgar E. Iglesias <>

ec5c3e48 01/14/2010 03:42 pm Edgar E. Iglesias

ppc-40x: Correct decoding of zone protection bits.

The 40x MMU has 15 zones in the ZPR register.

Signed-off-by: Edgar E. Iglesias <>

c5b9729a 01/14/2010 03:42 pm Edgar E. Iglesias

ppc-40x: Correct check for Endian swapping TLB entries.

Bailout on 40x TLB entries with endianess swapping only if the entry
is valid.

Signed-off-by: Edgar E. Iglesias <>

f25359cd 01/14/2010 03:41 pm Edgar E. Iglesias

ppc-40x: Get TLB attributes from TLBLO.

The ZSEL was incorrectly beeing decoded from TLBHI. Decode it from
TLBLO instead.

Signed-off-by: Edgar E. Iglesias <>

73b01960 12/21/2009 05:03 pm Alexander Graf

PPC: Make DCR uint32_t

For what I know DCR is always 32 bits wide, so we should also use uint32_t to
pass it along the stacks.

This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, making
it compile without --disable-werror

Signed-off-by: Alexander Graf <>...

b711de95 12/21/2009 02:52 pm Aurelien Jarno

PPC64: Fix alternate timebase

Fix the alternate time base the same way as the default timebase. SPR_ATBL
should return a 64-bit value on 64 bit implementations.

Signed-off-by: Aurelien Jarno <>

e3ea6529 12/21/2009 02:42 pm Alexander Graf

PPC64: Fix timebase

On PPC we have a 64-bit time base. Usually (PPC32) this is accessed using
two separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.

On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full
64 bits as return value. If we only take the lower ones, fine. But Linux...

82c09f2f 12/19/2009 10:30 am Alexander Graf

target-ppc: fix ppc32 kvm build

My segment sync patch broke compilation on PPC32, because it was trying to
sync the SLB even though ppc32 CPUs don't have an SLB.

So let's only sync it when we're on a PP64 one!

Signed-off-by: Alexander Graf <>...

ba5e5090 12/03/2009 09:10 pm Alexander Graf

target-ppc: Get MMU state on register sync

While x86 only needs to sync cr0-4 to know all about its MMU state and enable
qemu to resolve virtual to physical addresses, we need to sync all of the
segment registers on PPC to know which mapping we're in.

So let's grab the segment register contents to be able to use the "x" monitor...

caa5af0f 11/17/2009 04:49 pm Jan Kiszka

kvm: Add arch reset handler

Will be required by succeeding changes.

Signed-off-by: Jan Kiszka <>
Signed-off-by: Anthony Liguori <>

812151f2 11/12/2009 07:23 pm Hollis Blanchard

kvm ppc: Remove unused label

Signed-off-by: Hollis Blanchard <>
Signed-off-by: Anthony Liguori <>

b55a37c9 11/07/2009 12:37 pm Blue Swirl

user: move CPU reset call to main.c for x86/PPC/Sparc

Signed-off-by: Blue Swirl <>

d84bda46 11/07/2009 12:36 pm Blue Swirl

PPC: rename cpu_ppc_reset to cpu_reset for consistency

Signed-off-by: Blue Swirl <>

e4394131 11/07/2009 11:32 am Blue Swirl

PPC: remove unneeded calls to device reset

Signed-off-by: Blue Swirl <>

cb2dbfc3 10/23/2009 01:14 am Aurelien Jarno

target-ppc: move often used CPU fields at the top of the structure

Signed-off-by: Aurelien Jarno <>

74d77cae 10/18/2009 05:15 pm Thomas Monjalon

target-ppc: simpler definitions for microcontrollers based on e300

No need to alias e300 core for each CPU package.
Differences between microcontrollers have to be implemented in a higher layer
than translate_init.c

Signed-off-by: Thomas Monjalon <>...

492d7bf5 10/18/2009 05:15 pm Thomas Monjalon

target-ppc: add declarations of microcontrollers based on e300

Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E.

Signed-off-by: Thomas Monjalon <>
Signed-off-by: Aurelien Jarno <>

8daf1781 10/18/2009 05:15 pm Thomas Monjalon

target-ppc: better support of e300 CPU core

Declare HID2 register.

Use high BATs for e300 (8 instead of 4).

Fix index of high BATs registers.
Before the fix, IBAT4-7 were overwriting IBAT0-3.

Signed-off-by: Fran├žois Armand <>
Signed-off-by: Aurelien Jarno <>

c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...

99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <>

731c54f8 09/28/2009 02:40 pm Aurelien Jarno

target-ppc: log instructions start in TCG code

Signed-off-by: Aurelien Jarno <>

86178a57 09/25/2009 10:51 pm Juan Quintela

static and inline should came before the type of the functions

Signed-off-by: Juan Quintela <>
Signed-off-by: Blue Swirl <>

7fd6bf7d 09/18/2009 05:57 pm Aurelien Jarno

target-ppc: optimize slw/srw/sld/srd

Remove a temp local variable and a jump by computing a mask with shifts.

Signed-off-by: Aurelien Jarno <>

72cf2d4f 09/12/2009 10:36 am Blue Swirl

Fix sys-queue.h conflict for good

Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...

6ee093c9 09/11/2009 06:19 pm Juan Quintela

Unexport ticks_per_sec variable. Create get_ticks_per_sec() function

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>

4c0960c0 08/28/2009 04:35 am Avi Kivity

kvm: Simplify cpu_synchronize_state()

cpu_synchronize_state() is a little unreadable since the 'modified'
argument isn't self-explanatory. Simplify it by making it always
synchronize the kernel state into qemu, and automatically flush the
registers back to the kernel if they've been synchronized on this...

0b5c1ce8 08/24/2009 04:21 pm Nathan Froyd

cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal

handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations. This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets...

b11ebf64 08/16/2009 02:54 pm Blue Swirl

Replace REGX with PRIx64

Signed-off-by: Blue Swirl <>

90e189ec 08/16/2009 02:13 pm Blue Swirl

Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx

Signed-off-by: Blue Swirl <>

636aa200 08/16/2009 12:06 pm Blue Swirl

Replace always_inline with inline

We define inline as always_inline.

Signed-off-by: Blue Swirl <>

174c80d5 08/03/2009 07:33 pm Nathan Froyd

target-ppc: add cpu_set_tls

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

18b21a2f 08/03/2009 07:33 pm Nathan Froyd

target-ppc: retain l{w,d}arx loaded value

We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed. It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <>...

4425265b 08/03/2009 07:33 pm Nathan Froyd

target-ppc: add exceptions for conditional stores

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

d11f69b2 08/03/2009 07:33 pm Nathan Froyd

target-ppc: fix cpu_clone_regs

We only need to make sure that the clone syscall looks like it
succeeded, not clobber 60% of the register set.

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

e2542fe2 07/27/2009 10:09 pm Juan Quintela

rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>

3f0855b1 07/27/2009 10:09 pm Juan Quintela

Rename HAVE_FDT to CONFIG_FDT and define it also in Makefile

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>

16415335 07/22/2009 06:58 pm Alexander Graf

Use correct input constant

440 and desktop codes use different input constants for interrupt indication.

Let's use the respective ones for KVM.

Signed-off-by: Alexander Graf <>
Signed-off-by: Anthony Liguori <>

861bbc80 07/22/2009 06:58 pm Alexander Graf

Set PVR in sregs

We need to tell the kernel about some initial CPU state we don't have yet,
so let's use the "sregs" IOCTL for that and simply put the Processor Version
Register in there.

Now the kernel knows which guest CPU to virtualize.

Signed-off-by: Alexander Graf <>...

0bf9e31a 07/20/2009 08:19 pm Blue Swirl

Fix most warnings (errors with -Werror) when debugging is enabled

I used the following command to enable debugging:
perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*

Signed-off-by: Blue Swirl <>

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

f4078236 07/13/2009 02:58 am Baojun Wang

target-ppc: enable PPC_MFTB for 44x

According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a
preserved instruction:

PPC440_UM2013.pdf, p.445, table A-3

when I compile a kernel (2.6.30, bamboo_defconfig/440EP &
canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump...

fbe73008 07/13/2009 02:51 am Baojun Wang

ppc tcg: fix wrong bit/mask of wrteei

Signed-off-by: Baojun Wang <>
Signed-off-by: Aurelien Jarno <>

33890b3e 07/13/2009 12:36 am Nathan Froyd

target-ppc: fix evmergelo and evmergelohi

For 32-bit PPC targets, we translated:

evmergelo rX, rX, rY

as:

rX-lo = rY-lo
rX-hi = rX-lo

which is wrong, because we should be transferring rX-lo first. This
problem is fixed by swapping the order in which we write the parts of...

a139aa17 06/23/2009 08:11 pm Nathan Froyd

target-ppc: permit linux-user to read PVR

Access to the PVR SPR is normally forbidden from userspace apps. The
Linux kernel, however, fixes up reads in the appropriate trap handler.
To permit applications that read PVR to run on QEMU, then, we need to
implement the same handling of PVR reads....

d2e9fd8f 06/20/2009 04:51 am malc

Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be used
uninitialized

5c55ff99 06/17/2009 06:22 pm Blue Swirl

Replace ELF section hack with normal table

Signed-off-by: Blue Swirl <>

2e610050 06/17/2009 06:22 pm Blue Swirl

Concentrate rest of table entries to top

Signed-off-by: Blue Swirl <>

54623277 06/17/2009 06:22 pm Blue Swirl

Concentrate most table entries to top

Signed-off-by: Blue Swirl <>

e8eaa2c0 06/17/2009 06:22 pm Blue Swirl

Clean up GEN_HANDLER2

Signed-off-by: Blue Swirl <>

99e300ef 06/17/2009 06:22 pm Blue Swirl

Clean up GEN_HANDLER

Signed-off-by: Blue Swirl <>

c5b76b38 06/13/2009 11:44 am Blue Swirl

Fix mingw32 build warnings

Work around buffer and ioctlsocket argument type signedness problems
Suppress a prototype which is unused on mingw32
Expand a macro to avoid warnings from some GCC versions

Signed-off-by: Blue Swirl <>

b0a46a33 05/22/2009 06:50 pm Jan Kiszka

kvm: Add missing bits to support live migration

This patch adds the missing hooks to allow live migration in KVM mode.
It adds proper synchronization before/after saving/restoring the VCPU
states (note: PPC is untested), hooks into
cpu_physical_memory_set_dirty_tracking() to enable dirty memory logging...

f80f9ec9 05/21/2009 04:47 pm Anthony Liguori

Convert machine registration to use module init functions

This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.

Signed-off-by: Anthony Liguori <>

1ad2134f 05/19/2009 06:17 pm Paul Brook

Hardware convenience library

The only target dependency for most hardware is sizeof(target_phys_addr_t).
Build these files into a convenience library, and use that instead of
building for every target.

Remove and poison various target specific macros to avoid bogus target...

c29b735c 05/16/2009 12:36 am Nathan Froyd

target-ppc: expose cpu capability flags

Do this so other pieces of code can make decisions based on the
capabilities of the CPU we're emulating.

Signed-off-by: Nathan Froyd <>
Signed-off-by: malc <>

55616505 05/13/2009 10:54 pm Paul Brook

Include assert.h from qemu-common.h

Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <>

1481e16a 05/13/2009 02:18 pm malc

Fix typo that leads to out of bounds array access on big endian systems

2d3eb7bf 04/28/2009 09:07 pm Tristan Gingold

Fix powerpc 604 reset vector

According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is set
for hreset and the vector is at offset 0x100 from the exception prefix.

No difference in this area between 604 and 604e.

Signed-off-by: Tristan Gingold <>

fc1c67bc 04/28/2009 09:00 pm Blue Swirl

Fix PPC reset

0bf46a40 04/24/2009 09:03 pm aliguori

qemu: introduce qemu_init_vcpu (Marcelo Tosatti)

Signed-off-by: Marcelo Tosatti <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162

6a4955a8 04/24/2009 09:03 pm aliguori

qemu: per-arch cpu_has_work (Marcelo Tosatti)

Blue Swirl: fix Sparc32 breakage

Signed-off-by: Marcelo Tosatti <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162

69a218fc 04/16/2009 03:57 pm aurel32

target-ppc: mark a few helpers TCG_CALL_CONST and/or TCG_CALL_PURE

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7129 c046a42c-6fe2-441c-8c8c-71466251a162

2dc766da 04/13/2009 07:06 pm blueswir1

Fix ppc-softmmu warnings on OpenBSD host

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162

1b530a6d 04/05/2009 11:08 pm aurel32

Add new command line option -singlestep for tcg single stepping.

This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode....

bf1752ef 03/29/2009 04:36 pm aurel32

target-ppc: Explain why the whole TLB is flushed on SR write

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162

af4b6c54 03/29/2009 04:18 am aurel32

target-ppc: avoid nop to override next instruction

While searching PC, always store the pc of a new instruction.
Instructions that didn't generate tcg code (such as nop) prevented the
next one to be referenced.

Based on patch for target-alpha, r6930.

Signed-off-by: Aurelien Jarno <>...

7f70c937 03/13/2009 11:16 pm blueswir1

Make the ELF loader aware of backwards compatibility

Most 64 bit architectures I'm aware of support running 32 bit code
of the same architecture as well.

So x86_64 can run i386 code easily and ppc64 can run ppc code.

Unfortunately, the current checks are pretty strict. So you can only...

fa3966a3 03/13/2009 11:35 am aurel32

target-ppc: use the new bswap* TCG ops

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162

66896cb8 03/13/2009 11:34 am aurel32

tcg: rename bswap_i32/i64 functions

Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162

515e2f7e 03/10/2009 09:37 pm aurel32

target-ppc: fix commit r6789

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162

651721b2 03/09/2009 08:50 pm aurel32

targe-ppc: optimize mfcr and mtcrf

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162

69bd5820 03/09/2009 08:27 am aurel32

target-ppc: free a tcg temp variable

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162

d34defbc 03/09/2009 08:27 am aurel32

target-ppc: add support for reading/writing spefscr

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162

70976a79 03/08/2009 12:00 am aurel32

Fix off-by-one errors for Altivec and SPE registers

Altivec and SPE both have 34 registers in their register sets, not 35
with a missing register 32.

GDB would ask for register 32 of the Altivec (resp. SPE) registers and
the code would claim it had zero width. The QEMU GDB stub code would...

94855937 03/07/2009 10:58 pm blueswir1

Disable BAT for 970

The 970 doesn't know BAT, so let's not search BATs there.
This was only in as a hack for OpenHackWare so it would
work on PPC64.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162

0497d2f4 03/07/2009 10:57 pm aurel32

Fix mfcr on ppc64-softmmu

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162

8eee0af9 03/07/2009 10:57 pm blueswir1

Keep SLB in-CPU

Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled...

29c8ca6f 03/07/2009 10:57 pm blueswir1

Fix NX bit

ctx->nx only got ORed, but never reset. So when one page in the
lifetime of the VM was ever NX, all later pages were too.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162

2ada0ed7 03/07/2009 10:56 pm blueswir1

Fix RFI

The current implementation masks some MSR bits from SRR1 as it is
given on rfi(d). This looks pretty wrong and breaks Altivec.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6754 c046a42c-6fe2-441c-8c8c-71466251a162

4911012d 03/07/2009 10:55 pm blueswir1

Implement mtfsf.L encoding

Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162

6ce0ca12 03/07/2009 10:54 pm blueswir1

Enable 64bit mode on interrupts

Real 970s enable MSR_SF on all interrupts. The current code didn't do
this until now, so let's activate it!

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162

4e98d8cf 03/07/2009 10:54 pm blueswir1

Nop some SPRs on 970fx

Linux tries to access some SPRs on PPC64 boot. Let's just ignore those
for the 970fx for now to make it happy.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162

bf14b1ce 03/07/2009 10:52 pm blueswir1

Implment tlbiel

Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLB
flush opcode only flushes an entry for the CPU it runs on, not across
all CPUs in the system.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162

5b5aba4f 03/07/2009 10:51 pm blueswir1

Implement large pages

The current SLB/PTE code does not support large pages, which are
required by Linux, as it boots up with the kernel regions up as large.

This patch implements large page support, so we can run Linux.

Signed-off-by: Alexander Graf <>...

f6b868fc 03/07/2009 10:50 pm blueswir1

Implement slbmte

In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.

This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later....

50773fd2 03/07/2009 05:59 pm blueswir1

Sparse fixes: add extern to ELF opcode tables to avoid warnings

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162

c2764719 03/07/2009 05:24 pm pbrook

The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications. Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.

Signed-off-by: Paul Brook <>...