Revision 26f69dc0
b/pc-bios/vgabios.diff | ||
---|---|---|
1 |
? biossums |
|
2 |
? vgabios.cirrus.debug.txt |
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3 |
? vgabios.cirrus.txt |
|
4 |
? vgabios.debug.txt |
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5 |
? vgabios.txt |
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6 |
? tests/Makefile |
|
7 |
? tests/setmode.S |
|
8 |
? tests/setmode.c |
|
9 |
? tests/setmode.com |
|
10 |
? tests/setmode.elf |
|
11 | 1 |
Index: Makefile |
12 | 2 |
=================================================================== |
13 |
RCS file: /cvsroot/vgabios/vgabios/Makefile,v |
|
14 |
retrieving revision 1.15 |
|
15 |
diff -u -w -r1.15 Makefile |
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16 |
Index: VGABIOS-lgpl-latest.bin |
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17 |
=================================================================== |
|
18 |
RCS file: /cvsroot/vgabios/vgabios/VGABIOS-lgpl-latest.bin,v |
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19 |
retrieving revision 1.60 |
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20 |
diff -u -w -r1.60 VGABIOS-lgpl-latest.bin |
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21 |
Binary files /tmp/cvsCahrMA and VGABIOS-lgpl-latest.bin differ |
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22 |
Index: VGABIOS-lgpl-latest.cirrus.bin |
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23 |
=================================================================== |
|
24 |
RCS file: /cvsroot/vgabios/vgabios/VGABIOS-lgpl-latest.cirrus.bin,v |
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25 |
retrieving revision 1.12 |
|
26 |
diff -u -w -r1.12 VGABIOS-lgpl-latest.cirrus.bin |
|
27 |
Binary files /tmp/cvsewygNU and VGABIOS-lgpl-latest.cirrus.bin differ |
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28 |
Index: VGABIOS-lgpl-latest.cirrus.debug.bin |
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29 |
=================================================================== |
|
30 |
RCS file: /cvsroot/vgabios/vgabios/VGABIOS-lgpl-latest.cirrus.debug.bin,v |
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31 |
retrieving revision 1.12 |
|
32 |
diff -u -w -r1.12 VGABIOS-lgpl-latest.cirrus.debug.bin |
|
33 |
Binary files /tmp/cvsey9TQf and VGABIOS-lgpl-latest.cirrus.debug.bin differ |
|
34 |
Index: VGABIOS-lgpl-latest.debug.bin |
|
35 |
=================================================================== |
|
36 |
RCS file: /cvsroot/vgabios/vgabios/VGABIOS-lgpl-latest.debug.bin,v |
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37 |
retrieving revision 1.60 |
|
38 |
diff -u -w -r1.60 VGABIOS-lgpl-latest.debug.bin |
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39 |
Binary files /tmp/cvskxbTbC and VGABIOS-lgpl-latest.debug.bin differ |
|
3 |
RCS file: /sources/vgabios/vgabios/Makefile,v |
|
4 |
retrieving revision 1.17 |
|
5 |
diff -u -w -r1.17 Makefile |
|
6 |
--- Makefile 6 Mar 2005 13:06:47 -0000 1.17 |
|
7 |
+++ Makefile 25 Mar 2006 01:19:02 -0000 |
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8 |
@@ -17,9 +17,9 @@ |
|
9 |
all: bios cirrus-bios |
|
10 |
|
|
11 |
|
|
12 |
-bios: biossums vgabios.bin vgabios.debug.bin |
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13 |
+bios: biossums vgabios.bin #vgabios.debug.bin |
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14 |
|
|
15 |
-cirrus-bios: vgabios-cirrus.bin vgabios-cirrus.debug.bin |
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16 |
+cirrus-bios: vgabios-cirrus.bin #vgabios-cirrus.debug.bin |
|
17 |
|
|
18 |
clean: |
|
19 |
/bin/rm -f biossums *.o *.s *.ld86 \ |
|
40 | 20 |
Index: clext.c |
41 | 21 |
=================================================================== |
42 |
RCS file: /cvsroot/vgabios/vgabios/clext.c,v |
|
43 |
retrieving revision 1.8 |
|
44 |
diff -u -w -r1.8 clext.c |
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45 |
--- clext.c 8 Aug 2004 16:52:55 -0000 1.8 |
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46 |
+++ clext.c 30 Nov 2004 23:38:32 -0000 |
|
47 |
@@ -222,7 +222,21 @@ |
|
48 |
0x001a,0x221b,0x001d, |
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22 |
RCS file: /sources/vgabios/vgabios/clext.c,v |
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23 |
retrieving revision 1.9 |
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24 |
diff -u -w -r1.9 clext.c |
|
25 |
--- clext.c 4 Dec 2004 15:26:17 -0000 1.9 |
|
26 |
+++ clext.c 25 Mar 2006 01:19:03 -0000 |
|
27 |
@@ -238,6 +238,21 @@ |
|
49 | 28 |
0xffff |
50 | 29 |
}; |
51 |
- |
|
52 |
+/* 1280x1024x16 */
|
|
53 |
+unsigned short cseq_1280x1024x16[] = {
|
|
54 |
+0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
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|
30 |
|
|
31 |
+/* 1600x1200x8 */
|
|
32 |
+unsigned short cseq_1600x1200x8[] = {
|
|
33 |
+0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
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55 | 34 |
+0x760b,0x760c,0x760d,0x760e, |
56 | 35 |
+0x0412,0x0013,0x2017, |
57 | 36 |
+0x341b,0x341c,0x341d,0x341e, |
58 | 37 |
+0xffff |
59 | 38 |
+}; |
60 |
+unsigned short ccrtc_1280x1024x16[] = {
|
|
39 |
+unsigned short ccrtc_1600x1200x8[] = {
|
|
61 | 40 |
+0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707, |
62 | 41 |
+0x6009,0x000c,0x000d, |
63 |
+0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
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|
64 |
+0x001a,0x321b,0x001d,
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|
42 |
+0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
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|
43 |
+0x001a,0x221b,0x001d,
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|
65 | 44 |
+0xffff |
66 | 45 |
+}; |
67 | 46 |
|
68 | 47 |
cirrus_mode_t cirrus_modes[] = |
69 | 48 |
{ |
70 |
@@ -269,6 +283,12 @@ |
|
71 |
{0x6d,1280,1024,8,0x00, |
|
72 |
cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8, |
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73 |
4,0,0,0,0,0,0,0,0}, |
|
74 |
+ {0x69,1280,1024,15,0xf0, |
|
75 |
+ cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16, |
|
76 |
+ 6,5,10,5,5,5,0,1,15}, |
|
77 |
+ {0x75,1280,1024,16,0xe1, |
|
78 |
+ cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16, |
|
79 |
+ 6,5,11,6,5,5,0,0,0}, |
|
49 |
@@ -291,6 +306,10 @@ |
|
50 |
cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16, |
|
51 |
6,5,11,6,5,5,0,0,0}, |
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80 | 52 |
|
53 |
+ {0x7b,1600,1200,8,0x00, |
|
54 |
+ cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8, |
|
55 |
+ 4,0,0,0,0,0,0,0,0}, |
|
56 |
+ |
|
81 | 57 |
{0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0, |
82 | 58 |
0xff,0,0,0,0,0,0,0,0}, |
83 |
@@ -310,9 +330,13 @@ |
|
84 |
// 1024x768x16 |
|
85 |
0x117, 0x74, |
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86 |
// 1024x768x24 |
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87 |
-//0x118, 0x79, |
|
88 |
+ 0x118, 0x79, |
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89 |
// 1280x1024x8 |
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90 |
0x107, 0x6d, |
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91 |
+// 1280x1024x15 |
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92 |
+ 0x119, 0x69, |
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93 |
+// 1280x1024x16 |
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94 |
+ 0x11a, 0x75, |
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95 |
// invalid |
|
96 |
0xffff,0xffff |
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59 |
{0xff,0,0,0,0,0,0,0,0, |
|
60 |
Index: vgabios.c |
|
61 |
=================================================================== |
|
62 |
RCS file: /sources/vgabios/vgabios/vgabios.c,v |
|
63 |
retrieving revision 1.63 |
|
64 |
diff -u -w -r1.63 vgabios.c |
|
65 |
--- vgabios.c 26 Dec 2005 19:50:26 -0000 1.63 |
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66 |
+++ vgabios.c 25 Mar 2006 01:19:03 -0000 |
|
67 |
@@ -111,6 +111,7 @@ |
|
68 |
static void biosfn_read_video_state_size(); |
|
69 |
static void biosfn_save_video_state(); |
|
70 |
static void biosfn_restore_video_state(); |
|
71 |
+extern Bit8u video_save_pointer_table[]; |
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72 |
|
|
73 |
// This is for compiling with gcc2 and gcc3 |
|
74 |
#define ASM_START #asm |
|
75 |
@@ -459,6 +460,29 @@ |
|
76 |
|
|
77 |
pop ds |
|
78 |
ret |
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79 |
+ |
|
80 |
+_video_save_pointer_table: |
|
81 |
+ .word _video_param_table |
|
82 |
+ .word 0xc000 |
|
83 |
+ |
|
84 |
+ .word 0 /* XXX: fill it */ |
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85 |
+ .word 0 |
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86 |
+ |
|
87 |
+ .word 0 /* XXX: fill it */ |
|
88 |
+ .word 0 |
|
89 |
+ |
|
90 |
+ .word 0 /* XXX: fill it */ |
|
91 |
+ .word 0 |
|
92 |
+ |
|
93 |
+ .word 0 /* XXX: fill it */ |
|
94 |
+ .word 0 |
|
95 |
+ |
|
96 |
+ .word 0 /* XXX: fill it */ |
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97 |
+ .word 0 |
|
98 |
+ |
|
99 |
+ .word 0 /* XXX: fill it */ |
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100 |
+ .word 0 |
|
101 |
+ |
|
102 |
ASM_END |
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103 |
|
|
104 |
// -------------------------------------------------------------------------------------------- |
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105 |
@@ -780,8 +804,8 @@ |
|
106 |
|
|
107 |
// Should we clear the screen ? |
|
108 |
Bit8u noclearmem=mode&0x80; |
|
109 |
- Bit8u line,mmask,*palette; |
|
110 |
- Bit16u i,twidth,theight,cheight; |
|
111 |
+ Bit8u line,mmask,*palette,vpti; |
|
112 |
+ Bit16u i,twidth,theightm1,cheight; |
|
113 |
Bit8u modeset_ctl,video_ctl,vga_switches; |
|
114 |
Bit16u crtc_addr; |
|
115 |
|
|
116 |
@@ -804,9 +828,10 @@ |
|
117 |
if(line==0xFF) |
|
118 |
return; |
|
119 |
|
|
120 |
- twidth=vga_modes[line].twidth; |
|
121 |
- theight=vga_modes[line].theight; |
|
122 |
- cheight=vga_modes[line].cheight; |
|
123 |
+ vpti=line_to_vpti[line]; |
|
124 |
+ twidth=video_param_table[vpti].twidth; |
|
125 |
+ theightm1=video_param_table[vpti].theightm1; |
|
126 |
+ cheight=video_param_table[vpti].cheight; |
|
127 |
|
|
128 |
// Read the bios vga control |
|
129 |
video_ctl=read_byte(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL); |
|
130 |
@@ -866,21 +891,25 @@ |
|
131 |
inb(VGAREG_ACTL_RESET); |
|
132 |
|
|
133 |
// Set Attribute Ctl |
|
134 |
- for(i=0;i<=ACTL_MAX_REG;i++) |
|
135 |
+ for(i=0;i<=0x13;i++) |
|
136 |
{outb(VGAREG_ACTL_ADDRESS,i); |
|
137 |
- outb(VGAREG_ACTL_WRITE_DATA,actl_regs[vga_modes[line].actlmodel][i]); |
|
138 |
+ outb(VGAREG_ACTL_WRITE_DATA,video_param_table[vpti].actl_regs[i]); |
|
139 |
} |
|
140 |
+ outb(VGAREG_ACTL_ADDRESS,0x14); |
|
141 |
+ outb(VGAREG_ACTL_WRITE_DATA,0x00); |
|
142 |
|
|
143 |
// Set Sequencer Ctl |
|
144 |
- for(i=0;i<=SEQU_MAX_REG;i++) |
|
145 |
+ outb(VGAREG_SEQU_ADDRESS,0); |
|
146 |
+ outb(VGAREG_SEQU_DATA,0x03); |
|
147 |
+ for(i=1;i<=4;i++) |
|
148 |
{outb(VGAREG_SEQU_ADDRESS,i); |
|
149 |
- outb(VGAREG_SEQU_DATA,sequ_regs[vga_modes[line].sequmodel][i]); |
|
150 |
+ outb(VGAREG_SEQU_DATA,video_param_table[vpti].sequ_regs[i - 1]); |
|
151 |
} |
|
152 |
|
|
153 |
// Set Grafx Ctl |
|
154 |
- for(i=0;i<=GRDC_MAX_REG;i++) |
|
155 |
+ for(i=0;i<=8;i++) |
|
156 |
{outb(VGAREG_GRDC_ADDRESS,i); |
|
157 |
- outb(VGAREG_GRDC_DATA,grdc_regs[vga_modes[line].grdcmodel][i]); |
|
158 |
+ outb(VGAREG_GRDC_DATA,video_param_table[vpti].grdc_regs[i]); |
|
159 |
} |
|
160 |
|
|
161 |
// Set CRTC address VGA or MDA |
|
162 |
@@ -889,13 +918,13 @@ |
|
163 |
// Disable CRTC write protection |
|
164 |
outw(crtc_addr,0x0011); |
|
165 |
// Set CRTC regs |
|
166 |
- for(i=0;i<=CRTC_MAX_REG;i++) |
|
167 |
+ for(i=0;i<=0x18;i++) |
|
168 |
{outb(crtc_addr,i); |
|
169 |
- outb(crtc_addr+1,crtc_regs[vga_modes[line].crtcmodel][i]); |
|
170 |
+ outb(crtc_addr+1,video_param_table[vpti].crtc_regs[i]); |
|
171 |
} |
|
172 |
|
|
173 |
// Set the misc register |
|
174 |
- outb(VGAREG_WRITE_MISC_OUTPUT,vga_modes[line].miscreg); |
|
175 |
+ outb(VGAREG_WRITE_MISC_OUTPUT,video_param_table[vpti].miscreg); |
|
176 |
|
|
177 |
// Enable video |
|
178 |
outb(VGAREG_ACTL_ADDRESS,0x20); |
|
179 |
@@ -927,9 +956,9 @@ |
|
180 |
// Set the BIOS mem |
|
181 |
write_byte(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,mode); |
|
182 |
write_word(BIOSMEM_SEG,BIOSMEM_NB_COLS,twidth); |
|
183 |
- write_word(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,vga_modes[line].slength); |
|
184 |
+ write_word(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,*(Bit16u *)&video_param_table[vpti].slength_l); |
|
185 |
write_word(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS,crtc_addr); |
|
186 |
- write_byte(BIOSMEM_SEG,BIOSMEM_NB_ROWS,theight-1); |
|
187 |
+ write_byte(BIOSMEM_SEG,BIOSMEM_NB_ROWS,theightm1); |
|
188 |
write_word(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT,cheight); |
|
189 |
write_byte(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL,(0x60|noclearmem)); |
|
190 |
write_byte(BIOSMEM_SEG,BIOSMEM_SWITCHES,0xF9); |
|
191 |
@@ -937,8 +966,8 @@ |
|
192 |
|
|
193 |
// FIXME We nearly have the good tables. to be reworked |
|
194 |
write_byte(BIOSMEM_SEG,BIOSMEM_DCC_INDEX,0x08); // 8 is VGA should be ok for now |
|
195 |
- write_word(BIOSMEM_SEG,BIOSMEM_VS_POINTER,0x00); |
|
196 |
- write_word(BIOSMEM_SEG,BIOSMEM_VS_POINTER+2,0x00); |
|
197 |
+ write_word(BIOSMEM_SEG,BIOSMEM_VS_POINTER, video_save_pointer_table); |
|
198 |
+ write_word(BIOSMEM_SEG,BIOSMEM_VS_POINTER+2, 0xc000); |
|
199 |
|
|
200 |
// FIXME |
|
201 |
write_byte(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x00); // Unavailable on vanilla vga, but... |
|
202 |
@@ -1114,7 +1143,7 @@ |
|
203 |
} |
|
204 |
else |
|
205 |
{ |
|
206 |
- address = page*vga_modes[line].slength; |
|
207 |
+ address = page * (*(Bit16u *)&video_param_table[line_to_vpti[line]].slength_l); |
|
208 |
} |
|
209 |
|
|
210 |
// CRTC regs 0x0c and 0x0d |
|
211 |
@@ -1271,7 +1300,7 @@ |
|
212 |
else |
|
213 |
{ |
|
214 |
// FIXME gfx mode not complete |
|
215 |
- cheight=vga_modes[line].cheight; |
|
216 |
+ cheight=video_param_table[line_to_vpti[line]].cheight; |
|
217 |
switch(vga_modes[line].memmodel) |
|
218 |
{ |
|
219 |
case PLANAR4: |
|
220 |
@@ -1581,7 +1610,7 @@ |
|
221 |
else |
|
222 |
{ |
|
223 |
// FIXME gfx mode not complete |
|
224 |
- cheight=vga_modes[line].cheight; |
|
225 |
+ cheight=video_param_table[line_to_vpti[line]].cheight; |
|
226 |
bpp=vga_modes[line].pixbits; |
|
227 |
while((count-->0) && (xcurs<nbcols)) |
|
228 |
{ |
|
229 |
@@ -1641,7 +1670,7 @@ |
|
230 |
else |
|
231 |
{ |
|
232 |
// FIXME gfx mode not complete |
|
233 |
- cheight=vga_modes[line].cheight; |
|
234 |
+ cheight=video_param_table[line_to_vpti[line]].cheight; |
|
235 |
bpp=vga_modes[line].pixbits; |
|
236 |
while((count-->0) && (xcurs<nbcols)) |
|
237 |
{ |
|
238 |
@@ -1949,7 +1978,7 @@ |
|
239 |
else |
|
240 |
{ |
|
241 |
// FIXME gfx mode not complete |
|
242 |
- cheight=vga_modes[line].cheight; |
|
243 |
+ cheight=video_param_table[line_to_vpti[line]].cheight; |
|
244 |
bpp=vga_modes[line].pixbits; |
|
245 |
switch(vga_modes[line].memmodel) |
|
246 |
{ |
|
247 |
Index: vgatables.h |
|
248 |
=================================================================== |
|
249 |
RCS file: /sources/vgabios/vgabios/vgatables.h,v |
|
250 |
retrieving revision 1.9 |
|
251 |
diff -u -w -r1.9 vgatables.h |
|
252 |
--- vgatables.h 21 Sep 2005 18:45:20 -0000 1.9 |
|
253 |
+++ vgatables.h 25 Mar 2006 01:19:04 -0000 |
|
254 |
@@ -77,7 +77,7 @@ |
|
255 |
* Tables of default values for each mode |
|
256 |
* |
|
257 |
*/ |
|
258 |
-#define MODE_MAX 0x14 |
|
259 |
+#define MODE_MAX 15 |
|
260 |
#define TEXT 0x00 |
|
261 |
#define GRAPH 0x01 |
|
262 |
|
|
263 |
@@ -96,126 +96,38 @@ |
|
264 |
|
|
265 |
typedef struct |
|
266 |
{Bit8u svgamode; |
|
267 |
- Bit16u vesamode; |
|
268 |
Bit8u class; /* TEXT, GRAPH */ |
|
269 |
Bit8u memmodel; /* CTEXT,MTEXT,CGA,PL1,PL2,PL4,P8,P15,P16,P24,P32 */ |
|
270 |
- Bit8u nbpages; |
|
271 |
Bit8u pixbits; |
|
272 |
- Bit16u swidth, sheight; |
|
273 |
- Bit16u twidth, theight; |
|
274 |
- Bit16u cwidth, cheight; |
|
275 |
Bit16u sstart; |
|
276 |
- Bit16u slength; |
|
277 |
- Bit8u miscreg; |
|
278 |
Bit8u pelmask; |
|
279 |
- Bit8u crtcmodel; |
|
280 |
- Bit8u actlmodel; |
|
281 |
- Bit8u grdcmodel; |
|
282 |
- Bit8u sequmodel; |
|
283 |
Bit8u dacmodel; /* 0 1 2 3 */ |
|
284 |
} VGAMODES; |
|
285 |
|
|
286 |
static VGAMODES vga_modes[MODE_MAX+1]= |
|
287 |
-{//mode vesa class model pg bits sw sh tw th cw ch sstart slength misc pelm crtc actl gdc sequ dac |
|
288 |
- {0x00, 0xFFFF, TEXT, CTEXT, 8, 4, 360, 400, 40, 25, 9, 16, 0xB800, 0x0800, 0x67, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x02}, |
|
289 |
- {0x01, 0xFFFF, TEXT, CTEXT, 8, 4, 360, 400, 40, 25, 9, 16, 0xB800, 0x0800, 0x67, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x02}, |
|
290 |
- {0x02, 0xFFFF, TEXT, CTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB800, 0x1000, 0x67, 0xFF, 0x01, 0x00, 0x00, 0x01, 0x02}, |
|
291 |
- {0x03, 0xFFFF, TEXT, CTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB800, 0x1000, 0x67, 0xFF, 0x01, 0x00, 0x00, 0x01, 0x02}, |
|
292 |
- {0x04, 0xFFFF, GRAPH, CGA, 4, 2, 320, 200, 40, 25, 8, 8, 0xB800, 0x0800, 0x63, 0xFF, 0x02, 0x01, 0x01, 0x02, 0x01}, |
|
293 |
- {0x05, 0xFFFF, GRAPH, CGA, 1, 2, 320, 200, 40, 25, 8, 8, 0xB800, 0x0800, 0x63, 0xFF, 0x02, 0x01, 0x01, 0x02, 0x01}, |
|
294 |
- {0x06, 0xFFFF, GRAPH, CGA, 1, 1, 640, 200, 80, 25, 8, 8, 0xB800, 0x1000, 0x63, 0xFF, 0x03, 0x02, 0x02, 0x03, 0x01}, |
|
295 |
- {0x07, 0xFFFF, TEXT, MTEXT, 4, 4, 720, 400, 80, 25, 9, 16, 0xB000, 0x1000, 0x66, 0xFF, 0x04, 0x03, 0x03, 0x01, 0x00}, |
|
296 |
- {0x0D, 0xFFFF, GRAPH, PLANAR4, 8, 4, 320, 200, 40, 25, 8, 8, 0xA000, 0x2000, 0x63, 0xFF, 0x05, 0x04, 0x04, 0x04, 0x01}, |
|
297 |
- {0x0E, 0xFFFF, GRAPH, PLANAR4, 4, 4, 640, 200, 80, 25, 8, 8, 0xA000, 0x4000, 0x63, 0xFF, 0x06, 0x04, 0x04, 0x05, 0x01}, |
|
298 |
- {0x0F, 0xFFFF, GRAPH, PLANAR1, 2, 1, 640, 350, 80, 25, 8, 14, 0xA000, 0x8000, 0xa3, 0xFF, 0x07, 0x05, 0x04, 0x05, 0x00}, |
|
299 |
- {0x10, 0xFFFF, GRAPH, PLANAR4, 2, 4, 640, 350, 80, 25, 8, 14, 0xA000, 0x8000, 0xa3, 0xFF, 0x07, 0x06, 0x04, 0x05, 0x02}, |
|
300 |
- {0x11, 0xFFFF, GRAPH, PLANAR1, 1, 1, 640, 480, 80, 30, 8, 16, 0xA000, 0x0000, 0xe3, 0xFF, 0x08, 0x07, 0x04, 0x05, 0x02}, |
|
301 |
- {0x12, 0xFFFF, GRAPH, PLANAR4, 1, 4, 640, 480, 80, 30, 8, 16, 0xA000, 0x0000, 0xe3, 0xFF, 0x08, 0x06, 0x04, 0x05, 0x02}, |
|
302 |
- {0x13, 0xFFFF, GRAPH, LINEAR8, 1, 8, 320, 200, 40, 25, 8, 8, 0xA000, 0x0000, 0x63, 0xFF, 0x09, 0x08, 0x05, 0x06, 0x03}, |
|
303 |
- {0x6A, 0xFFFF, GRAPH, PLANAR4, 1, 4, 800, 600,100, 37, 8, 16, 0xA000, 0x0000, 0xe3, 0xFF, 0x0A, 0x06, 0x04, 0x05, 0x02} |
|
304 |
-}; |
|
305 |
- |
|
306 |
-/* CRTC */ |
|
307 |
-#define CRTC_MAX_REG 0x18 |
|
308 |
-#define CRTC_MAX_MODEL 0x0A |
|
309 |
-static Bit8u crtc_access[CRTC_MAX_REG+1]= |
|
310 |
-{ /* 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 */ |
|
311 |
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 |
|
312 |
-}; |
|
313 |
-static Bit8u crtc_regs[CRTC_MAX_MODEL+1][CRTC_MAX_REG+1]= |
|
314 |
-{/* Model 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 */ |
|
315 |
- /* 00 */ 0x2d,0x27,0x28,0x90,0x2b,0xa0,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x1f,0x96,0xb9,0xa3,0xff, |
|
316 |
- /* 01 */ 0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,0xff, |
|
317 |
- /* 02 */ 0x2d,0x27,0x28,0x90,0x2b,0x80,0xbf,0x1f,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xa2,0xff, |
|
318 |
- /* 03 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x00,0x96,0xb9,0xc2,0xff, |
|
319 |
- /* 04 */ 0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x0f,0x96,0xb9,0xa3,0xff, |
|
320 |
- /* 05 */ 0x2d,0x27,0x28,0x90,0x2b,0x80,0xbf,0x1f,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xe3,0xff, |
|
321 |
- /* 06 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x00,0x96,0xb9,0xe3,0xff, |
|
322 |
- /* 07 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x85,0x5d,0x28,0x0f,0x63,0xba,0xe3,0xff, |
|
323 |
- /* 08 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0xea,0x8c,0xdf,0x28,0x00,0xe7,0x04,0xe3,0xff, |
|
324 |
- /* 09 */ 0x5f,0x4f,0x50,0x82,0x54,0x80,0xbf,0x1f,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x8e,0x8f,0x28,0x40,0x96,0xb9,0xa3,0xff, |
|
325 |
- /* 0A */ 0x7f,0x63,0x63,0x83,0x6b,0x1b,0x72,0xf0,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x59,0x8d,0x57,0x32,0x00,0x57,0x73,0xe3,0xff |
|
326 |
-}; |
|
327 |
- |
|
328 |
-/* Attribute Controler 0x3c0 */ |
|
329 |
-#define ACTL_MAX_REG 0x14 |
|
330 |
-#define ACTL_MAX_MODEL 0x08 |
|
331 |
- |
|
332 |
-static Bit8u actl_access[ACTL_MAX_REG+1]= |
|
333 |
-{/* 00 01 02 03 04 05 06 07 08 09 0A 0B OC OD OE OF 10 11 12 13 14 */ |
|
334 |
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 |
|
335 |
-}; |
|
336 |
- |
|
337 |
-static Bit8u actl_regs[ACTL_MAX_MODEL+1][ACTL_MAX_REG+1]= |
|
338 |
-{/* Model 00 01 02 03 04 05 06 07 08 09 0A 0B OC OD OE OF 10 11 12 13 14 */ |
|
339 |
- /* 00 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x0c,0x00,0x0f,0x08,0x00, |
|
340 |
- /* 01 */ 0x00,0x13,0x15,0x17,0x02,0x04,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x01,0x00,0x03,0x00,0x00, |
|
341 |
- /* 02 */ 0x00,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x01,0x00,0x01,0x00,0x00, |
|
342 |
- /* 03 */ 0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x0e,0x00,0x0f,0x08,0x00, |
|
343 |
- /* 04 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x01,0x00,0x0f,0x00,0x00, |
|
344 |
- /* 05 */ 0x00,0x08,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x18,0x00,0x00,0x01,0x00,0x01,0x00,0x00, |
|
345 |
- /* 06 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00, |
|
346 |
- /* 07 */ 0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x00,0x3f,0x01,0x00,0x0f,0x00,0x00, |
|
347 |
- /* 08 */ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x41,0x00,0x0f,0x00,0x00 |
|
348 |
-}; |
|
349 |
- |
|
350 |
-/* Sequencer 0x3c4 */ |
|
351 |
-#define SEQU_MAX_REG 0x04 |
|
352 |
-#define SEQU_MAX_MODEL 0x06 |
|
353 |
- |
|
354 |
-static Bit8u sequ_access[SEQU_MAX_REG+1]= |
|
355 |
-{ /* 00 01 02 03 04 */ |
|
356 |
- 0x00,0x00,0x00,0x00,0x00 |
|
357 |
-}; |
|
358 |
- |
|
359 |
-static Bit8u sequ_regs[SEQU_MAX_MODEL+1][SEQU_MAX_REG+1]= |
|
360 |
-{/* Model 00 01 02 03 04 */ |
|
361 |
- /* 00 */ 0x03,0x08,0x03,0x00,0x02, |
|
362 |
- /* 01 */ 0x03,0x00,0x03,0x00,0x02, |
|
363 |
- /* 02 */ 0x03,0x09,0x03,0x00,0x02, |
|
364 |
- /* 03 */ 0x03,0x01,0x01,0x00,0x06, |
|
365 |
- /* 04 */ 0x03,0x09,0x0f,0x00,0x06, |
|
366 |
- /* 05 */ 0x03,0x01,0x0f,0x00,0x06, |
|
367 |
- /* 06 */ 0x03,0x01,0x0f,0x00,0x0e |
|
368 |
-}; |
|
369 |
- |
|
370 |
-/* Graphic ctl 0x3ce */ |
|
371 |
-#define GRDC_MAX_REG 0x08 |
|
372 |
-#define GRDC_MAX_MODEL 0x05 |
|
373 |
- |
|
374 |
-static Bit8u grdc_access[GRDC_MAX_REG+1]= |
|
375 |
-{ /* 00 01 02 03 04 05 06 07 08 */ |
|
376 |
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 |
|
377 |
-}; |
|
378 |
- |
|
379 |
-static Bit8u grdc_regs[GRDC_MAX_MODEL+1][GRDC_MAX_REG+1]= |
|
380 |
-{/* Model 00 01 02 03 04 05 06 07 08 */ |
|
381 |
- /* 00 */ 0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x0f,0xff, |
|
382 |
- /* 01 */ 0x00,0x00,0x00,0x00,0x00,0x30,0x0f,0x0f,0xff, |
|
383 |
- /* 02 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x0d,0x0f,0xff, |
|
384 |
- /* 03 */ 0x00,0x00,0x00,0x00,0x00,0x10,0x0a,0x0f,0xff, |
|
385 |
- /* 04 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff, |
|
386 |
- /* 05 */ 0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f,0xff |
|
387 |
+{//mode class model bits sstart pelm dac |
|
388 |
+ {0x00, TEXT, CTEXT, 4, 0xB800, 0xFF, 0x02}, |
|
389 |
+ {0x01, TEXT, CTEXT, 4, 0xB800, 0xFF, 0x02}, |
|
390 |
+ {0x02, TEXT, CTEXT, 4, 0xB800, 0xFF, 0x02}, |
|
391 |
+ {0x03, TEXT, CTEXT, 4, 0xB800, 0xFF, 0x02}, |
|
392 |
+ {0x04, GRAPH, CGA, 2, 0xB800, 0xFF, 0x01}, |
|
393 |
+ {0x05, GRAPH, CGA, 2, 0xB800, 0xFF, 0x01}, |
|
394 |
+ {0x06, GRAPH, CGA, 1, 0xB800, 0xFF, 0x01}, |
|
395 |
+ {0x07, TEXT, MTEXT, 4, 0xB000, 0xFF, 0x00}, |
|
396 |
+ {0x0D, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x01}, |
|
397 |
+ {0x0E, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x01}, |
|
398 |
+ {0x0F, GRAPH, PLANAR1, 1, 0xA000, 0xFF, 0x00}, |
|
399 |
+ {0x10, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x02}, |
|
400 |
+ {0x11, GRAPH, PLANAR1, 1, 0xA000, 0xFF, 0x02}, |
|
401 |
+ {0x12, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x02}, |
|
402 |
+ {0x13, GRAPH, LINEAR8, 8, 0xA000, 0xFF, 0x03}, |
|
403 |
+ {0x6A, GRAPH, PLANAR4, 4, 0xA000, 0xFF, 0x02} |
|
404 |
+}; |
|
405 |
+ |
|
406 |
+/* convert index in vga_modes[] to index in video_param_table[] */ |
|
407 |
+static Bit8u line_to_vpti[MODE_MAX+1]={ |
|
408 |
+ 0x17, 0x17, 0x18, 0x18, 0x04, 0x05, 0x06, 0x07, |
|
409 |
+ 0x0d, 0x0e, 0x11, 0x12, 0x1a, 0x1b, 0x1c, 0x1d, |
|
97 | 410 |
}; |
411 |
|
|
412 |
/* Default Palette */ |
|
413 |
@@ -224,6 +136,398 @@ |
|
414 |
static Bit8u dac_regs[DAC_MAX_MODEL+1]= |
|
415 |
{0x3f,0x3f,0x3f,0xff}; |
|
416 |
|
|
417 |
+/* standard BIOS Video Parameter Table */ |
|
418 |
+typedef struct { |
|
419 |
+ Bit8u twidth; |
|
420 |
+ Bit8u theightm1; |
|
421 |
+ Bit8u cheight; |
|
422 |
+ Bit8u slength_l; |
|
423 |
+ Bit8u slength_h; |
|
424 |
+ Bit8u sequ_regs[4]; |
|
425 |
+ Bit8u miscreg; |
|
426 |
+ Bit8u crtc_regs[25]; |
|
427 |
+ Bit8u actl_regs[20]; |
|
428 |
+ Bit8u grdc_regs[9]; |
|
429 |
+} VideoParamTableEntry; |
|
430 |
+ |
|
431 |
+static VideoParamTableEntry video_param_table[30] = { |
|
432 |
+{ |
|
433 |
+ /* index=0x00 no mode defined */ |
|
434 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
435 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
436 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
437 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
438 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
439 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
440 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
441 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
442 |
+}, |
|
443 |
+{ |
|
444 |
+ /* index=0x01 no mode defined */ |
|
445 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
446 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
447 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
448 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
449 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
450 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
451 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
452 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
453 |
+}, |
|
454 |
+{ |
|
455 |
+ /* index=0x02 no mode defined */ |
|
456 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
457 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
458 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
459 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
460 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
461 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
462 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
463 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
464 |
+}, |
|
465 |
+{ |
|
466 |
+ /* index=0x03 no mode defined */ |
|
467 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
468 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
469 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
470 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
471 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
472 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
473 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
474 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
475 |
+}, |
|
476 |
+{ |
|
477 |
+ /* index=0x04 vga mode 0x04 */ |
|
478 |
+ 40, 24, 8, 0x00, 0x08, /* tw, th-1, ch, slength */ |
|
479 |
+ 0x09, 0x03, 0x00, 0x02, /* sequ_regs */ |
|
480 |
+ 0x63, /* miscreg */ |
|
481 |
+ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f, |
|
482 |
+ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
483 |
+ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2, |
|
484 |
+ 0xff, /* crtc_regs */ |
|
485 |
+ 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07, |
|
486 |
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, |
|
487 |
+ 0x01, 0x00, 0x03, 0x00, /* actl_regs */ |
|
488 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff, /* grdc_regs */ |
|
489 |
+}, |
|
490 |
+{ |
|
491 |
+ /* index=0x05 vga mode 0x05 */ |
|
492 |
+ 40, 24, 8, 0x00, 0x08, /* tw, th-1, ch, slength */ |
|
493 |
+ 0x09, 0x03, 0x00, 0x02, /* sequ_regs */ |
|
494 |
+ 0x63, /* miscreg */ |
|
495 |
+ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f, |
|
496 |
+ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
497 |
+ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2, |
|
498 |
+ 0xff, /* crtc_regs */ |
|
499 |
+ 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07, |
|
500 |
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, |
|
501 |
+ 0x01, 0x00, 0x03, 0x00, /* actl_regs */ |
|
502 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff, /* grdc_regs */ |
|
503 |
+}, |
|
504 |
+{ |
|
505 |
+ /* index=0x06 vga mode 0x06 */ |
|
506 |
+ 80, 24, 8, 0x00, 0x10, /* tw, th-1, ch, slength */ |
|
507 |
+ 0x01, 0x01, 0x00, 0x06, /* sequ_regs */ |
|
508 |
+ 0x63, /* miscreg */ |
|
509 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, |
|
510 |
+ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
511 |
+ 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xc2, |
|
512 |
+ 0xff, /* crtc_regs */ |
|
513 |
+ 0x00, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, |
|
514 |
+ 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, |
|
515 |
+ 0x01, 0x00, 0x01, 0x00, /* actl_regs */ |
|
516 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x0f, 0xff, /* grdc_regs */ |
|
517 |
+}, |
|
518 |
+{ |
|
519 |
+ /* index=0x07 vga mode 0x07 */ |
|
520 |
+ 80, 24, 16, 0x00, 0x10, /* tw, th-1, ch, slength */ |
|
521 |
+ 0x00, 0x03, 0x00, 0x02, /* sequ_regs */ |
|
522 |
+ 0x66, /* miscreg */ |
|
523 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, |
|
524 |
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
|
525 |
+ 0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3, |
|
526 |
+ 0xff, /* crtc_regs */ |
|
527 |
+ 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, |
|
528 |
+ 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, |
|
529 |
+ 0x0e, 0x00, 0x0f, 0x08, /* actl_regs */ |
|
530 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff, /* grdc_regs */ |
|
531 |
+}, |
|
532 |
+{ |
|
533 |
+ /* index=0x08 no mode defined */ |
|
534 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
535 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
536 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
537 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
538 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
539 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
540 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
541 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
542 |
+}, |
|
543 |
+{ |
|
544 |
+ /* index=0x09 no mode defined */ |
|
545 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
546 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
547 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
548 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
549 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
550 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
551 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
552 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
553 |
+}, |
|
554 |
+{ |
|
555 |
+ /* index=0x0a no mode defined */ |
|
556 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
557 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
558 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
559 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
560 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
561 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
562 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
563 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
564 |
+}, |
|
565 |
+{ |
|
566 |
+ /* index=0x0b no mode defined */ |
|
567 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
568 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
569 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
570 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
571 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
572 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
573 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
574 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
575 |
+}, |
|
576 |
+{ |
|
577 |
+ /* index=0x0c no mode defined */ |
|
578 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
579 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
580 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
581 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
582 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
583 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
584 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
585 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
586 |
+}, |
|
587 |
+{ |
|
588 |
+ /* index=0x0d vga mode 0x0d */ |
|
589 |
+ 40, 24, 8, 0x00, 0x20, /* tw, th-1, ch, slength */ |
|
590 |
+ 0x09, 0x0f, 0x00, 0x06, /* sequ_regs */ |
|
591 |
+ 0x63, /* miscreg */ |
|
592 |
+ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f, |
|
593 |
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
594 |
+ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xe3, |
|
595 |
+ 0xff, /* crtc_regs */ |
|
596 |
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
|
597 |
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, |
|
598 |
+ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ |
|
599 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ |
|
600 |
+}, |
|
601 |
+{ |
|
602 |
+ /* index=0x0e vga mode 0x0e */ |
|
603 |
+ 80, 24, 8, 0x00, 0x40, /* tw, th-1, ch, slength */ |
|
604 |
+ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ |
|
605 |
+ 0x63, /* miscreg */ |
|
606 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, |
|
607 |
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
608 |
+ 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xe3, |
|
609 |
+ 0xff, /* crtc_regs */ |
|
610 |
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
|
611 |
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, |
|
612 |
+ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ |
|
613 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ |
|
614 |
+}, |
|
615 |
+{ |
|
616 |
+ /* index=0x0f no mode defined */ |
|
617 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
618 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
619 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
620 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
621 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
622 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
623 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
624 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
625 |
+}, |
|
626 |
+{ |
|
627 |
+ /* index=0x10 no mode defined */ |
|
628 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
629 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
630 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
631 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
632 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
633 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
634 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
635 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
636 |
+}, |
|
637 |
+{ |
|
638 |
+ /* index=0x11 vga mode 0x0f */ |
|
639 |
+ 80, 24, 14, 0x00, 0x80, /* tw, th-1, ch, slength */ |
|
640 |
+ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ |
|
641 |
+ 0xa3, /* miscreg */ |
|
642 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, |
|
643 |
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
644 |
+ 0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3, |
|
645 |
+ 0xff, /* crtc_regs */ |
|
646 |
+ 0x00, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, |
|
647 |
+ 0x00, 0x08, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, |
|
648 |
+ 0x01, 0x00, 0x01, 0x00, /* actl_regs */ |
|
649 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ |
|
650 |
+}, |
|
651 |
+{ |
|
652 |
+ /* index=0x12 vga mode 0x10 */ |
|
653 |
+ 80, 24, 14, 0x00, 0x80, /* tw, th-1, ch, slength */ |
|
654 |
+ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ |
|
655 |
+ 0xa3, /* miscreg */ |
|
656 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, |
|
657 |
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
658 |
+ 0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3, |
|
659 |
+ 0xff, /* crtc_regs */ |
|
660 |
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, |
|
661 |
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, |
|
662 |
+ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ |
|
663 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ |
|
664 |
+}, |
|
665 |
+{ |
|
666 |
+ /* index=0x13 no mode defined */ |
|
667 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
668 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
669 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
670 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
671 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
672 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
673 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
674 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
675 |
+}, |
|
676 |
+{ |
|
677 |
+ /* index=0x14 no mode defined */ |
|
678 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
679 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
680 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
681 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
682 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
683 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
684 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
685 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
686 |
+}, |
|
687 |
+{ |
|
688 |
+ /* index=0x15 no mode defined */ |
|
689 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
690 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
691 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
692 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
693 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
694 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
695 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
696 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
697 |
+}, |
|
698 |
+{ |
|
699 |
+ /* index=0x16 no mode defined */ |
|
700 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
701 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
702 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
703 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
704 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
705 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
706 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
707 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
708 |
+}, |
|
709 |
+{ |
|
710 |
+ /* index=0x17 vga mode 0x01 */ |
|
711 |
+ 40, 24, 16, 0x00, 0x08, /* tw, th-1, ch, slength */ |
|
712 |
+ 0x08, 0x03, 0x00, 0x02, /* sequ_regs */ |
|
713 |
+ 0x67, /* miscreg */ |
|
714 |
+ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f, |
|
715 |
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
|
716 |
+ 0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3, |
|
717 |
+ 0xff, /* crtc_regs */ |
|
718 |
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, |
|
719 |
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, |
|
720 |
+ 0x0c, 0x00, 0x0f, 0x08, /* actl_regs */ |
|
721 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff, /* grdc_regs */ |
|
722 |
+}, |
|
723 |
+{ |
|
724 |
+ /* index=0x18 vga mode 0x03 */ |
|
725 |
+ 80, 24, 16, 0x00, 0x10, /* tw, th-1, ch, slength */ |
|
726 |
+ 0x00, 0x03, 0x00, 0x02, /* sequ_regs */ |
|
727 |
+ 0x67, /* miscreg */ |
|
728 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, |
|
729 |
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
|
730 |
+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, |
|
731 |
+ 0xff, /* crtc_regs */ |
|
732 |
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, |
|
733 |
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, |
|
734 |
+ 0x0c, 0x00, 0x0f, 0x08, /* actl_regs */ |
|
735 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff, /* grdc_regs */ |
|
736 |
+}, |
|
737 |
+{ |
|
738 |
+ /* index=0x19 vga mode 0x07 */ |
|
739 |
+ 80, 24, 16, 0x00, 0x10, /* tw, th-1, ch, slength */ |
|
740 |
+ 0x00, 0x03, 0x00, 0x02, /* sequ_regs */ |
|
741 |
+ 0x66, /* miscreg */ |
|
742 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, |
|
743 |
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
|
744 |
+ 0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3, |
|
745 |
+ 0xff, /* crtc_regs */ |
|
746 |
+ 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, |
|
747 |
+ 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, |
|
748 |
+ 0x0e, 0x00, 0x0f, 0x08, /* actl_regs */ |
|
749 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff, /* grdc_regs */ |
|
750 |
+}, |
|
751 |
+{ |
|
752 |
+ /* index=0x1a vga mode 0x11 */ |
|
753 |
+ 80, 29, 16, 0x00, 0x00, /* tw, th-1, ch, slength */ |
|
754 |
+ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ |
|
755 |
+ 0xe3, /* miscreg */ |
|
756 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, |
|
757 |
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
758 |
+ 0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, |
|
759 |
+ 0xff, /* crtc_regs */ |
|
760 |
+ 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, |
|
761 |
+ 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, |
|
762 |
+ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ |
|
763 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ |
|
764 |
+}, |
|
765 |
+{ |
|
766 |
+ /* index=0x1b vga mode 0x12 */ |
|
767 |
+ 80, 29, 16, 0x00, 0x00, /* tw, th-1, ch, slength */ |
|
768 |
+ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ |
|
769 |
+ 0xe3, /* miscreg */ |
|
770 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, |
|
771 |
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
772 |
+ 0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, |
|
773 |
+ 0xff, /* crtc_regs */ |
|
774 |
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, |
|
775 |
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, |
|
776 |
+ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ |
|
777 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ |
|
778 |
+}, |
|
779 |
+{ |
|
780 |
+ /* index=0x1c vga mode 0x13 */ |
|
781 |
+ 40, 24, 8, 0x00, 0x00, /* tw, th-1, ch, slength */ |
|
782 |
+ 0x01, 0x0f, 0x00, 0x0e, /* sequ_regs */ |
|
783 |
+ 0x63, /* miscreg */ |
|
784 |
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, |
|
785 |
+ 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
786 |
+ 0x9c, 0x8e, 0x8f, 0x28, 0x40, 0x96, 0xb9, 0xa3, |
|
787 |
+ 0xff, /* crtc_regs */ |
|
788 |
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
|
789 |
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, |
|
790 |
+ 0x41, 0x00, 0x0f, 0x00, /* actl_regs */ |
|
791 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff, /* grdc_regs */ |
|
792 |
+}, |
|
793 |
+{ |
|
794 |
+ /* index=0x1d vga mode 0x6a */ |
|
795 |
+ 100, 36, 16, 0x00, 0x00, /* tw, th-1, ch, slength */ |
|
796 |
+ 0x01, 0x0f, 0x00, 0x06, /* sequ_regs */ |
|
797 |
+ 0xe3, /* miscreg */ |
|
798 |
+ 0x7f, 0x63, 0x63, 0x83, 0x6b, 0x1b, 0x72, 0xf0, |
|
799 |
+ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
800 |
+ 0x59, 0x8d, 0x57, 0x32, 0x00, 0x57, 0x73, 0xe3, |
|
801 |
+ 0xff, /* crtc_regs */ |
|
802 |
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, |
|
803 |
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, |
|
804 |
+ 0x01, 0x00, 0x0f, 0x00, /* actl_regs */ |
|
805 |
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, /* grdc_regs */ |
|
806 |
+}, |
|
807 |
+}; |
|
808 |
+ |
|
809 |
/* Mono */ |
|
810 |
static Bit8u palette0[63+1][3]= |
|
811 |
{ |
Also available in: Unified diff