root / target-sparc / op_helper.c @ 273af660
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#include "exec.h" |
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#include "host-utils.h" |
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|
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//#define DEBUG_PCALL
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//#define DEBUG_MMU
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//#define DEBUG_MXCC
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//#define DEBUG_UNALIGNED
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//#define DEBUG_UNASSIGNED
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|
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, args...) \
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do { printf("MMU: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF_MMU(fmt, args...)
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#endif
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|
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#ifdef DEBUG_MXCC
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#define DPRINTF_MXCC(fmt, args...) \
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do { printf("MXCC: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF_MXCC(fmt, args...)
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#endif
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|
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void raise_exception(int tt) |
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{ |
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env->exception_index = tt; |
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cpu_loop_exit(); |
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} |
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|
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void check_ieee_exceptions()
|
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{ |
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T0 = get_float_exception_flags(&env->fp_status); |
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if (T0)
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{ |
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/* Copy IEEE 754 flags into FSR */
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if (T0 & float_flag_invalid)
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env->fsr |= FSR_NVC; |
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if (T0 & float_flag_overflow)
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env->fsr |= FSR_OFC; |
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if (T0 & float_flag_underflow)
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env->fsr |= FSR_UFC; |
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if (T0 & float_flag_divbyzero)
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env->fsr |= FSR_DZC; |
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if (T0 & float_flag_inexact)
|
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env->fsr |= FSR_NXC; |
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|
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if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) |
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{ |
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/* Unmasked exception, generate a trap */
|
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env->fsr |= FSR_FTT_IEEE_EXCP; |
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raise_exception(TT_FP_EXCP); |
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} |
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else
|
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{ |
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/* Accumulate exceptions */
|
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env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
|
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} |
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} |
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} |
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|
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#ifdef USE_INT_TO_FLOAT_HELPERS
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void do_fitos(void) |
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{ |
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set_float_exception_flags(0, &env->fp_status);
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FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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|
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void do_fitod(void) |
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{ |
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DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
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} |
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#ifdef TARGET_SPARC64
|
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void do_fxtos(void) |
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{ |
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set_float_exception_flags(0, &env->fp_status);
|
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FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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|
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void do_fxtod(void) |
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{ |
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set_float_exception_flags(0, &env->fp_status);
|
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DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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#endif
|
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#endif
|
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|
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void do_fabss(void) |
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{ |
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FT0 = float32_abs(FT1); |
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} |
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|
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#ifdef TARGET_SPARC64
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void do_fabsd(void) |
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{ |
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DT0 = float64_abs(DT1); |
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} |
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#endif
|
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|
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void do_fsqrts(void) |
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{ |
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set_float_exception_flags(0, &env->fp_status);
|
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FT0 = float32_sqrt(FT1, &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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|
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void do_fsqrtd(void) |
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{ |
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set_float_exception_flags(0, &env->fp_status);
|
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DT0 = float64_sqrt(DT1, &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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|
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#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
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void glue(do_, name) (void) \ |
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{ \ |
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
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switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
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case float_relation_unordered: \
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; \ |
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if ((env->fsr & FSR_NVM) || TRAP) { \
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env->fsr |= T0; \ |
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env->fsr |= FSR_NVC; \ |
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env->fsr |= FSR_FTT_IEEE_EXCP; \ |
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raise_exception(TT_FP_EXCP); \ |
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} else { \
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env->fsr |= FSR_NVA; \ |
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} \ |
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break; \
|
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case float_relation_less: \
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T0 = FSR_FCC0 << FS; \ |
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break; \
|
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case float_relation_greater: \
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T0 = FSR_FCC1 << FS; \ |
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break; \
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default: \
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T0 = 0; \
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break; \
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} \ |
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env->fsr |= T0; \ |
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} |
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|
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GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
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GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
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|
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GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); |
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GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
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|
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#ifdef TARGET_SPARC64
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GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
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GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
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|
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GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); |
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
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|
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GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); |
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GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
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|
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GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); |
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GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
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|
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GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1); |
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GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
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|
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GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1); |
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GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
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#endif
|
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|
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#ifndef TARGET_SPARC64
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#ifndef CONFIG_USER_ONLY
|
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|
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#ifdef DEBUG_MXCC
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static void dump_mxcc(CPUState *env) |
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{ |
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printf("mxccdata: %016llx %016llx %016llx %016llx\n",
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env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); |
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printf("mxccregs: %016llx %016llx %016llx %016llx\n"
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" %016llx %016llx %016llx %016llx\n",
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env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], |
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env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); |
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} |
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#endif
|
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|
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void helper_ld_asi(int asi, int size, int sign) |
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{ |
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uint32_t ret = 0;
|
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uint64_t tmp; |
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#ifdef DEBUG_MXCC
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uint32_t last_T0 = T0; |
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#endif
|
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|
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switch (asi) {
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case 2: /* SuperSparc MXCC registers */ |
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switch (T0) {
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case 0x01c00a00: /* MXCC control register */ |
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if (size == 8) { |
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ret = env->mxccregs[3];
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T0 = env->mxccregs[3] >> 32; |
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} else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
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break;
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case 0x01c00a04: /* MXCC control register */ |
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if (size == 4) |
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ret = env->mxccregs[3];
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
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break;
|
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case 0x01c00f00: /* MBus port address register */ |
211 |
if (size == 8) { |
212 |
ret = env->mxccregs[7];
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T0 = env->mxccregs[7] >> 32; |
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} else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
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break;
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default:
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DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
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break;
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} |
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DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
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"T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
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#ifdef DEBUG_MXCC
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dump_mxcc(env); |
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#endif
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break;
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case 3: /* MMU probe */ |
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{ |
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int mmulev;
|
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|
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mmulev = (T0 >> 8) & 15; |
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if (mmulev > 4) |
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ret = 0;
|
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else {
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ret = mmu_probe(env, T0, mmulev); |
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//bswap32s(&ret);
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} |
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DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
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} |
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break;
|
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case 4: /* read MMU regs */ |
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{ |
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int reg = (T0 >> 8) & 0xf; |
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|
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ret = env->mmuregs[reg]; |
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if (reg == 3) /* Fault status cleared on read */ |
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env->mmuregs[reg] = 0;
|
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DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
|
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} |
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break;
|
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case 9: /* Supervisor code access */ |
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switch(size) {
|
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case 1: |
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ret = ldub_code(T0); |
255 |
break;
|
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case 2: |
257 |
ret = lduw_code(T0 & ~1);
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break;
|
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default:
|
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case 4: |
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ret = ldl_code(T0 & ~3);
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break;
|
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case 8: |
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tmp = ldq_code(T0 & ~7);
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ret = tmp >> 32;
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T0 = tmp & 0xffffffff;
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break;
|
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} |
269 |
break;
|
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case 0xa: /* User data access */ |
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switch(size) {
|
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case 1: |
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ret = ldub_user(T0); |
274 |
break;
|
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case 2: |
276 |
ret = lduw_user(T0 & ~1);
|
277 |
break;
|
278 |
default:
|
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case 4: |
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ret = ldl_user(T0 & ~3);
|
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break;
|
282 |
case 8: |
283 |
tmp = ldq_user(T0 & ~7);
|
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ret = tmp >> 32;
|
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T0 = tmp & 0xffffffff;
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break;
|
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} |
288 |
break;
|
289 |
case 0xb: /* Supervisor data access */ |
290 |
switch(size) {
|
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case 1: |
292 |
ret = ldub_kernel(T0); |
293 |
break;
|
294 |
case 2: |
295 |
ret = lduw_kernel(T0 & ~1);
|
296 |
break;
|
297 |
default:
|
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case 4: |
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ret = ldl_kernel(T0 & ~3);
|
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break;
|
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case 8: |
302 |
tmp = ldq_kernel(T0 & ~7);
|
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ret = tmp >> 32;
|
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T0 = tmp & 0xffffffff;
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break;
|
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} |
307 |
break;
|
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case 0xc: /* I-cache tag */ |
309 |
case 0xd: /* I-cache data */ |
310 |
case 0xe: /* D-cache tag */ |
311 |
case 0xf: /* D-cache data */ |
312 |
break;
|
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case 0x20: /* MMU passthrough */ |
314 |
switch(size) {
|
315 |
case 1: |
316 |
ret = ldub_phys(T0); |
317 |
break;
|
318 |
case 2: |
319 |
ret = lduw_phys(T0 & ~1);
|
320 |
break;
|
321 |
default:
|
322 |
case 4: |
323 |
ret = ldl_phys(T0 & ~3);
|
324 |
break;
|
325 |
case 8: |
326 |
tmp = ldq_phys(T0 & ~7);
|
327 |
ret = tmp >> 32;
|
328 |
T0 = tmp & 0xffffffff;
|
329 |
break;
|
330 |
} |
331 |
break;
|
332 |
case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
333 |
case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
334 |
switch(size) {
|
335 |
case 1: |
336 |
ret = ldub_phys((target_phys_addr_t)T0 |
337 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
338 |
break;
|
339 |
case 2: |
340 |
ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
|
341 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
342 |
break;
|
343 |
default:
|
344 |
case 4: |
345 |
ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
|
346 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
347 |
break;
|
348 |
case 8: |
349 |
tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
|
350 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
351 |
ret = tmp >> 32;
|
352 |
T0 = tmp & 0xffffffff;
|
353 |
break;
|
354 |
} |
355 |
break;
|
356 |
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
357 |
default:
|
358 |
do_unassigned_access(T0, 0, 0, 1); |
359 |
ret = 0;
|
360 |
break;
|
361 |
} |
362 |
if (sign) {
|
363 |
switch(size) {
|
364 |
case 1: |
365 |
T1 = (int8_t) ret; |
366 |
break;
|
367 |
case 2: |
368 |
T1 = (int16_t) ret; |
369 |
break;
|
370 |
default:
|
371 |
T1 = ret; |
372 |
break;
|
373 |
} |
374 |
} |
375 |
else
|
376 |
T1 = ret; |
377 |
} |
378 |
|
379 |
void helper_st_asi(int asi, int size) |
380 |
{ |
381 |
switch(asi) {
|
382 |
case 2: /* SuperSparc MXCC registers */ |
383 |
switch (T0) {
|
384 |
case 0x01c00000: /* MXCC stream data register 0 */ |
385 |
if (size == 8) |
386 |
env->mxccdata[0] = ((uint64_t)T1 << 32) | T2; |
387 |
else
|
388 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
389 |
break;
|
390 |
case 0x01c00008: /* MXCC stream data register 1 */ |
391 |
if (size == 8) |
392 |
env->mxccdata[1] = ((uint64_t)T1 << 32) | T2; |
393 |
else
|
394 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
395 |
break;
|
396 |
case 0x01c00010: /* MXCC stream data register 2 */ |
397 |
if (size == 8) |
398 |
env->mxccdata[2] = ((uint64_t)T1 << 32) | T2; |
399 |
else
|
400 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
401 |
break;
|
402 |
case 0x01c00018: /* MXCC stream data register 3 */ |
403 |
if (size == 8) |
404 |
env->mxccdata[3] = ((uint64_t)T1 << 32) | T2; |
405 |
else
|
406 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
407 |
break;
|
408 |
case 0x01c00100: /* MXCC stream source */ |
409 |
if (size == 8) |
410 |
env->mxccregs[0] = ((uint64_t)T1 << 32) | T2; |
411 |
else
|
412 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
413 |
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); |
414 |
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); |
415 |
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); |
416 |
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); |
417 |
break;
|
418 |
case 0x01c00200: /* MXCC stream destination */ |
419 |
if (size == 8) |
420 |
env->mxccregs[1] = ((uint64_t)T1 << 32) | T2; |
421 |
else
|
422 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
423 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); |
424 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); |
425 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); |
426 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); |
427 |
break;
|
428 |
case 0x01c00a00: /* MXCC control register */ |
429 |
if (size == 8) |
430 |
env->mxccregs[3] = ((uint64_t)T1 << 32) | T2; |
431 |
else
|
432 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
433 |
break;
|
434 |
case 0x01c00a04: /* MXCC control register */ |
435 |
if (size == 4) |
436 |
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000) | T1; |
437 |
else
|
438 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
439 |
break;
|
440 |
case 0x01c00e00: /* MXCC error register */ |
441 |
if (size == 8) |
442 |
env->mxccregs[6] = ((uint64_t)T1 << 32) | T2; |
443 |
else
|
444 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
445 |
if (env->mxccregs[6] == 0xffffffffffffffffULL) { |
446 |
// this is probably a reset
|
447 |
} |
448 |
break;
|
449 |
case 0x01c00f00: /* MBus port address register */ |
450 |
if (size == 8) |
451 |
env->mxccregs[7] = ((uint64_t)T1 << 32) | T2; |
452 |
else
|
453 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
454 |
break;
|
455 |
default:
|
456 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
|
457 |
break;
|
458 |
} |
459 |
DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
|
460 |
#ifdef DEBUG_MXCC
|
461 |
dump_mxcc(env); |
462 |
#endif
|
463 |
break;
|
464 |
case 3: /* MMU flush */ |
465 |
{ |
466 |
int mmulev;
|
467 |
|
468 |
mmulev = (T0 >> 8) & 15; |
469 |
DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
470 |
switch (mmulev) {
|
471 |
case 0: // flush page |
472 |
tlb_flush_page(env, T0 & 0xfffff000);
|
473 |
break;
|
474 |
case 1: // flush segment (256k) |
475 |
case 2: // flush region (16M) |
476 |
case 3: // flush context (4G) |
477 |
case 4: // flush entire |
478 |
tlb_flush(env, 1);
|
479 |
break;
|
480 |
default:
|
481 |
break;
|
482 |
} |
483 |
#ifdef DEBUG_MMU
|
484 |
dump_mmu(env); |
485 |
#endif
|
486 |
return;
|
487 |
} |
488 |
case 4: /* write MMU regs */ |
489 |
{ |
490 |
int reg = (T0 >> 8) & 0xf; |
491 |
uint32_t oldreg; |
492 |
|
493 |
oldreg = env->mmuregs[reg]; |
494 |
switch(reg) {
|
495 |
case 0: |
496 |
env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); |
497 |
env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); |
498 |
// Mappings generated during no-fault mode or MMU
|
499 |
// disabled mode are invalid in normal mode
|
500 |
if (oldreg != env->mmuregs[reg])
|
501 |
tlb_flush(env, 1);
|
502 |
break;
|
503 |
case 2: |
504 |
env->mmuregs[reg] = T1; |
505 |
if (oldreg != env->mmuregs[reg]) {
|
506 |
/* we flush when the MMU context changes because
|
507 |
QEMU has no MMU context support */
|
508 |
tlb_flush(env, 1);
|
509 |
} |
510 |
break;
|
511 |
case 3: |
512 |
case 4: |
513 |
break;
|
514 |
default:
|
515 |
env->mmuregs[reg] = T1; |
516 |
break;
|
517 |
} |
518 |
if (oldreg != env->mmuregs[reg]) {
|
519 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
520 |
} |
521 |
#ifdef DEBUG_MMU
|
522 |
dump_mmu(env); |
523 |
#endif
|
524 |
return;
|
525 |
} |
526 |
case 0xa: /* User data access */ |
527 |
switch(size) {
|
528 |
case 1: |
529 |
stb_user(T0, T1); |
530 |
break;
|
531 |
case 2: |
532 |
stw_user(T0 & ~1, T1);
|
533 |
break;
|
534 |
default:
|
535 |
case 4: |
536 |
stl_user(T0 & ~3, T1);
|
537 |
break;
|
538 |
case 8: |
539 |
stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
540 |
break;
|
541 |
} |
542 |
break;
|
543 |
case 0xb: /* Supervisor data access */ |
544 |
switch(size) {
|
545 |
case 1: |
546 |
stb_kernel(T0, T1); |
547 |
break;
|
548 |
case 2: |
549 |
stw_kernel(T0 & ~1, T1);
|
550 |
break;
|
551 |
default:
|
552 |
case 4: |
553 |
stl_kernel(T0 & ~3, T1);
|
554 |
break;
|
555 |
case 8: |
556 |
stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
557 |
break;
|
558 |
} |
559 |
break;
|
560 |
case 0xc: /* I-cache tag */ |
561 |
case 0xd: /* I-cache data */ |
562 |
case 0xe: /* D-cache tag */ |
563 |
case 0xf: /* D-cache data */ |
564 |
case 0x10: /* I/D-cache flush page */ |
565 |
case 0x11: /* I/D-cache flush segment */ |
566 |
case 0x12: /* I/D-cache flush region */ |
567 |
case 0x13: /* I/D-cache flush context */ |
568 |
case 0x14: /* I/D-cache flush user */ |
569 |
break;
|
570 |
case 0x17: /* Block copy, sta access */ |
571 |
{ |
572 |
// value (T1) = src
|
573 |
// address (T0) = dst
|
574 |
// copy 32 bytes
|
575 |
unsigned int i; |
576 |
uint32_t src = T1 & ~3, dst = T0 & ~3, temp; |
577 |
|
578 |
for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
579 |
temp = ldl_kernel(src); |
580 |
stl_kernel(dst, temp); |
581 |
} |
582 |
} |
583 |
return;
|
584 |
case 0x1f: /* Block fill, stda access */ |
585 |
{ |
586 |
// value (T1, T2)
|
587 |
// address (T0) = dst
|
588 |
// fill 32 bytes
|
589 |
unsigned int i; |
590 |
uint32_t dst = T0 & 7;
|
591 |
uint64_t val; |
592 |
|
593 |
val = (((uint64_t)T1) << 32) | T2;
|
594 |
|
595 |
for (i = 0; i < 32; i += 8, dst += 8) |
596 |
stq_kernel(dst, val); |
597 |
} |
598 |
return;
|
599 |
case 0x20: /* MMU passthrough */ |
600 |
{ |
601 |
switch(size) {
|
602 |
case 1: |
603 |
stb_phys(T0, T1); |
604 |
break;
|
605 |
case 2: |
606 |
stw_phys(T0 & ~1, T1);
|
607 |
break;
|
608 |
case 4: |
609 |
default:
|
610 |
stl_phys(T0 & ~3, T1);
|
611 |
break;
|
612 |
case 8: |
613 |
stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
614 |
break;
|
615 |
} |
616 |
} |
617 |
return;
|
618 |
case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
619 |
case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
620 |
{ |
621 |
switch(size) {
|
622 |
case 1: |
623 |
stb_phys((target_phys_addr_t)T0 |
624 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
625 |
break;
|
626 |
case 2: |
627 |
stw_phys((target_phys_addr_t)(T0 & ~1)
|
628 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
629 |
break;
|
630 |
case 4: |
631 |
default:
|
632 |
stl_phys((target_phys_addr_t)(T0 & ~3)
|
633 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
634 |
break;
|
635 |
case 8: |
636 |
stq_phys((target_phys_addr_t)(T0 & ~7)
|
637 |
| ((target_phys_addr_t)(asi & 0xf) << 32), |
638 |
((uint64_t)T1 << 32) | T2);
|
639 |
break;
|
640 |
} |
641 |
} |
642 |
return;
|
643 |
case 0x31: /* Ross RT620 I-cache flush */ |
644 |
case 0x36: /* I-cache flash clear */ |
645 |
case 0x37: /* D-cache flash clear */ |
646 |
break;
|
647 |
case 9: /* Supervisor code access, XXX */ |
648 |
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
649 |
default:
|
650 |
do_unassigned_access(T0, 1, 0, 1); |
651 |
return;
|
652 |
} |
653 |
} |
654 |
|
655 |
#endif /* CONFIG_USER_ONLY */ |
656 |
#else /* TARGET_SPARC64 */ |
657 |
|
658 |
#ifdef CONFIG_USER_ONLY
|
659 |
void helper_ld_asi(int asi, int size, int sign) |
660 |
{ |
661 |
uint64_t ret = 0;
|
662 |
|
663 |
if (asi < 0x80) |
664 |
raise_exception(TT_PRIV_ACT); |
665 |
|
666 |
switch (asi) {
|
667 |
case 0x80: // Primary |
668 |
case 0x82: // Primary no-fault |
669 |
case 0x88: // Primary LE |
670 |
case 0x8a: // Primary no-fault LE |
671 |
{ |
672 |
switch(size) {
|
673 |
case 1: |
674 |
ret = ldub_raw(T0); |
675 |
break;
|
676 |
case 2: |
677 |
ret = lduw_raw(T0 & ~1);
|
678 |
break;
|
679 |
case 4: |
680 |
ret = ldl_raw(T0 & ~3);
|
681 |
break;
|
682 |
default:
|
683 |
case 8: |
684 |
ret = ldq_raw(T0 & ~7);
|
685 |
break;
|
686 |
} |
687 |
} |
688 |
break;
|
689 |
case 0x81: // Secondary |
690 |
case 0x83: // Secondary no-fault |
691 |
case 0x89: // Secondary LE |
692 |
case 0x8b: // Secondary no-fault LE |
693 |
// XXX
|
694 |
break;
|
695 |
default:
|
696 |
break;
|
697 |
} |
698 |
|
699 |
/* Convert from little endian */
|
700 |
switch (asi) {
|
701 |
case 0x88: // Primary LE |
702 |
case 0x89: // Secondary LE |
703 |
case 0x8a: // Primary no-fault LE |
704 |
case 0x8b: // Secondary no-fault LE |
705 |
switch(size) {
|
706 |
case 2: |
707 |
ret = bswap16(ret); |
708 |
break;
|
709 |
case 4: |
710 |
ret = bswap32(ret); |
711 |
break;
|
712 |
case 8: |
713 |
ret = bswap64(ret); |
714 |
break;
|
715 |
default:
|
716 |
break;
|
717 |
} |
718 |
default:
|
719 |
break;
|
720 |
} |
721 |
|
722 |
/* Convert to signed number */
|
723 |
if (sign) {
|
724 |
switch(size) {
|
725 |
case 1: |
726 |
ret = (int8_t) ret; |
727 |
break;
|
728 |
case 2: |
729 |
ret = (int16_t) ret; |
730 |
break;
|
731 |
case 4: |
732 |
ret = (int32_t) ret; |
733 |
break;
|
734 |
default:
|
735 |
break;
|
736 |
} |
737 |
} |
738 |
T1 = ret; |
739 |
} |
740 |
|
741 |
void helper_st_asi(int asi, int size) |
742 |
{ |
743 |
if (asi < 0x80) |
744 |
raise_exception(TT_PRIV_ACT); |
745 |
|
746 |
/* Convert to little endian */
|
747 |
switch (asi) {
|
748 |
case 0x88: // Primary LE |
749 |
case 0x89: // Secondary LE |
750 |
switch(size) {
|
751 |
case 2: |
752 |
T0 = bswap16(T0); |
753 |
break;
|
754 |
case 4: |
755 |
T0 = bswap32(T0); |
756 |
break;
|
757 |
case 8: |
758 |
T0 = bswap64(T0); |
759 |
break;
|
760 |
default:
|
761 |
break;
|
762 |
} |
763 |
default:
|
764 |
break;
|
765 |
} |
766 |
|
767 |
switch(asi) {
|
768 |
case 0x80: // Primary |
769 |
case 0x88: // Primary LE |
770 |
{ |
771 |
switch(size) {
|
772 |
case 1: |
773 |
stb_raw(T0, T1); |
774 |
break;
|
775 |
case 2: |
776 |
stw_raw(T0 & ~1, T1);
|
777 |
break;
|
778 |
case 4: |
779 |
stl_raw(T0 & ~3, T1);
|
780 |
break;
|
781 |
case 8: |
782 |
default:
|
783 |
stq_raw(T0 & ~7, T1);
|
784 |
break;
|
785 |
} |
786 |
} |
787 |
break;
|
788 |
case 0x81: // Secondary |
789 |
case 0x89: // Secondary LE |
790 |
// XXX
|
791 |
return;
|
792 |
|
793 |
case 0x82: // Primary no-fault, RO |
794 |
case 0x83: // Secondary no-fault, RO |
795 |
case 0x8a: // Primary no-fault LE, RO |
796 |
case 0x8b: // Secondary no-fault LE, RO |
797 |
default:
|
798 |
do_unassigned_access(T0, 1, 0, 1); |
799 |
return;
|
800 |
} |
801 |
} |
802 |
|
803 |
#else /* CONFIG_USER_ONLY */ |
804 |
|
805 |
void helper_ld_asi(int asi, int size, int sign) |
806 |
{ |
807 |
uint64_t ret = 0;
|
808 |
|
809 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
810 |
|| (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) |
811 |
raise_exception(TT_PRIV_ACT); |
812 |
|
813 |
switch (asi) {
|
814 |
case 0x10: // As if user primary |
815 |
case 0x18: // As if user primary LE |
816 |
case 0x80: // Primary |
817 |
case 0x82: // Primary no-fault |
818 |
case 0x88: // Primary LE |
819 |
case 0x8a: // Primary no-fault LE |
820 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
821 |
if (env->hpstate & HS_PRIV) {
|
822 |
switch(size) {
|
823 |
case 1: |
824 |
ret = ldub_hypv(T0); |
825 |
break;
|
826 |
case 2: |
827 |
ret = lduw_hypv(T0 & ~1);
|
828 |
break;
|
829 |
case 4: |
830 |
ret = ldl_hypv(T0 & ~3);
|
831 |
break;
|
832 |
default:
|
833 |
case 8: |
834 |
ret = ldq_hypv(T0 & ~7);
|
835 |
break;
|
836 |
} |
837 |
} else {
|
838 |
switch(size) {
|
839 |
case 1: |
840 |
ret = ldub_kernel(T0); |
841 |
break;
|
842 |
case 2: |
843 |
ret = lduw_kernel(T0 & ~1);
|
844 |
break;
|
845 |
case 4: |
846 |
ret = ldl_kernel(T0 & ~3);
|
847 |
break;
|
848 |
default:
|
849 |
case 8: |
850 |
ret = ldq_kernel(T0 & ~7);
|
851 |
break;
|
852 |
} |
853 |
} |
854 |
} else {
|
855 |
switch(size) {
|
856 |
case 1: |
857 |
ret = ldub_user(T0); |
858 |
break;
|
859 |
case 2: |
860 |
ret = lduw_user(T0 & ~1);
|
861 |
break;
|
862 |
case 4: |
863 |
ret = ldl_user(T0 & ~3);
|
864 |
break;
|
865 |
default:
|
866 |
case 8: |
867 |
ret = ldq_user(T0 & ~7);
|
868 |
break;
|
869 |
} |
870 |
} |
871 |
break;
|
872 |
case 0x14: // Bypass |
873 |
case 0x15: // Bypass, non-cacheable |
874 |
case 0x1c: // Bypass LE |
875 |
case 0x1d: // Bypass, non-cacheable LE |
876 |
{ |
877 |
switch(size) {
|
878 |
case 1: |
879 |
ret = ldub_phys(T0); |
880 |
break;
|
881 |
case 2: |
882 |
ret = lduw_phys(T0 & ~1);
|
883 |
break;
|
884 |
case 4: |
885 |
ret = ldl_phys(T0 & ~3);
|
886 |
break;
|
887 |
default:
|
888 |
case 8: |
889 |
ret = ldq_phys(T0 & ~7);
|
890 |
break;
|
891 |
} |
892 |
break;
|
893 |
} |
894 |
case 0x04: // Nucleus |
895 |
case 0x0c: // Nucleus Little Endian (LE) |
896 |
case 0x11: // As if user secondary |
897 |
case 0x19: // As if user secondary LE |
898 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
899 |
case 0x2c: // Nucleus quad LDD 128 bit atomic |
900 |
case 0x4a: // UPA config |
901 |
case 0x81: // Secondary |
902 |
case 0x83: // Secondary no-fault |
903 |
case 0x89: // Secondary LE |
904 |
case 0x8b: // Secondary no-fault LE |
905 |
// XXX
|
906 |
break;
|
907 |
case 0x45: // LSU |
908 |
ret = env->lsu; |
909 |
break;
|
910 |
case 0x50: // I-MMU regs |
911 |
{ |
912 |
int reg = (T0 >> 3) & 0xf; |
913 |
|
914 |
ret = env->immuregs[reg]; |
915 |
break;
|
916 |
} |
917 |
case 0x51: // I-MMU 8k TSB pointer |
918 |
case 0x52: // I-MMU 64k TSB pointer |
919 |
case 0x55: // I-MMU data access |
920 |
// XXX
|
921 |
break;
|
922 |
case 0x56: // I-MMU tag read |
923 |
{ |
924 |
unsigned int i; |
925 |
|
926 |
for (i = 0; i < 64; i++) { |
927 |
// Valid, ctx match, vaddr match
|
928 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && |
929 |
env->itlb_tag[i] == T0) { |
930 |
ret = env->itlb_tag[i]; |
931 |
break;
|
932 |
} |
933 |
} |
934 |
break;
|
935 |
} |
936 |
case 0x58: // D-MMU regs |
937 |
{ |
938 |
int reg = (T0 >> 3) & 0xf; |
939 |
|
940 |
ret = env->dmmuregs[reg]; |
941 |
break;
|
942 |
} |
943 |
case 0x5e: // D-MMU tag read |
944 |
{ |
945 |
unsigned int i; |
946 |
|
947 |
for (i = 0; i < 64; i++) { |
948 |
// Valid, ctx match, vaddr match
|
949 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && |
950 |
env->dtlb_tag[i] == T0) { |
951 |
ret = env->dtlb_tag[i]; |
952 |
break;
|
953 |
} |
954 |
} |
955 |
break;
|
956 |
} |
957 |
case 0x59: // D-MMU 8k TSB pointer |
958 |
case 0x5a: // D-MMU 64k TSB pointer |
959 |
case 0x5b: // D-MMU data pointer |
960 |
case 0x5d: // D-MMU data access |
961 |
case 0x48: // Interrupt dispatch, RO |
962 |
case 0x49: // Interrupt data receive |
963 |
case 0x7f: // Incoming interrupt vector, RO |
964 |
// XXX
|
965 |
break;
|
966 |
case 0x54: // I-MMU data in, WO |
967 |
case 0x57: // I-MMU demap, WO |
968 |
case 0x5c: // D-MMU data in, WO |
969 |
case 0x5f: // D-MMU demap, WO |
970 |
case 0x77: // Interrupt vector, WO |
971 |
default:
|
972 |
do_unassigned_access(T0, 0, 0, 1); |
973 |
ret = 0;
|
974 |
break;
|
975 |
} |
976 |
|
977 |
/* Convert from little endian */
|
978 |
switch (asi) {
|
979 |
case 0x0c: // Nucleus Little Endian (LE) |
980 |
case 0x18: // As if user primary LE |
981 |
case 0x19: // As if user secondary LE |
982 |
case 0x1c: // Bypass LE |
983 |
case 0x1d: // Bypass, non-cacheable LE |
984 |
case 0x88: // Primary LE |
985 |
case 0x89: // Secondary LE |
986 |
case 0x8a: // Primary no-fault LE |
987 |
case 0x8b: // Secondary no-fault LE |
988 |
switch(size) {
|
989 |
case 2: |
990 |
ret = bswap16(ret); |
991 |
break;
|
992 |
case 4: |
993 |
ret = bswap32(ret); |
994 |
break;
|
995 |
case 8: |
996 |
ret = bswap64(ret); |
997 |
break;
|
998 |
default:
|
999 |
break;
|
1000 |
} |
1001 |
default:
|
1002 |
break;
|
1003 |
} |
1004 |
|
1005 |
/* Convert to signed number */
|
1006 |
if (sign) {
|
1007 |
switch(size) {
|
1008 |
case 1: |
1009 |
ret = (int8_t) ret; |
1010 |
break;
|
1011 |
case 2: |
1012 |
ret = (int16_t) ret; |
1013 |
break;
|
1014 |
case 4: |
1015 |
ret = (int32_t) ret; |
1016 |
break;
|
1017 |
default:
|
1018 |
break;
|
1019 |
} |
1020 |
} |
1021 |
T1 = ret; |
1022 |
} |
1023 |
|
1024 |
void helper_st_asi(int asi, int size) |
1025 |
{ |
1026 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
1027 |
|| (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) |
1028 |
raise_exception(TT_PRIV_ACT); |
1029 |
|
1030 |
/* Convert to little endian */
|
1031 |
switch (asi) {
|
1032 |
case 0x0c: // Nucleus Little Endian (LE) |
1033 |
case 0x18: // As if user primary LE |
1034 |
case 0x19: // As if user secondary LE |
1035 |
case 0x1c: // Bypass LE |
1036 |
case 0x1d: // Bypass, non-cacheable LE |
1037 |
case 0x88: // Primary LE |
1038 |
case 0x89: // Secondary LE |
1039 |
switch(size) {
|
1040 |
case 2: |
1041 |
T0 = bswap16(T0); |
1042 |
break;
|
1043 |
case 4: |
1044 |
T0 = bswap32(T0); |
1045 |
break;
|
1046 |
case 8: |
1047 |
T0 = bswap64(T0); |
1048 |
break;
|
1049 |
default:
|
1050 |
break;
|
1051 |
} |
1052 |
default:
|
1053 |
break;
|
1054 |
} |
1055 |
|
1056 |
switch(asi) {
|
1057 |
case 0x10: // As if user primary |
1058 |
case 0x18: // As if user primary LE |
1059 |
case 0x80: // Primary |
1060 |
case 0x88: // Primary LE |
1061 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
1062 |
if (env->hpstate & HS_PRIV) {
|
1063 |
switch(size) {
|
1064 |
case 1: |
1065 |
stb_hypv(T0, T1); |
1066 |
break;
|
1067 |
case 2: |
1068 |
stw_hypv(T0 & ~1, T1);
|
1069 |
break;
|
1070 |
case 4: |
1071 |
stl_hypv(T0 & ~3, T1);
|
1072 |
break;
|
1073 |
case 8: |
1074 |
default:
|
1075 |
stq_hypv(T0 & ~7, T1);
|
1076 |
break;
|
1077 |
} |
1078 |
} else {
|
1079 |
switch(size) {
|
1080 |
case 1: |
1081 |
stb_kernel(T0, T1); |
1082 |
break;
|
1083 |
case 2: |
1084 |
stw_kernel(T0 & ~1, T1);
|
1085 |
break;
|
1086 |
case 4: |
1087 |
stl_kernel(T0 & ~3, T1);
|
1088 |
break;
|
1089 |
case 8: |
1090 |
default:
|
1091 |
stq_kernel(T0 & ~7, T1);
|
1092 |
break;
|
1093 |
} |
1094 |
} |
1095 |
} else {
|
1096 |
switch(size) {
|
1097 |
case 1: |
1098 |
stb_user(T0, T1); |
1099 |
break;
|
1100 |
case 2: |
1101 |
stw_user(T0 & ~1, T1);
|
1102 |
break;
|
1103 |
case 4: |
1104 |
stl_user(T0 & ~3, T1);
|
1105 |
break;
|
1106 |
case 8: |
1107 |
default:
|
1108 |
stq_user(T0 & ~7, T1);
|
1109 |
break;
|
1110 |
} |
1111 |
} |
1112 |
break;
|
1113 |
case 0x14: // Bypass |
1114 |
case 0x15: // Bypass, non-cacheable |
1115 |
case 0x1c: // Bypass LE |
1116 |
case 0x1d: // Bypass, non-cacheable LE |
1117 |
{ |
1118 |
switch(size) {
|
1119 |
case 1: |
1120 |
stb_phys(T0, T1); |
1121 |
break;
|
1122 |
case 2: |
1123 |
stw_phys(T0 & ~1, T1);
|
1124 |
break;
|
1125 |
case 4: |
1126 |
stl_phys(T0 & ~3, T1);
|
1127 |
break;
|
1128 |
case 8: |
1129 |
default:
|
1130 |
stq_phys(T0 & ~7, T1);
|
1131 |
break;
|
1132 |
} |
1133 |
} |
1134 |
return;
|
1135 |
case 0x04: // Nucleus |
1136 |
case 0x0c: // Nucleus Little Endian (LE) |
1137 |
case 0x11: // As if user secondary |
1138 |
case 0x19: // As if user secondary LE |
1139 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
1140 |
case 0x2c: // Nucleus quad LDD 128 bit atomic |
1141 |
case 0x4a: // UPA config |
1142 |
case 0x81: // Secondary |
1143 |
case 0x89: // Secondary LE |
1144 |
// XXX
|
1145 |
return;
|
1146 |
case 0x45: // LSU |
1147 |
{ |
1148 |
uint64_t oldreg; |
1149 |
|
1150 |
oldreg = env->lsu; |
1151 |
env->lsu = T1 & (DMMU_E | IMMU_E); |
1152 |
// Mappings generated during D/I MMU disabled mode are
|
1153 |
// invalid in normal mode
|
1154 |
if (oldreg != env->lsu) {
|
1155 |
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); |
1156 |
#ifdef DEBUG_MMU
|
1157 |
dump_mmu(env); |
1158 |
#endif
|
1159 |
tlb_flush(env, 1);
|
1160 |
} |
1161 |
return;
|
1162 |
} |
1163 |
case 0x50: // I-MMU regs |
1164 |
{ |
1165 |
int reg = (T0 >> 3) & 0xf; |
1166 |
uint64_t oldreg; |
1167 |
|
1168 |
oldreg = env->immuregs[reg]; |
1169 |
switch(reg) {
|
1170 |
case 0: // RO |
1171 |
case 4: |
1172 |
return;
|
1173 |
case 1: // Not in I-MMU |
1174 |
case 2: |
1175 |
case 7: |
1176 |
case 8: |
1177 |
return;
|
1178 |
case 3: // SFSR |
1179 |
if ((T1 & 1) == 0) |
1180 |
T1 = 0; // Clear SFSR |
1181 |
break;
|
1182 |
case 5: // TSB access |
1183 |
case 6: // Tag access |
1184 |
default:
|
1185 |
break;
|
1186 |
} |
1187 |
env->immuregs[reg] = T1; |
1188 |
if (oldreg != env->immuregs[reg]) {
|
1189 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
1190 |
} |
1191 |
#ifdef DEBUG_MMU
|
1192 |
dump_mmu(env); |
1193 |
#endif
|
1194 |
return;
|
1195 |
} |
1196 |
case 0x54: // I-MMU data in |
1197 |
{ |
1198 |
unsigned int i; |
1199 |
|
1200 |
// Try finding an invalid entry
|
1201 |
for (i = 0; i < 64; i++) { |
1202 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { |
1203 |
env->itlb_tag[i] = env->immuregs[6];
|
1204 |
env->itlb_tte[i] = T1; |
1205 |
return;
|
1206 |
} |
1207 |
} |
1208 |
// Try finding an unlocked entry
|
1209 |
for (i = 0; i < 64; i++) { |
1210 |
if ((env->itlb_tte[i] & 0x40) == 0) { |
1211 |
env->itlb_tag[i] = env->immuregs[6];
|
1212 |
env->itlb_tte[i] = T1; |
1213 |
return;
|
1214 |
} |
1215 |
} |
1216 |
// error state?
|
1217 |
return;
|
1218 |
} |
1219 |
case 0x55: // I-MMU data access |
1220 |
{ |
1221 |
unsigned int i = (T0 >> 3) & 0x3f; |
1222 |
|
1223 |
env->itlb_tag[i] = env->immuregs[6];
|
1224 |
env->itlb_tte[i] = T1; |
1225 |
return;
|
1226 |
} |
1227 |
case 0x57: // I-MMU demap |
1228 |
// XXX
|
1229 |
return;
|
1230 |
case 0x58: // D-MMU regs |
1231 |
{ |
1232 |
int reg = (T0 >> 3) & 0xf; |
1233 |
uint64_t oldreg; |
1234 |
|
1235 |
oldreg = env->dmmuregs[reg]; |
1236 |
switch(reg) {
|
1237 |
case 0: // RO |
1238 |
case 4: |
1239 |
return;
|
1240 |
case 3: // SFSR |
1241 |
if ((T1 & 1) == 0) { |
1242 |
T1 = 0; // Clear SFSR, Fault address |
1243 |
env->dmmuregs[4] = 0; |
1244 |
} |
1245 |
env->dmmuregs[reg] = T1; |
1246 |
break;
|
1247 |
case 1: // Primary context |
1248 |
case 2: // Secondary context |
1249 |
case 5: // TSB access |
1250 |
case 6: // Tag access |
1251 |
case 7: // Virtual Watchpoint |
1252 |
case 8: // Physical Watchpoint |
1253 |
default:
|
1254 |
break;
|
1255 |
} |
1256 |
env->dmmuregs[reg] = T1; |
1257 |
if (oldreg != env->dmmuregs[reg]) {
|
1258 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
1259 |
} |
1260 |
#ifdef DEBUG_MMU
|
1261 |
dump_mmu(env); |
1262 |
#endif
|
1263 |
return;
|
1264 |
} |
1265 |
case 0x5c: // D-MMU data in |
1266 |
{ |
1267 |
unsigned int i; |
1268 |
|
1269 |
// Try finding an invalid entry
|
1270 |
for (i = 0; i < 64; i++) { |
1271 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { |
1272 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1273 |
env->dtlb_tte[i] = T1; |
1274 |
return;
|
1275 |
} |
1276 |
} |
1277 |
// Try finding an unlocked entry
|
1278 |
for (i = 0; i < 64; i++) { |
1279 |
if ((env->dtlb_tte[i] & 0x40) == 0) { |
1280 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1281 |
env->dtlb_tte[i] = T1; |
1282 |
return;
|
1283 |
} |
1284 |
} |
1285 |
// error state?
|
1286 |
return;
|
1287 |
} |
1288 |
case 0x5d: // D-MMU data access |
1289 |
{ |
1290 |
unsigned int i = (T0 >> 3) & 0x3f; |
1291 |
|
1292 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1293 |
env->dtlb_tte[i] = T1; |
1294 |
return;
|
1295 |
} |
1296 |
case 0x5f: // D-MMU demap |
1297 |
case 0x49: // Interrupt data receive |
1298 |
// XXX
|
1299 |
return;
|
1300 |
case 0x51: // I-MMU 8k TSB pointer, RO |
1301 |
case 0x52: // I-MMU 64k TSB pointer, RO |
1302 |
case 0x56: // I-MMU tag read, RO |
1303 |
case 0x59: // D-MMU 8k TSB pointer, RO |
1304 |
case 0x5a: // D-MMU 64k TSB pointer, RO |
1305 |
case 0x5b: // D-MMU data pointer, RO |
1306 |
case 0x5e: // D-MMU tag read, RO |
1307 |
case 0x48: // Interrupt dispatch, RO |
1308 |
case 0x7f: // Incoming interrupt vector, RO |
1309 |
case 0x82: // Primary no-fault, RO |
1310 |
case 0x83: // Secondary no-fault, RO |
1311 |
case 0x8a: // Primary no-fault LE, RO |
1312 |
case 0x8b: // Secondary no-fault LE, RO |
1313 |
default:
|
1314 |
do_unassigned_access(T0, 1, 0, 1); |
1315 |
return;
|
1316 |
} |
1317 |
} |
1318 |
#endif /* CONFIG_USER_ONLY */ |
1319 |
|
1320 |
void helper_ldf_asi(int asi, int size, int rd) |
1321 |
{ |
1322 |
target_ulong tmp_T0 = T0, tmp_T1 = T1; |
1323 |
unsigned int i; |
1324 |
|
1325 |
switch (asi) {
|
1326 |
case 0xf0: // Block load primary |
1327 |
case 0xf1: // Block load secondary |
1328 |
case 0xf8: // Block load primary LE |
1329 |
case 0xf9: // Block load secondary LE |
1330 |
if (rd & 7) { |
1331 |
raise_exception(TT_ILL_INSN); |
1332 |
return;
|
1333 |
} |
1334 |
if (T0 & 0x3f) { |
1335 |
raise_exception(TT_UNALIGNED); |
1336 |
return;
|
1337 |
} |
1338 |
for (i = 0; i < 16; i++) { |
1339 |
helper_ld_asi(asi & 0x8f, 4, 0); |
1340 |
*(uint32_t *)&env->fpr[rd++] = T1; |
1341 |
T0 += 4;
|
1342 |
} |
1343 |
T0 = tmp_T0; |
1344 |
T1 = tmp_T1; |
1345 |
|
1346 |
return;
|
1347 |
default:
|
1348 |
break;
|
1349 |
} |
1350 |
|
1351 |
helper_ld_asi(asi, size, 0);
|
1352 |
switch(size) {
|
1353 |
default:
|
1354 |
case 4: |
1355 |
*((uint32_t *)&FT0) = T1; |
1356 |
break;
|
1357 |
case 8: |
1358 |
*((int64_t *)&DT0) = T1; |
1359 |
break;
|
1360 |
} |
1361 |
T1 = tmp_T1; |
1362 |
} |
1363 |
|
1364 |
void helper_stf_asi(int asi, int size, int rd) |
1365 |
{ |
1366 |
target_ulong tmp_T0 = T0, tmp_T1 = T1; |
1367 |
unsigned int i; |
1368 |
|
1369 |
switch (asi) {
|
1370 |
case 0xf0: // Block store primary |
1371 |
case 0xf1: // Block store secondary |
1372 |
case 0xf8: // Block store primary LE |
1373 |
case 0xf9: // Block store secondary LE |
1374 |
if (rd & 7) { |
1375 |
raise_exception(TT_ILL_INSN); |
1376 |
return;
|
1377 |
} |
1378 |
if (T0 & 0x3f) { |
1379 |
raise_exception(TT_UNALIGNED); |
1380 |
return;
|
1381 |
} |
1382 |
for (i = 0; i < 16; i++) { |
1383 |
T1 = *(uint32_t *)&env->fpr[rd++]; |
1384 |
helper_st_asi(asi & 0x8f, 4); |
1385 |
T0 += 4;
|
1386 |
} |
1387 |
T0 = tmp_T0; |
1388 |
T1 = tmp_T1; |
1389 |
|
1390 |
return;
|
1391 |
default:
|
1392 |
break;
|
1393 |
} |
1394 |
|
1395 |
switch(size) {
|
1396 |
default:
|
1397 |
case 4: |
1398 |
T1 = *((uint32_t *)&FT0); |
1399 |
break;
|
1400 |
case 8: |
1401 |
T1 = *((int64_t *)&DT0); |
1402 |
break;
|
1403 |
} |
1404 |
helper_st_asi(asi, size); |
1405 |
T1 = tmp_T1; |
1406 |
} |
1407 |
|
1408 |
#endif /* TARGET_SPARC64 */ |
1409 |
|
1410 |
#ifndef TARGET_SPARC64
|
1411 |
void helper_rett()
|
1412 |
{ |
1413 |
unsigned int cwp; |
1414 |
|
1415 |
if (env->psret == 1) |
1416 |
raise_exception(TT_ILL_INSN); |
1417 |
|
1418 |
env->psret = 1;
|
1419 |
cwp = (env->cwp + 1) & (NWINDOWS - 1); |
1420 |
if (env->wim & (1 << cwp)) { |
1421 |
raise_exception(TT_WIN_UNF); |
1422 |
} |
1423 |
set_cwp(cwp); |
1424 |
env->psrs = env->psrps; |
1425 |
} |
1426 |
#endif
|
1427 |
|
1428 |
void helper_ldfsr(void) |
1429 |
{ |
1430 |
int rnd_mode;
|
1431 |
switch (env->fsr & FSR_RD_MASK) {
|
1432 |
case FSR_RD_NEAREST:
|
1433 |
rnd_mode = float_round_nearest_even; |
1434 |
break;
|
1435 |
default:
|
1436 |
case FSR_RD_ZERO:
|
1437 |
rnd_mode = float_round_to_zero; |
1438 |
break;
|
1439 |
case FSR_RD_POS:
|
1440 |
rnd_mode = float_round_up; |
1441 |
break;
|
1442 |
case FSR_RD_NEG:
|
1443 |
rnd_mode = float_round_down; |
1444 |
break;
|
1445 |
} |
1446 |
set_float_rounding_mode(rnd_mode, &env->fp_status); |
1447 |
} |
1448 |
|
1449 |
void helper_debug()
|
1450 |
{ |
1451 |
env->exception_index = EXCP_DEBUG; |
1452 |
cpu_loop_exit(); |
1453 |
} |
1454 |
|
1455 |
#ifndef TARGET_SPARC64
|
1456 |
void do_wrpsr()
|
1457 |
{ |
1458 |
if ((T0 & PSR_CWP) >= NWINDOWS)
|
1459 |
raise_exception(TT_ILL_INSN); |
1460 |
else
|
1461 |
PUT_PSR(env, T0); |
1462 |
} |
1463 |
|
1464 |
void do_rdpsr()
|
1465 |
{ |
1466 |
T0 = GET_PSR(env); |
1467 |
} |
1468 |
|
1469 |
#else
|
1470 |
|
1471 |
void do_popc()
|
1472 |
{ |
1473 |
T0 = ctpop64(T1); |
1474 |
} |
1475 |
|
1476 |
static inline uint64_t *get_gregset(uint64_t pstate) |
1477 |
{ |
1478 |
switch (pstate) {
|
1479 |
default:
|
1480 |
case 0: |
1481 |
return env->bgregs;
|
1482 |
case PS_AG:
|
1483 |
return env->agregs;
|
1484 |
case PS_MG:
|
1485 |
return env->mgregs;
|
1486 |
case PS_IG:
|
1487 |
return env->igregs;
|
1488 |
} |
1489 |
} |
1490 |
|
1491 |
static inline void change_pstate(uint64_t new_pstate) |
1492 |
{ |
1493 |
uint64_t pstate_regs, new_pstate_regs; |
1494 |
uint64_t *src, *dst; |
1495 |
|
1496 |
pstate_regs = env->pstate & 0xc01;
|
1497 |
new_pstate_regs = new_pstate & 0xc01;
|
1498 |
if (new_pstate_regs != pstate_regs) {
|
1499 |
// Switch global register bank
|
1500 |
src = get_gregset(new_pstate_regs); |
1501 |
dst = get_gregset(pstate_regs); |
1502 |
memcpy32(dst, env->gregs); |
1503 |
memcpy32(env->gregs, src); |
1504 |
} |
1505 |
env->pstate = new_pstate; |
1506 |
} |
1507 |
|
1508 |
void do_wrpstate(void) |
1509 |
{ |
1510 |
change_pstate(T0 & 0xf3f);
|
1511 |
} |
1512 |
|
1513 |
void do_done(void) |
1514 |
{ |
1515 |
env->tl--; |
1516 |
env->pc = env->tnpc[env->tl]; |
1517 |
env->npc = env->tnpc[env->tl] + 4;
|
1518 |
PUT_CCR(env, env->tstate[env->tl] >> 32);
|
1519 |
env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
1520 |
change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
1521 |
PUT_CWP64(env, env->tstate[env->tl] & 0xff);
|
1522 |
} |
1523 |
|
1524 |
void do_retry(void) |
1525 |
{ |
1526 |
env->tl--; |
1527 |
env->pc = env->tpc[env->tl]; |
1528 |
env->npc = env->tnpc[env->tl]; |
1529 |
PUT_CCR(env, env->tstate[env->tl] >> 32);
|
1530 |
env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
1531 |
change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
1532 |
PUT_CWP64(env, env->tstate[env->tl] & 0xff);
|
1533 |
} |
1534 |
#endif
|
1535 |
|
1536 |
void set_cwp(int new_cwp) |
1537 |
{ |
1538 |
/* put the modified wrap registers at their proper location */
|
1539 |
if (env->cwp == (NWINDOWS - 1)) |
1540 |
memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
1541 |
env->cwp = new_cwp; |
1542 |
/* put the wrap registers at their temporary location */
|
1543 |
if (new_cwp == (NWINDOWS - 1)) |
1544 |
memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
1545 |
env->regwptr = env->regbase + (new_cwp * 16);
|
1546 |
REGWPTR = env->regwptr; |
1547 |
} |
1548 |
|
1549 |
void cpu_set_cwp(CPUState *env1, int new_cwp) |
1550 |
{ |
1551 |
CPUState *saved_env; |
1552 |
#ifdef reg_REGWPTR
|
1553 |
target_ulong *saved_regwptr; |
1554 |
#endif
|
1555 |
|
1556 |
saved_env = env; |
1557 |
#ifdef reg_REGWPTR
|
1558 |
saved_regwptr = REGWPTR; |
1559 |
#endif
|
1560 |
env = env1; |
1561 |
set_cwp(new_cwp); |
1562 |
env = saved_env; |
1563 |
#ifdef reg_REGWPTR
|
1564 |
REGWPTR = saved_regwptr; |
1565 |
#endif
|
1566 |
} |
1567 |
|
1568 |
#ifdef TARGET_SPARC64
|
1569 |
void do_interrupt(int intno) |
1570 |
{ |
1571 |
#ifdef DEBUG_PCALL
|
1572 |
if (loglevel & CPU_LOG_INT) {
|
1573 |
static int count; |
1574 |
fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n", |
1575 |
count, intno, |
1576 |
env->pc, |
1577 |
env->npc, env->regwptr[6]);
|
1578 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1579 |
#if 0
|
1580 |
{
|
1581 |
int i;
|
1582 |
uint8_t *ptr;
|
1583 |
|
1584 |
fprintf(logfile, " code=");
|
1585 |
ptr = (uint8_t *)env->pc;
|
1586 |
for(i = 0; i < 16; i++) {
|
1587 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
1588 |
}
|
1589 |
fprintf(logfile, "\n");
|
1590 |
}
|
1591 |
#endif
|
1592 |
count++; |
1593 |
} |
1594 |
#endif
|
1595 |
#if !defined(CONFIG_USER_ONLY)
|
1596 |
if (env->tl == MAXTL) {
|
1597 |
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
1598 |
return;
|
1599 |
} |
1600 |
#endif
|
1601 |
env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | |
1602 |
((env->pstate & 0xf3f) << 8) | GET_CWP64(env); |
1603 |
env->tpc[env->tl] = env->pc; |
1604 |
env->tnpc[env->tl] = env->npc; |
1605 |
env->tt[env->tl] = intno; |
1606 |
change_pstate(PS_PEF | PS_PRIV | PS_AG); |
1607 |
|
1608 |
if (intno == TT_CLRWIN)
|
1609 |
set_cwp((env->cwp - 1) & (NWINDOWS - 1)); |
1610 |
else if ((intno & 0x1c0) == TT_SPILL) |
1611 |
set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1)); |
1612 |
else if ((intno & 0x1c0) == TT_FILL) |
1613 |
set_cwp((env->cwp + 1) & (NWINDOWS - 1)); |
1614 |
env->tbr &= ~0x7fffULL;
|
1615 |
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
1616 |
if (env->tl < MAXTL - 1) { |
1617 |
env->tl++; |
1618 |
} else {
|
1619 |
env->pstate |= PS_RED; |
1620 |
if (env->tl != MAXTL)
|
1621 |
env->tl++; |
1622 |
} |
1623 |
env->pc = env->tbr; |
1624 |
env->npc = env->pc + 4;
|
1625 |
env->exception_index = 0;
|
1626 |
} |
1627 |
#else
|
1628 |
void do_interrupt(int intno) |
1629 |
{ |
1630 |
int cwp;
|
1631 |
|
1632 |
#ifdef DEBUG_PCALL
|
1633 |
if (loglevel & CPU_LOG_INT) {
|
1634 |
static int count; |
1635 |
fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
|
1636 |
count, intno, |
1637 |
env->pc, |
1638 |
env->npc, env->regwptr[6]);
|
1639 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1640 |
#if 0
|
1641 |
{
|
1642 |
int i;
|
1643 |
uint8_t *ptr;
|
1644 |
|
1645 |
fprintf(logfile, " code=");
|
1646 |
ptr = (uint8_t *)env->pc;
|
1647 |
for(i = 0; i < 16; i++) {
|
1648 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
1649 |
}
|
1650 |
fprintf(logfile, "\n");
|
1651 |
}
|
1652 |
#endif
|
1653 |
count++; |
1654 |
} |
1655 |
#endif
|
1656 |
#if !defined(CONFIG_USER_ONLY)
|
1657 |
if (env->psret == 0) { |
1658 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
1659 |
return;
|
1660 |
} |
1661 |
#endif
|
1662 |
env->psret = 0;
|
1663 |
cwp = (env->cwp - 1) & (NWINDOWS - 1); |
1664 |
set_cwp(cwp); |
1665 |
env->regwptr[9] = env->pc;
|
1666 |
env->regwptr[10] = env->npc;
|
1667 |
env->psrps = env->psrs; |
1668 |
env->psrs = 1;
|
1669 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
1670 |
env->pc = env->tbr; |
1671 |
env->npc = env->pc + 4;
|
1672 |
env->exception_index = 0;
|
1673 |
} |
1674 |
#endif
|
1675 |
|
1676 |
#if !defined(CONFIG_USER_ONLY)
|
1677 |
|
1678 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1679 |
void *retaddr);
|
1680 |
|
1681 |
#define MMUSUFFIX _mmu
|
1682 |
#define ALIGNED_ONLY
|
1683 |
#ifdef __s390__
|
1684 |
# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) |
1685 |
#else
|
1686 |
# define GETPC() (__builtin_return_address(0)) |
1687 |
#endif
|
1688 |
|
1689 |
#define SHIFT 0 |
1690 |
#include "softmmu_template.h" |
1691 |
|
1692 |
#define SHIFT 1 |
1693 |
#include "softmmu_template.h" |
1694 |
|
1695 |
#define SHIFT 2 |
1696 |
#include "softmmu_template.h" |
1697 |
|
1698 |
#define SHIFT 3 |
1699 |
#include "softmmu_template.h" |
1700 |
|
1701 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1702 |
void *retaddr)
|
1703 |
{ |
1704 |
#ifdef DEBUG_UNALIGNED
|
1705 |
printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
|
1706 |
#endif
|
1707 |
raise_exception(TT_UNALIGNED); |
1708 |
} |
1709 |
|
1710 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
1711 |
NULL, it means that the function was called in C code (i.e. not
|
1712 |
from generated code or from helper.c) */
|
1713 |
/* XXX: fix it to restore all registers */
|
1714 |
void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
1715 |
{ |
1716 |
TranslationBlock *tb; |
1717 |
int ret;
|
1718 |
unsigned long pc; |
1719 |
CPUState *saved_env; |
1720 |
|
1721 |
/* XXX: hack to restore env in all cases, even if not called from
|
1722 |
generated code */
|
1723 |
saved_env = env; |
1724 |
env = cpu_single_env; |
1725 |
|
1726 |
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
1727 |
if (ret) {
|
1728 |
if (retaddr) {
|
1729 |
/* now we have a real cpu fault */
|
1730 |
pc = (unsigned long)retaddr; |
1731 |
tb = tb_find_pc(pc); |
1732 |
if (tb) {
|
1733 |
/* the PC is inside the translated code. It means that we have
|
1734 |
a virtual CPU fault */
|
1735 |
cpu_restore_state(tb, env, pc, (void *)T2);
|
1736 |
} |
1737 |
} |
1738 |
cpu_loop_exit(); |
1739 |
} |
1740 |
env = saved_env; |
1741 |
} |
1742 |
|
1743 |
#endif
|
1744 |
|
1745 |
#ifndef TARGET_SPARC64
|
1746 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
1747 |
int is_asi)
|
1748 |
{ |
1749 |
CPUState *saved_env; |
1750 |
|
1751 |
/* XXX: hack to restore env in all cases, even if not called from
|
1752 |
generated code */
|
1753 |
saved_env = env; |
1754 |
env = cpu_single_env; |
1755 |
if (env->mmuregs[3]) /* Fault status register */ |
1756 |
env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
1757 |
if (is_asi)
|
1758 |
env->mmuregs[3] |= 1 << 16; |
1759 |
if (env->psrs)
|
1760 |
env->mmuregs[3] |= 1 << 5; |
1761 |
if (is_exec)
|
1762 |
env->mmuregs[3] |= 1 << 6; |
1763 |
if (is_write)
|
1764 |
env->mmuregs[3] |= 1 << 7; |
1765 |
env->mmuregs[3] |= (5 << 2) | 2; |
1766 |
env->mmuregs[4] = addr; /* Fault address register */ |
1767 |
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
1768 |
#ifdef DEBUG_UNASSIGNED
|
1769 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
1770 |
"\n", addr, env->pc);
|
1771 |
#endif
|
1772 |
if (is_exec)
|
1773 |
raise_exception(TT_CODE_ACCESS); |
1774 |
else
|
1775 |
raise_exception(TT_DATA_ACCESS); |
1776 |
} |
1777 |
env = saved_env; |
1778 |
} |
1779 |
#else
|
1780 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
1781 |
int is_asi)
|
1782 |
{ |
1783 |
#ifdef DEBUG_UNASSIGNED
|
1784 |
CPUState *saved_env; |
1785 |
|
1786 |
/* XXX: hack to restore env in all cases, even if not called from
|
1787 |
generated code */
|
1788 |
saved_env = env; |
1789 |
env = cpu_single_env; |
1790 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", |
1791 |
addr, env->pc); |
1792 |
env = saved_env; |
1793 |
#endif
|
1794 |
if (is_exec)
|
1795 |
raise_exception(TT_CODE_ACCESS); |
1796 |
else
|
1797 |
raise_exception(TT_DATA_ACCESS); |
1798 |
} |
1799 |
#endif
|
1800 |
|
1801 |
#ifdef TARGET_SPARC64
|
1802 |
void do_tick_set_count(void *opaque, uint64_t count) |
1803 |
{ |
1804 |
#if !defined(CONFIG_USER_ONLY)
|
1805 |
ptimer_set_count(opaque, -count); |
1806 |
#endif
|
1807 |
} |
1808 |
|
1809 |
uint64_t do_tick_get_count(void *opaque)
|
1810 |
{ |
1811 |
#if !defined(CONFIG_USER_ONLY)
|
1812 |
return -ptimer_get_count(opaque);
|
1813 |
#else
|
1814 |
return 0; |
1815 |
#endif
|
1816 |
} |
1817 |
|
1818 |
void do_tick_set_limit(void *opaque, uint64_t limit) |
1819 |
{ |
1820 |
#if !defined(CONFIG_USER_ONLY)
|
1821 |
ptimer_set_limit(opaque, -limit, 0);
|
1822 |
#endif
|
1823 |
} |
1824 |
#endif
|