root / hw / hpet.c @ 27bb0b2d
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/*
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* High Precisition Event Timer emulation
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*
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* Copyright (c) 2007 Alexander Graf
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* Copyright (c) 2008 IBM Corporation
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*
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* Authors: Beth Kon <bkon@us.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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* *****************************************************************
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*
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* This driver attempts to emulate an HPET device in software.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "console.h" |
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#include "qemu-timer.h" |
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#include "hpet_emul.h" |
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//#define HPET_DEBUG
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#ifdef HPET_DEBUG
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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struct HPETState;
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typedef struct HPETTimer { /* timers */ |
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uint8_t tn; /*timer number*/
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QEMUTimer *qemu_timer; |
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struct HPETState *state;
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/* Memory-mapped, software visible timer registers */
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uint64_t config; /* configuration/cap */
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uint64_t cmp; /* comparator */
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uint64_t fsb; /* FSB route, not supported now */
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/* Hidden register state */
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uint64_t period; /* Last value written to comparator */
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uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
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* mode. Next pop will be actual timer expiration.
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*/
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} HPETTimer; |
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typedef struct HPETState { |
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uint64_t hpet_offset; |
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qemu_irq *irqs; |
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HPETTimer timer[HPET_NUM_TIMERS]; |
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/* Memory-mapped, software visible registers */
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uint64_t capability; /* capabilities */
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uint64_t config; /* configuration */
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uint64_t isr; /* interrupt status reg */
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uint64_t hpet_counter; /* main counter */
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} HPETState; |
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static HPETState *hpet_statep;
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uint32_t hpet_in_legacy_mode(void)
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{ |
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if (!hpet_statep) {
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return 0; |
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} |
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return hpet_statep->config & HPET_CFG_LEGACY;
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} |
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static uint32_t timer_int_route(struct HPETTimer *timer) |
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{ |
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return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
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} |
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static uint32_t hpet_enabled(void) |
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{ |
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return hpet_statep->config & HPET_CFG_ENABLE;
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} |
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static uint32_t timer_is_periodic(HPETTimer *t)
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{ |
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return t->config & HPET_TN_PERIODIC;
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} |
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static uint32_t timer_enabled(HPETTimer *t)
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{ |
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return t->config & HPET_TN_ENABLE;
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} |
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static uint32_t hpet_time_after(uint64_t a, uint64_t b)
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{ |
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return ((int32_t)(b) - (int32_t)(a) < 0); |
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} |
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static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
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{ |
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return ((int64_t)(b) - (int64_t)(a) < 0); |
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} |
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static uint64_t ticks_to_ns(uint64_t value)
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{ |
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return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
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} |
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static uint64_t ns_to_ticks(uint64_t value)
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{ |
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return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
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} |
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static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
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{ |
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new &= mask; |
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new |= old & ~mask; |
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return new;
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} |
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static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) |
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{ |
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return (!(old & mask) && (new & mask));
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} |
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static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) |
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{ |
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return ((old & mask) && !(new & mask));
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} |
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static uint64_t hpet_get_ticks(void) |
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{ |
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return ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
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} |
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/*
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* calculate diff between comparator value and current ticks
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*/
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static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) |
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{ |
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if (t->config & HPET_TN_32BIT) {
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uint32_t diff, cmp; |
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cmp = (uint32_t)t->cmp; |
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diff = cmp - (uint32_t)current; |
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diff = (int32_t)diff > 0 ? diff : (uint32_t)0; |
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return (uint64_t)diff;
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} else {
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uint64_t diff, cmp; |
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cmp = t->cmp; |
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diff = cmp - current; |
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diff = (int64_t)diff > 0 ? diff : (uint64_t)0; |
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return diff;
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} |
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} |
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static void update_irq(struct HPETTimer *timer) |
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{ |
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int route;
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if (timer->tn <= 1 && hpet_in_legacy_mode()) { |
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/* if LegacyReplacementRoute bit is set, HPET specification requires
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* timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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* timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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*/
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route = (timer->tn == 0) ? 0 : 8; |
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} else {
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route = timer_int_route(timer); |
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} |
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if (!timer_enabled(timer) || !hpet_enabled()) {
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return;
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} |
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qemu_irq_pulse(timer->state->irqs[route]); |
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} |
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static void hpet_pre_save(void *opaque) |
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{ |
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HPETState *s = opaque; |
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/* save current counter value */
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s->hpet_counter = hpet_get_ticks(); |
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} |
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static int hpet_post_load(void *opaque, int version_id) |
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{ |
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HPETState *s = opaque; |
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/* Recalculate the offset between the main counter and guest time */
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s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); |
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return 0; |
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} |
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static const VMStateDescription vmstate_hpet_timer = { |
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.name = "hpet_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_UINT8(tn, HPETTimer), |
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VMSTATE_UINT64(config, HPETTimer), |
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VMSTATE_UINT64(cmp, HPETTimer), |
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VMSTATE_UINT64(fsb, HPETTimer), |
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VMSTATE_UINT64(period, HPETTimer), |
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VMSTATE_UINT8(wrap_flag, HPETTimer), |
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VMSTATE_TIMER(qemu_timer, HPETTimer), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_hpet = { |
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.name = "hpet",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.pre_save = hpet_pre_save, |
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.post_load = hpet_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_UINT64(config, HPETState), |
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VMSTATE_UINT64(isr, HPETState), |
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VMSTATE_UINT64(hpet_counter, HPETState), |
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VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
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vmstate_hpet_timer, HPETTimer), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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/*
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* timer expiration callback
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*/
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static void hpet_timer(void *opaque) |
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{ |
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HPETTimer *t = opaque; |
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uint64_t diff; |
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uint64_t period = t->period; |
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uint64_t cur_tick = hpet_get_ticks(); |
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if (timer_is_periodic(t) && period != 0) { |
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if (t->config & HPET_TN_32BIT) {
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while (hpet_time_after(cur_tick, t->cmp)) {
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t->cmp = (uint32_t)(t->cmp + t->period); |
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} |
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} else {
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while (hpet_time_after64(cur_tick, t->cmp)) {
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t->cmp += period; |
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} |
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} |
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diff = hpet_calculate_diff(t, cur_tick); |
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qemu_mod_timer(t->qemu_timer, |
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qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); |
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} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
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if (t->wrap_flag) {
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diff = hpet_calculate_diff(t, cur_tick); |
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) + |
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(int64_t)ticks_to_ns(diff)); |
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t->wrap_flag = 0;
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} |
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} |
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update_irq(t); |
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} |
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static void hpet_set_timer(HPETTimer *t) |
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{ |
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uint64_t diff; |
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uint32_t wrap_diff; /* how many ticks until we wrap? */
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uint64_t cur_tick = hpet_get_ticks(); |
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/* whenever new timer is being set up, make sure wrap_flag is 0 */
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t->wrap_flag = 0;
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diff = hpet_calculate_diff(t, cur_tick); |
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/* hpet spec says in one-shot 32-bit mode, generate an interrupt when
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* counter wraps in addition to an interrupt with comparator match.
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*/
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if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
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wrap_diff = 0xffffffff - (uint32_t)cur_tick;
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if (wrap_diff < (uint32_t)diff) {
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diff = wrap_diff; |
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t->wrap_flag = 1;
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} |
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} |
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qemu_mod_timer(t->qemu_timer, |
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qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); |
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} |
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static void hpet_del_timer(HPETTimer *t) |
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{ |
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qemu_del_timer(t->qemu_timer); |
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} |
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#ifdef HPET_DEBUG
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static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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printf("qemu: hpet_read b at %" PRIx64 "\n", addr); |
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return 0; |
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} |
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static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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printf("qemu: hpet_read w at %" PRIx64 "\n", addr); |
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return 0; |
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} |
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#endif
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static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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HPETState *s = opaque; |
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uint64_t cur_tick, index; |
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DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
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index = addr; |
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/*address range of all TN regs*/
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if (index >= 0x100 && index <= 0x3ff) { |
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uint8_t timer_id = (addr - 0x100) / 0x20; |
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HPETTimer *timer = &s->timer[timer_id]; |
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if (timer_id > HPET_NUM_TIMERS - 1) { |
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DPRINTF("qemu: timer id out of range\n");
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return 0; |
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} |
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switch ((addr - 0x100) % 0x20) { |
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case HPET_TN_CFG:
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return timer->config;
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case HPET_TN_CFG + 4: // Interrupt capabilities |
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return timer->config >> 32; |
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case HPET_TN_CMP: // comparator register |
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return timer->cmp;
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case HPET_TN_CMP + 4: |
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return timer->cmp >> 32; |
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case HPET_TN_ROUTE:
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return timer->fsb >> 32; |
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default:
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break;
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} |
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} else {
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switch (index) {
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case HPET_ID:
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return s->capability;
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case HPET_PERIOD:
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return s->capability >> 32; |
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case HPET_CFG:
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return s->config;
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case HPET_CFG + 4: |
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DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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return 0; |
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case HPET_COUNTER:
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if (hpet_enabled()) {
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cur_tick = hpet_get_ticks(); |
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} else {
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cur_tick = s->hpet_counter; |
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} |
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DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); |
361 |
return cur_tick;
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case HPET_COUNTER + 4: |
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if (hpet_enabled()) {
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cur_tick = hpet_get_ticks(); |
365 |
} else {
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cur_tick = s->hpet_counter; |
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} |
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DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); |
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return cur_tick >> 32; |
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case HPET_STATUS:
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return s->isr;
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default:
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break;
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} |
376 |
} |
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return 0; |
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} |
379 |
|
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#ifdef HPET_DEBUG
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static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", |
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addr, value); |
386 |
} |
387 |
|
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static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
390 |
{ |
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printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", |
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addr, value); |
393 |
} |
394 |
#endif
|
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|
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static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
398 |
{ |
399 |
int i;
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HPETState *s = opaque; |
401 |
uint64_t old_val, new_val, val, index; |
402 |
|
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DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
404 |
index = addr; |
405 |
old_val = hpet_ram_readl(opaque, addr); |
406 |
new_val = value; |
407 |
|
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/*address range of all TN regs*/
|
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if (index >= 0x100 && index <= 0x3ff) { |
410 |
uint8_t timer_id = (addr - 0x100) / 0x20; |
411 |
HPETTimer *timer = &s->timer[timer_id]; |
412 |
|
413 |
DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
|
414 |
if (timer_id > HPET_NUM_TIMERS - 1) { |
415 |
DPRINTF("qemu: timer id out of range\n");
|
416 |
return;
|
417 |
} |
418 |
switch ((addr - 0x100) % 0x20) { |
419 |
case HPET_TN_CFG:
|
420 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
|
421 |
val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
422 |
timer->config = (timer->config & 0xffffffff00000000ULL) | val;
|
423 |
if (new_val & HPET_TN_32BIT) {
|
424 |
timer->cmp = (uint32_t)timer->cmp; |
425 |
timer->period = (uint32_t)timer->period; |
426 |
} |
427 |
if (new_val & HPET_TN_TYPE_LEVEL) {
|
428 |
printf("qemu: level-triggered hpet not supported\n");
|
429 |
exit (-1);
|
430 |
} |
431 |
break;
|
432 |
case HPET_TN_CFG + 4: // Interrupt capabilities |
433 |
DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
|
434 |
break;
|
435 |
case HPET_TN_CMP: // comparator register |
436 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
|
437 |
if (timer->config & HPET_TN_32BIT) {
|
438 |
new_val = (uint32_t)new_val; |
439 |
} |
440 |
if (!timer_is_periodic(timer)
|
441 |
|| (timer->config & HPET_TN_SETVAL)) { |
442 |
timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
|
443 |
} |
444 |
if (timer_is_periodic(timer)) {
|
445 |
/*
|
446 |
* FIXME: Clamp period to reasonable min value?
|
447 |
* Clamp period to reasonable max value
|
448 |
*/
|
449 |
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
450 |
timer->period = |
451 |
(timer->period & 0xffffffff00000000ULL) | new_val;
|
452 |
} |
453 |
timer->config &= ~HPET_TN_SETVAL; |
454 |
if (hpet_enabled()) {
|
455 |
hpet_set_timer(timer); |
456 |
} |
457 |
break;
|
458 |
case HPET_TN_CMP + 4: // comparator register high order |
459 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
|
460 |
if (!timer_is_periodic(timer)
|
461 |
|| (timer->config & HPET_TN_SETVAL)) { |
462 |
timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; |
463 |
} else {
|
464 |
/*
|
465 |
* FIXME: Clamp period to reasonable min value?
|
466 |
* Clamp period to reasonable max value
|
467 |
*/
|
468 |
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
469 |
timer->period = |
470 |
(timer->period & 0xffffffffULL) | new_val << 32; |
471 |
} |
472 |
timer->config &= ~HPET_TN_SETVAL; |
473 |
if (hpet_enabled()) {
|
474 |
hpet_set_timer(timer); |
475 |
} |
476 |
break;
|
477 |
case HPET_TN_ROUTE + 4: |
478 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
|
479 |
break;
|
480 |
default:
|
481 |
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
482 |
break;
|
483 |
} |
484 |
return;
|
485 |
} else {
|
486 |
switch (index) {
|
487 |
case HPET_ID:
|
488 |
return;
|
489 |
case HPET_CFG:
|
490 |
val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); |
491 |
s->config = (s->config & 0xffffffff00000000ULL) | val;
|
492 |
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
493 |
/* Enable main counter and interrupt generation. */
|
494 |
s->hpet_offset = |
495 |
ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); |
496 |
for (i = 0; i < HPET_NUM_TIMERS; i++) { |
497 |
if ((&s->timer[i])->cmp != ~0ULL) { |
498 |
hpet_set_timer(&s->timer[i]); |
499 |
} |
500 |
} |
501 |
} else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
502 |
/* Halt main counter and disable interrupt generation. */
|
503 |
s->hpet_counter = hpet_get_ticks(); |
504 |
for (i = 0; i < HPET_NUM_TIMERS; i++) { |
505 |
hpet_del_timer(&s->timer[i]); |
506 |
} |
507 |
} |
508 |
/* i8254 and RTC are disabled when HPET is in legacy mode */
|
509 |
if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
510 |
hpet_pit_disable(); |
511 |
} else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
512 |
hpet_pit_enable(); |
513 |
} |
514 |
break;
|
515 |
case HPET_CFG + 4: |
516 |
DPRINTF("qemu: invalid HPET_CFG+4 write \n");
|
517 |
break;
|
518 |
case HPET_STATUS:
|
519 |
/* FIXME: need to handle level-triggered interrupts */
|
520 |
break;
|
521 |
case HPET_COUNTER:
|
522 |
if (hpet_enabled()) {
|
523 |
printf("qemu: Writing counter while HPET enabled!\n");
|
524 |
} |
525 |
s->hpet_counter = |
526 |
(s->hpet_counter & 0xffffffff00000000ULL) | value;
|
527 |
DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", |
528 |
value, s->hpet_counter); |
529 |
break;
|
530 |
case HPET_COUNTER + 4: |
531 |
if (hpet_enabled()) {
|
532 |
printf("qemu: Writing counter while HPET enabled!\n");
|
533 |
} |
534 |
s->hpet_counter = |
535 |
(s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); |
536 |
DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", |
537 |
value, s->hpet_counter); |
538 |
break;
|
539 |
default:
|
540 |
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
541 |
break;
|
542 |
} |
543 |
} |
544 |
} |
545 |
|
546 |
static CPUReadMemoryFunc * const hpet_ram_read[] = { |
547 |
#ifdef HPET_DEBUG
|
548 |
hpet_ram_readb, |
549 |
hpet_ram_readw, |
550 |
#else
|
551 |
NULL,
|
552 |
NULL,
|
553 |
#endif
|
554 |
hpet_ram_readl, |
555 |
}; |
556 |
|
557 |
static CPUWriteMemoryFunc * const hpet_ram_write[] = { |
558 |
#ifdef HPET_DEBUG
|
559 |
hpet_ram_writeb, |
560 |
hpet_ram_writew, |
561 |
#else
|
562 |
NULL,
|
563 |
NULL,
|
564 |
#endif
|
565 |
hpet_ram_writel, |
566 |
}; |
567 |
|
568 |
static void hpet_reset(void *opaque) |
569 |
{ |
570 |
HPETState *s = opaque; |
571 |
int i;
|
572 |
static int count = 0; |
573 |
|
574 |
for (i = 0; i < HPET_NUM_TIMERS; i++) { |
575 |
HPETTimer *timer = &s->timer[i]; |
576 |
|
577 |
hpet_del_timer(timer); |
578 |
timer->tn = i; |
579 |
timer->cmp = ~0ULL;
|
580 |
timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
581 |
/* advertise availability of ioapic inti2 */
|
582 |
timer->config |= 0x00000004ULL << 32; |
583 |
timer->state = s; |
584 |
timer->period = 0ULL;
|
585 |
timer->wrap_flag = 0;
|
586 |
} |
587 |
|
588 |
s->hpet_counter = 0ULL;
|
589 |
s->hpet_offset = 0ULL;
|
590 |
/* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
|
591 |
s->capability = 0x8086a201ULL;
|
592 |
s->capability |= ((HPET_CLK_PERIOD) << 32);
|
593 |
s->config = 0ULL;
|
594 |
if (count > 0) { |
595 |
/* we don't enable pit when hpet_reset is first called (by hpet_init)
|
596 |
* because hpet is taking over for pit here. On subsequent invocations,
|
597 |
* hpet_reset is called due to system reset. At this point control must
|
598 |
* be returned to pit until SW reenables hpet.
|
599 |
*/
|
600 |
hpet_pit_enable(); |
601 |
} |
602 |
count = 1;
|
603 |
} |
604 |
|
605 |
|
606 |
void hpet_init(qemu_irq *irq)
|
607 |
{ |
608 |
int i, iomemtype;
|
609 |
HPETTimer *timer; |
610 |
HPETState *s; |
611 |
|
612 |
DPRINTF ("hpet_init\n");
|
613 |
|
614 |
s = qemu_mallocz(sizeof(HPETState));
|
615 |
hpet_statep = s; |
616 |
s->irqs = irq; |
617 |
for (i = 0; i < HPET_NUM_TIMERS; i++) { |
618 |
timer = &s->timer[i]; |
619 |
timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); |
620 |
} |
621 |
vmstate_register(-1, &vmstate_hpet, s);
|
622 |
qemu_register_reset(hpet_reset, s); |
623 |
/* HPET Area */
|
624 |
iomemtype = cpu_register_io_memory(hpet_ram_read, |
625 |
hpet_ram_write, s); |
626 |
cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
|
627 |
} |