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/*
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 * ACPI implementation
3
 *
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 * Copyright (c) 2006 Fabrice Bellard
5
 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License version 2 as published by the Free Software Foundation.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>
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 */
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#include "hw.h"
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#include "pc.h"
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#include "apm.h"
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#include "pm_smbus.h"
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#include "pci.h"
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#include "acpi.h"
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#include "sysemu.h"
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#include "range.h"
26

    
27
//#define DEBUG
28

    
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
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#else
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# define PIIX4_DPRINTF(format, ...)     do { } while (0)
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#endif
34

    
35
#define ACPI_DBG_IO_ADDR  0xb044
36

    
37
#define GPE_BASE 0xafe0
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#define PCI_BASE 0xae00
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#define PCI_EJ_BASE 0xae08
40

    
41
#define PIIX4_PCI_HOTPLUG_STATUS 2
42

    
43
struct gpe_regs {
44
    uint16_t sts; /* status */
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    uint16_t en;  /* enabled */
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};
47

    
48
struct pci_status {
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    uint32_t up;
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    uint32_t down;
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};
52

    
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typedef struct PIIX4PMState {
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    PCIDevice dev;
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    IORange ioport;
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    uint16_t pmsts;
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    uint16_t pmen;
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    uint16_t pmcntrl;
59

    
60
    APMState apm;
61

    
62
    QEMUTimer *tmr_timer;
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    int64_t tmr_overflow_time;
64

    
65
    PMSMBus smb;
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    uint32_t smb_io_base;
67

    
68
    qemu_irq irq;
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    qemu_irq cmos_s3;
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    qemu_irq smi_irq;
71
    int kvm_enabled;
72

    
73
    /* for pci hotplug */
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    struct gpe_regs gpe;
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    struct pci_status pci0_status;
76
} PIIX4PMState;
77

    
78
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
79

    
80
#define ACPI_ENABLE 0xf1
81
#define ACPI_DISABLE 0xf0
82

    
83
static uint32_t get_pmtmr(PIIX4PMState *s)
84
{
85
    uint32_t d;
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    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
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    return d & 0xffffff;
88
}
89

    
90
static int get_pmsts(PIIX4PMState *s)
91
{
92
    int64_t d;
93

    
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    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
95
                 get_ticks_per_sec());
96
    if (d >= s->tmr_overflow_time)
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        s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
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    return s->pmsts;
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}
100

    
101
static void pm_update_sci(PIIX4PMState *s)
102
{
103
    int sci_level, pmsts;
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    int64_t expire_time;
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106
    pmsts = get_pmsts(s);
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    sci_level = (((pmsts & s->pmen) &
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                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
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                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
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                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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                   ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
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        (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
113

    
114
    qemu_set_irq(s->irq, sci_level);
115
    /* schedule a timer interruption if needed */
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    if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
117
        !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
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        expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
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                               PM_TIMER_FREQUENCY);
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        qemu_mod_timer(s->tmr_timer, expire_time);
121
    } else {
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        qemu_del_timer(s->tmr_timer);
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    }
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}
125

    
126
static void pm_tmr_timer(void *opaque)
127
{
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    PIIX4PMState *s = opaque;
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    pm_update_sci(s);
130
}
131

    
132
static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
133
                            uint64_t val)
134
{
135
    PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
136

    
137
    if (width != 2) {
138
        PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
139
                      (unsigned)addr, width, (unsigned)val);
140
    }
141

    
142
    switch(addr) {
143
    case 0x00:
144
        {
145
            int64_t d;
146
            int pmsts;
147
            pmsts = get_pmsts(s);
148
            if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
149
                /* if TMRSTS is reset, then compute the new overflow time */
150
                d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
151
                             get_ticks_per_sec());
152
                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
153
            }
154
            s->pmsts &= ~val;
155
            pm_update_sci(s);
156
        }
157
        break;
158
    case 0x02:
159
        s->pmen = val;
160
        pm_update_sci(s);
161
        break;
162
    case 0x04:
163
        {
164
            int sus_typ;
165
            s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
166
            if (val & ACPI_BITMASK_SLEEP_ENABLE) {
167
                /* change suspend type */
168
                sus_typ = (val >> 10) & 7;
169
                switch(sus_typ) {
170
                case 0: /* soft power off */
171
                    qemu_system_shutdown_request();
172
                    break;
173
                case 1:
174
                    /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
175
                       Pretend that resume was caused by power button */
176
                    s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
177
                                 ACPI_BITMASK_POWER_BUTTON_STATUS);
178
                    qemu_system_reset_request();
179
                    if (s->cmos_s3) {
180
                        qemu_irq_raise(s->cmos_s3);
181
                    }
182
                default:
183
                    break;
184
                }
185
            }
186
        }
187
        break;
188
    default:
189
        break;
190
    }
191
    PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
192
}
193

    
194
static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
195
                            uint64_t *data)
196
{
197
    PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
198
    uint32_t val;
199

    
200
    switch(addr) {
201
    case 0x00:
202
        val = get_pmsts(s);
203
        break;
204
    case 0x02:
205
        val = s->pmen;
206
        break;
207
    case 0x04:
208
        val = s->pmcntrl;
209
        break;
210
    case 0x08:
211
        val = get_pmtmr(s);
212
        break;
213
    default:
214
        val = 0;
215
        break;
216
    }
217
    PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
218
    *data = val;
219
}
220

    
221
static const IORangeOps pm_iorange_ops = {
222
    .read = pm_ioport_read,
223
    .write = pm_ioport_write,
224
};
225

    
226
static void apm_ctrl_changed(uint32_t val, void *arg)
227
{
228
    PIIX4PMState *s = arg;
229

    
230
    /* ACPI specs 3.0, 4.7.2.5 */
231
    if (val == ACPI_ENABLE) {
232
        s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
233
    } else if (val == ACPI_DISABLE) {
234
        s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
235
    }
236

    
237
    if (s->dev.config[0x5b] & (1 << 1)) {
238
        if (s->smi_irq) {
239
            qemu_irq_raise(s->smi_irq);
240
        }
241
    }
242
}
243

    
244
static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
245
{
246
    PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
247
}
248

    
249
static void pm_io_space_update(PIIX4PMState *s)
250
{
251
    uint32_t pm_io_base;
252

    
253
    if (s->dev.config[0x80] & 1) {
254
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
255
        pm_io_base &= 0xffc0;
256

    
257
        /* XXX: need to improve memory and ioport allocation */
258
        PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
259
        iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
260
        ioport_register(&s->ioport);
261
    }
262
}
263

    
264
static void pm_write_config(PCIDevice *d,
265
                            uint32_t address, uint32_t val, int len)
266
{
267
    pci_default_write_config(d, address, val, len);
268
    if (range_covers_byte(address, len, 0x80))
269
        pm_io_space_update((PIIX4PMState *)d);
270
}
271

    
272
static int vmstate_acpi_post_load(void *opaque, int version_id)
273
{
274
    PIIX4PMState *s = opaque;
275

    
276
    pm_io_space_update(s);
277
    return 0;
278
}
279

    
280
static const VMStateDescription vmstate_gpe = {
281
    .name = "gpe",
282
    .version_id = 1,
283
    .minimum_version_id = 1,
284
    .minimum_version_id_old = 1,
285
    .fields      = (VMStateField []) {
286
        VMSTATE_UINT16(sts, struct gpe_regs),
287
        VMSTATE_UINT16(en, struct gpe_regs),
288
        VMSTATE_END_OF_LIST()
289
    }
290
};
291

    
292
static const VMStateDescription vmstate_pci_status = {
293
    .name = "pci_status",
294
    .version_id = 1,
295
    .minimum_version_id = 1,
296
    .minimum_version_id_old = 1,
297
    .fields      = (VMStateField []) {
298
        VMSTATE_UINT32(up, struct pci_status),
299
        VMSTATE_UINT32(down, struct pci_status),
300
        VMSTATE_END_OF_LIST()
301
    }
302
};
303

    
304
static const VMStateDescription vmstate_acpi = {
305
    .name = "piix4_pm",
306
    .version_id = 2,
307
    .minimum_version_id = 1,
308
    .minimum_version_id_old = 1,
309
    .post_load = vmstate_acpi_post_load,
310
    .fields      = (VMStateField []) {
311
        VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
312
        VMSTATE_UINT16(pmsts, PIIX4PMState),
313
        VMSTATE_UINT16(pmen, PIIX4PMState),
314
        VMSTATE_UINT16(pmcntrl, PIIX4PMState),
315
        VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
316
        VMSTATE_TIMER(tmr_timer, PIIX4PMState),
317
        VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
318
        VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
319
        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
320
                       struct pci_status),
321
        VMSTATE_END_OF_LIST()
322
    }
323
};
324

    
325
static void piix4_reset(void *opaque)
326
{
327
    PIIX4PMState *s = opaque;
328
    uint8_t *pci_conf = s->dev.config;
329

    
330
    pci_conf[0x58] = 0;
331
    pci_conf[0x59] = 0;
332
    pci_conf[0x5a] = 0;
333
    pci_conf[0x5b] = 0;
334

    
335
    if (s->kvm_enabled) {
336
        /* Mark SMM as already inited (until KVM supports SMM). */
337
        pci_conf[0x5B] = 0x02;
338
    }
339
}
340

    
341
static void piix4_powerdown(void *opaque, int irq, int power_failing)
342
{
343
    PIIX4PMState *s = opaque;
344

    
345
    if (!s) {
346
        qemu_system_shutdown_request();
347
    } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
348
        s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
349
        pm_update_sci(s);
350
    }
351
}
352

    
353
static int piix4_pm_initfn(PCIDevice *dev)
354
{
355
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
356
    uint8_t *pci_conf;
357

    
358
    pci_conf = s->dev.config;
359
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
360
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
361
    pci_conf[0x06] = 0x80;
362
    pci_conf[0x07] = 0x02;
363
    pci_conf[0x08] = 0x03; // revision number
364
    pci_conf[0x09] = 0x00;
365
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
366
    pci_conf[0x3d] = 0x01; // interrupt pin 1
367

    
368
    pci_conf[0x40] = 0x01; /* PM io base read only bit */
369

    
370
    /* APM */
371
    apm_init(&s->apm, apm_ctrl_changed, s);
372

    
373
    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
374

    
375
    if (s->kvm_enabled) {
376
        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
377
         * support SMM mode. */
378
        pci_conf[0x5B] = 0x02;
379
    }
380

    
381
    /* XXX: which specification is used ? The i82731AB has different
382
       mappings */
383
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
384
    pci_conf[0x63] = 0x60;
385
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
386
        (serial_hds[1] != NULL ? 0x90 : 0);
387

    
388
    pci_conf[0x90] = s->smb_io_base | 1;
389
    pci_conf[0x91] = s->smb_io_base >> 8;
390
    pci_conf[0xd2] = 0x09;
391
    register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
392
    register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
393

    
394
    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
395

    
396
    qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
397

    
398
    pm_smbus_init(&s->dev.qdev, &s->smb);
399
    qemu_register_reset(piix4_reset, s);
400
    piix4_acpi_system_hot_add_init(dev->bus, s);
401

    
402
    return 0;
403
}
404

    
405
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
406
                       qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
407
                       int kvm_enabled)
408
{
409
    PCIDevice *dev;
410
    PIIX4PMState *s;
411

    
412
    dev = pci_create(bus, devfn, "PIIX4_PM");
413
    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
414

    
415
    s = DO_UPCAST(PIIX4PMState, dev, dev);
416
    s->irq = sci_irq;
417
    s->cmos_s3 = cmos_s3;
418
    s->smi_irq = smi_irq;
419
    s->kvm_enabled = kvm_enabled;
420

    
421
    qdev_init_nofail(&dev->qdev);
422

    
423
    return s->smb.smbus;
424
}
425

    
426
static PCIDeviceInfo piix4_pm_info = {
427
    .qdev.name          = "PIIX4_PM",
428
    .qdev.desc          = "PM",
429
    .qdev.size          = sizeof(PIIX4PMState),
430
    .qdev.vmsd          = &vmstate_acpi,
431
    .init               = piix4_pm_initfn,
432
    .config_write       = pm_write_config,
433
    .qdev.props         = (Property[]) {
434
        DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
435
        DEFINE_PROP_END_OF_LIST(),
436
    }
437
};
438

    
439
static void piix4_pm_register(void)
440
{
441
    pci_qdev_register(&piix4_pm_info);
442
}
443

    
444
device_init(piix4_pm_register);
445

    
446
static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
447
{
448
    if (addr & 1)
449
        return (val >> 8) & 0xff;
450
    return val & 0xff;
451
}
452

    
453
static uint32_t gpe_readb(void *opaque, uint32_t addr)
454
{
455
    uint32_t val = 0;
456
    PIIX4PMState *s = opaque;
457
    struct gpe_regs *g = &s->gpe;
458

    
459
    switch (addr) {
460
        case GPE_BASE:
461
        case GPE_BASE + 1:
462
            val = gpe_read_val(g->sts, addr);
463
            break;
464
        case GPE_BASE + 2:
465
        case GPE_BASE + 3:
466
            val = gpe_read_val(g->en, addr);
467
            break;
468
        default:
469
            break;
470
    }
471

    
472
    PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
473
    return val;
474
}
475

    
476
static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
477
{
478
    if (addr & 1)
479
        *cur = (*cur & 0xff) | (val << 8);
480
    else
481
        *cur = (*cur & 0xff00) | (val & 0xff);
482
}
483

    
484
static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
485
{
486
    uint16_t x1, x0 = val & 0xff;
487
    int shift = (addr & 1) ? 8 : 0;
488

    
489
    x1 = (*cur >> shift) & 0xff;
490

    
491
    x1 = x1 & ~x0;
492

    
493
    *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
494
}
495

    
496
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
497
{
498
    PIIX4PMState *s = opaque;
499
    struct gpe_regs *g = &s->gpe;
500

    
501
    switch (addr) {
502
        case GPE_BASE:
503
        case GPE_BASE + 1:
504
            gpe_reset_val(&g->sts, addr, val);
505
            break;
506
        case GPE_BASE + 2:
507
        case GPE_BASE + 3:
508
            gpe_write_val(&g->en, addr, val);
509
            break;
510
        default:
511
            break;
512
    }
513

    
514
    pm_update_sci(s);
515

    
516
    PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
517
}
518

    
519
static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
520
{
521
    uint32_t val = 0;
522
    struct pci_status *g = opaque;
523
    switch (addr) {
524
        case PCI_BASE:
525
            val = g->up;
526
            break;
527
        case PCI_BASE + 4:
528
            val = g->down;
529
            break;
530
        default:
531
            break;
532
    }
533

    
534
    PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
535
    return val;
536
}
537

    
538
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
539
{
540
    struct pci_status *g = opaque;
541
    switch (addr) {
542
        case PCI_BASE:
543
            g->up = val;
544
            break;
545
        case PCI_BASE + 4:
546
            g->down = val;
547
            break;
548
   }
549

    
550
    PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
551
}
552

    
553
static uint32_t pciej_read(void *opaque, uint32_t addr)
554
{
555
    PIIX4_DPRINTF("pciej read %x\n", addr);
556
    return 0;
557
}
558

    
559
static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
560
{
561
    BusState *bus = opaque;
562
    DeviceState *qdev, *next;
563
    PCIDevice *dev;
564
    int slot = ffs(val) - 1;
565

    
566
    QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
567
        dev = DO_UPCAST(PCIDevice, qdev, qdev);
568
        if (PCI_SLOT(dev->devfn) == slot) {
569
            qdev_free(qdev);
570
        }
571
    }
572

    
573

    
574
    PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
575
}
576

    
577
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
578
                                PCIHotplugState state);
579

    
580
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
581
{
582
    struct pci_status *pci0_status = &s->pci0_status;
583

    
584
    register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
585
    register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);
586

    
587
    register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
588
    register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
589

    
590
    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
591
    register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
592

    
593
    pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
594
}
595

    
596
static void enable_device(PIIX4PMState *s, int slot)
597
{
598
    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
599
    s->pci0_status.up |= (1 << slot);
600
}
601

    
602
static void disable_device(PIIX4PMState *s, int slot)
603
{
604
    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
605
    s->pci0_status.down |= (1 << slot);
606
}
607

    
608
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
609
                                PCIHotplugState state)
610
{
611
    int slot = PCI_SLOT(dev->devfn);
612
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
613
                                DO_UPCAST(PCIDevice, qdev, qdev));
614

    
615
    /* Don't send event when device is enabled during qemu machine creation:
616
     * it is present on boot, no hotplug event is necessary. We do send an
617
     * event when the device is disabled later. */
618
    if (state == PCI_COLDPLUG_ENABLED) {
619
        return 0;
620
    }
621

    
622
    s->pci0_status.up = 0;
623
    s->pci0_status.down = 0;
624
    if (state == PCI_HOTPLUG_ENABLED) {
625
        enable_device(s, slot);
626
    } else {
627
        disable_device(s, slot);
628
    }
629

    
630
    pm_update_sci(s);
631

    
632
    return 0;
633
}