Archipelago » qemu

    c[0x3c] = 0x00;      /* intr_ln interrupt line rw */

    c[0x3d] = 0x01;      /* intr_pn interrupt pin ro */

    register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s);

    qemu_register_reset (ac97_on_reset, 0, s);

    AUD_register_card ("ac97", &s->card);

    /* memory #0 LFB */

    /* memory #1 memory-mapped I/O */

    /* XXX: s->vga.vram_size must be a power of two */

			   PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);

    if (device_id == CIRRUS_ID_CLGD5446) {

                               PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);

    }

    /* XXX: ROM BIOS */

    d->mmio_index = cpu_register_io_memory(e1000_mmio_read,

            e1000_mmio_write, d);

                           PCI_ADDRESS_SPACE_MEM, e1000_mmio_map);

                           PCI_ADDRESS_SPACE_IO, ioport_map);

    memmove(d->eeprom_data, e1000_eeprom_template,

    d->eepro100.mmio_index =

        cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);

                           PCI_ADDRESS_SPACE_MEM |

                           PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map);

                           pci_map);

                           pci_mmio_map);

    qdev_get_macaddr(&d->dev.qdev, s->macaddr);

    s = &d->es1370;

    s->pci_dev = &d->dev;

    register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);

    qemu_register_reset (es1370_on_reset, 0, s);

        pci_conf[0x51] |= 0x08; /* enable IDE1 */

    }

                           PCI_ADDRESS_SPACE_IO, ide_map);

                           PCI_ADDRESS_SPACE_IO, ide_map);

                           PCI_ADDRESS_SPACE_IO, ide_map);

                           PCI_ADDRESS_SPACE_IO, ide_map);

                           PCI_ADDRESS_SPACE_IO, bmdma_map);

    pci_conf[0x3d] = 0x01; // interrupt on pin 1

    qemu_register_reset(piix3_reset, 0, d);

    piix3_reset(d);

                           PCI_ADDRESS_SPACE_IO, bmdma_map);

    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);

    qemu_register_reset(piix3_reset, 0, d);

    piix3_reset(d);

                           PCI_ADDRESS_SPACE_IO, bmdma_map);

    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);

    s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn,

                                            lsi_ram_writefn, s);

                           PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);

                           PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);

                           PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);

    s->queue = qemu_malloc(sizeof(lsi_queue));

    s->queue_len = 1;

    d->config[0x3d] = 0x01; // interrupt on pin 1

                           PCI_ADDRESS_SPACE_MEM, macio_map);

}

    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

    pci_conf[0x3d] = 1; // interrupt pin 0

                           PCI_ADDRESS_SPACE_IO, ne2000_map);

    s = &d->ne2000;

    s->irq = d->dev.irq[0];

        pci_conf[0x3d] = 0x00; // no interrupt pin

        /* Register I/O spaces */

                               PCI_ADDRESS_SPACE_MEM, &openpic_map);

    } else {

        opp = qemu_mallocz(sizeof(openpic_t));

    return 0;

}

                            uint32_t size, int type,

                            PCIMapIORegionFunc *map_func)

{

                               PCIConfigWriteFunc *config_write);

int pci_unregister_device(PCIDevice *pci_dev);

                            uint32_t size, int type,

                            PCIMapIORegionFunc *map_func);

    s->mmio_index =

      cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state);

                           PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);

                           PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);

    s->irq = pci_dev->irq[0];

    s->rtl8139_mmio_io_addr =

    cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s);

                           PCI_ADDRESS_SPACE_IO,  rtl8139_ioport_map);

                           PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);

    s->pci_dev = (PCIDevice *)d;

    s->config[0x0D] = 0x0a; // latency_timer

    s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

                           ebus_mmio_mapfunc);

                           ebus_mmio_mapfunc);

}

    usb_ohci_init(&ohci->state, num_ports, devfn, ohci->pci_dev.irq[0],

                  OHCI_TYPE_PCI, ohci->pci_dev.name, 0);

                           PCI_ADDRESS_SPACE_MEM, ohci_mapfunc);

}

    /* Use region 4 for consistency with real hardware.  BSD guests seem

       to rely on this.  */

                           PCI_ADDRESS_SPACE_IO, uhci_map);

    register_savevm("uhci", 0, 1, uhci_save, uhci_load, s);

    /* Use region 4 for consistency with real hardware.  BSD guests seem

       to rely on this.  */

                           PCI_ADDRESS_SPACE_IO, uhci_map);

    register_savevm("uhci", 0, 1, uhci_save, uhci_load, s);

    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

    /* XXX: VGA_RAM_SIZE must be a power of two */

                           PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);

    if (vga_bios_size != 0) {

        unsigned int bios_total_size;

        bios_total_size = 1;

        while (bios_total_size < vga_bios_size)

            bios_total_size <<= 1;

                               PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);

    }

    return 0;

    if (size & (size-1))

        size = 1 << qemu_fls(size);

                           virtio_map);

    virtio_bind_device(vdev, &virtio_pci_bindings, proxy);

    s->card.config[0x2f]		= SVGA_PCI_DEVICE_ID >> 8;

    s->card.config[0x3c]		= 0xff;		/* End */

                    PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);

                    PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);

    vmsvga_init(&s->chip, VGA_RAM_SIZE);

    pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER);

    pci_conf[0x0e] = 0x00;

                            PCI_ADDRESS_SPACE_MEM, i6300esb_map);

    register_savevm("i6300esb_wdt", -1, sizeof(I6300State),