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target-arm: Set carry flag correctly for Thumb2 ORNS
The code for Thumb2 ORNS (or negated and set flags) was trashinga TCG input register which was needed later for use in calculatingflags, with the effect that the carry flag was always set withthe wrong sense. Fix this by using the TCG orc op instead of...
target-arm: Handle VMOV between two core and VFP single regs
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry andVMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and apair of VFP single precision registers):
target-arm: Don't decode old cp15 WFI instructions on v7 cores
In v7 of the ARM architecture, WFI (wait for interrupt) is a first-classinstruction, but in previous versions this functionality was providedvia a cp15 coprocessor register. Add correct feature checks to the...
target-arm: Fix shift by immediate and narrow where src, dest overlap
For Neon shifts by immediate and narrow, correctly handle the casewhere the source registers and the destination registers overlap(the second pass should use the original register contents, not the...
target-arm: Refactor to pull narrowing decode into separate function
Pull the code which decodes narrowing operations as being eithersigned/unsigned saturate or plain out into its own function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix Neon VQSHRN and VSHRN.
Call the normal shift helpers instead of the rounding ones.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix decoding of Neon 64 bit shifts.
Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN,VQRSHRN, VQRSHRUN, taking into account whether inputs are unsignedor not.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Move Neon VZIP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inlinecode to helper functions. (At 50+ TCG ops it was well over therecommended limit for coding inline.) The helper implementations alsogive the correct answers where the inline implementation did not....
target-arm: Move Neon VUZP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inlinecode to helper functions. (At 50+ TCG ops it was well over therecommended limit for coding inline.) The helper implementations alsofix the handling of the quadword version of the instruction....
target-arm: Correct conversion of Thumb Neon dp encodings into ARM
We handle Thumb Neon data processing instructions by converting theminto the equivalent ARM encoding, as the two are very close. Howeverthe ARM encoding should have bit 28 set, not clear. This wasn't causing...
target-arm: Fix Neon VQDMLSL instruction
For VQDMLSL, negation has to occur after saturation, not before.
target-arm: Refactor handling of VQDMULL
Refactor the handling of VQDMULL so that it is dealt with inits own if() case rather than together with the accumulatinginstructions.
target-arm: Implement VMULL.P8
Implement VMULL.P8 (the 32x32->64 version of the polynomial multiplyinstruction).
target-arm: Use standard FPSCR for Neon half-precision operations
The Neon half-precision conversion operations (VCVT.F16.F32 andVCVT.F32.F16) use ARM standard floating-point arithmetic, unlikethe VFP versions (VCVTB and VCVTT).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: implement vsli.64, vsri.64
target-arm: fix VSHLL Neon instruction.
Fix bit mask used when widening the result of shift on narrow input.
target-arm: Fix VQMOVUN Neon instruction.
VQMOVUN does a signed-to-unsigned saturating conversion. This isdifferent from both the signed-to-signed and unsigned-to-unsignedconversions already implemented, so we need a new set of helperfunctions (neon_unarrow_sat*)....
target-arm: Fix decoding of preload and memory hint space
Correct the decoding of the ARM preload and memory hint space,by adding decoding of PLI, PLDW and the v7MP unallocated hintspace. This commit also corrects a slightly overexuberantdecoding of PLD which was not checking that bit 4...
target-arm: Fix decoding of Thumb preload and hint space
Refine the decoding of the Thumb preload and hint space, so weUNDEF on the patterns that are supposed to UNDEF rather than NOP.We also move the tests for this space earlier, so we don't emitharmless but unnecessary address generation code for preload...
Set the right overflow bit for neon 32 and 64 bit saturating add/sub.
target-arm: Fix Neon vsra instructions.
This patch fixes the errors reported by my tests in VSRA.
Support saturation with shift=0.
This patch fixes corner-case saturations, when the target range iszero. It merely removes the guard against (sh == 0), and makes:_ssat(0x87654321, 1) return 0xffffffff and set the saturation flag_usat(0x87654321, 0) return 0 and set the saturation flag...
target-arm: Fix garbage collection of temporaries in Neon emulation.
Fix garbage collection of temporaries in Neon emulation.
target-arm: Fix loading of scalar value for Neon multiply-by-scalar
Fix the register and part of register we get the scalar from inthe various "multiply vector by scalar" ops (VMUL by scalarand friends).
target-arm: Log instruction start in TCG code
Add support for logging the start of instructions in TCGcode debug dumps for ARM targets.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
target-arm: Translate with VFP-enabled from TB flags, not CPUState
When translating code, whether the VFP unit is enabled for this TBis stored in a bit in the TB flags. Use this rather than incorrectlyreading the FPEXC from the CPUState passed to translation....
target-arm: Translate with VFP len/stride from TB flags, not CPUState
When translating, the VFP vector length and stride for this TB are encodedin the TB flags; the CPUState copies may be different and must not be used.
target-arm: Translate with Thumb state from TB flags, not CPUState
The Thumb/ARM state for the TB being translated should come fromthe TB flags, not the CPUState.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>...
target-arm: Translate with condexec bits from TB flags, not CPUState
When translating, the condexec bits for the TB are in the TB flags;the CPUState condexec bits may be different.
This patch fixes https://bugs.launchpad.net/bugs/604872 where we mightsegfault if we took an exception in the middle of a TB with an IT...
target-arm: Translate with user-state from TB flags, not CPUState
When translating, get the user/priv state from the TB flags, notthe CPUState.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Remove redundant setting of IT bits before Thumb SWI
Remove a redundant call to gen_set_condexec() in the translation of Thumbmode SWI. (SWI and WFI generate "exceptions" which happen after theexecution of the instruction, ie when PC and IT bits have updated....
target-arm: Refactor translation of exception generating instructions
Create a new function which does the common sequence of gen_set_condexec,gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.
target-arm: Restore IT bits when resuming after an exception
We were not correctly restoring the IT bits when resuming executionafter taking an unexpected exception in the middle of an IT block.Fix this by tracking them along with PC changes and restoring in...
target-arm: Don't generate code specific to current CPU mode for SRS
When translating the SRS instruction, handle the "store registersto stack of current mode" case in the helper function rather thaninline. This means the generated code does not make assumptions...
ARM: Fix decoding of VQSHL/VQSHLU immediate forms
Fix errors in the decoding of ARM VQSHL/VQSHLU immediate forms,including using the new VQSHLU helper functions where appropriate.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix SMMLA/SMMLS instructions
SMMLA and SMMLS are broken on both in normal and thumb mode, that isboth (different) implementations are wrong. They try to avoid a 64-bitadd for the rounding, which is not trivial if you want to support bothSMMLA and SMMLS with the same code....
target-arm: fix UMAAL instruction
UMAAL should use unsigned multiply instead of signed.
This patch fixes this issue by handling UMAAL separately fromUMULL/UMLAL/SMULL/SMLAL as these instructions are differentenough. It also explicitly list instructions in case and catch...
target-arm: Fix arguments passed to VQSHL helpers
Correct the arguments passed when generating neon qshl_{u,s}64()helpers so that we use the correct registers.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix bug in translation of REVSH
The translation of REVSH shifted the low byte 8 steps left before performingan 8-bit sign extend, causing this part of the expression to alwas be 0.
Reported-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM: fix ldrexd/strexd
Correct ldrexd and strexd code to always read and write thehigh word of the 64-bit value from addr+4.Also make ldrexd and strexd agree that for a 64 bit value theaddress in env->exclusive_addr is that of the low word.
This fixes the issues reported in...
ARM: Fix decoding of VFP forms of VCVT between float and int/fixed
Correct the decoding of source and destination registersfor the VFP forms of the VCVT instructions which convertbetween floating point and integer or fixed-point.
ARM: Fix decoding of Neon forms of VCVT between float and fixed point
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted...
ARM: Fix sense of to_integer bit in Neon VCVT float/int conversion
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
target-arm: Add support for PKHxx in thumb2
The PKHxx instructions were not recognized by the thumb2 decoder. Thesolution provided in this changeset is identical to the arm-modeimplementation.
Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Fix mixup in decoding of saturating add and sub
The thumb2 decoder contained a mixup between the bit controllingdoubling and the bit controlling if the operation was an add or a sub.
target-arm: Handle 'smc' as an undefined instruction
Refine check on bkpt so that smc and undefined instruction encodings arehandled as an undefined instruction and trap.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-arm : fix thumb2 parallel add/sub opcode decoding
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
NEON vldN optimization
When combining multiple values as part of a NEON array load, do explcitshift/or rather than using gen_bfi. This voids redundant maskoperations.
Signed-off-by: Paul Brook <paul@codesourcery.com>
arm: remove dead assignments, spotted by clang analyzer
Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: fix neon vmon/vmvn with modified immediate
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com>Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: resource leak fixes for iwmmxt disassemble
This patch fixes few resource leaks in the iwmmxt disassemble.
Signed-off-by: Lars Munch <lars@segv.dk>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix handling of AL condition in IT instruction
Do not try to insert a conditional jump over next instruction when thecondition code is AL as this will trigger an internal error.
Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: make RFE usable with any register
The rfe instruction can be used with any register, not just sp. Adjust thecondition check accordingly.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix missing 'return' in SRS handling.
There's a return missing in the srs handling which leads to srs always beingtreated an an invalid op.
target-arm: neon vshll instruction fix
implementation only widened the 32bit source vector elements into a64bit destination vector but forgot to perform the actual shiftingoperation.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Riku Voipio <riku.voipio@nokia.com>...
target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN
The rounding/truncating options were inverted. truncatingwas done when rounding was meant and vice verse.
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
ARM CP15 tls fix
Fix temporary handling in cp15 tls register load/store.
target-arm: implement Thumb-2 exception return
Support the "subs pc, lr" Thumb-2 exception return instruction.
Signed-off-by: Rabin Vincent <rabin@rab.in>Signed-off-by: Paul Brook <paul@codesourcery.com>
target-arm: fix thumb CPS
The Thumb CPS currently does not work correctly: CPSID touches more bitsthan the instruction wants to, and CPSIE does nothing. Fix it bypassing the correct mask (the "affect" bits) and value.
Signed-off-by: Rabin Vincent <rabin@rab.in>
target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of witha slow helper. If the the cp15 read/write was not TLS register access,fall back to the cp15 helper.
This makes accessing __thread variables in linux-user when apps are compiled...
target-arm: fix strexd
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.
ARM FP16 support
Implement the ARM VFP half precision floating point extensions.
target-arm: use native tcg-ops for ror/bic/vorn
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix neon vshrn/vrshrn ops
In the existing code shift value is clobbered during the pass loop.This patch changes the code so that it stores the intermediateresult in the target neon register directly and eliminates the needto use a temporary to hold the intermediate value thus leaving the...
target-arm: add support for neon vld1.64/vst1.64 instructions
Add support for NEON vld1.64 and vst1.64 instructions. This patch isrevised to follow more closely the specification and raisesundefined exception if 64bit element size is used for vld2/vst2 or...
target-arm: allow modifying vfp fpexc en bit only
All other bits except for the EN in the VFP FPEXC register are definedas subarchitecture specific and real functionality for any of theother bits has not been implemented in QEMU. However, current codeallows modifying all bits in the VFP FPEXC register leading to...
target-arm: fix neon vsri, vshl and vsli ops
Shift by immediate value is incorrectly overwritten by a temporaryvariable in the processing of NEON vsri, vshl and vsli instructions.This patch has been revised to also include a fix for the specialcase where the code would previously try to shift an integer value...
target-arm: fix incorrect temporary variable freeing
tmp4 and tmp5 temporary variables are allocated using tcg_const_i32but incorrectly released using dead_tmp which will cause resourceleak tracking to report false leaks.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>...
target-arm: optimize thumb 32-bit multiply
Current implementation of thumb mul instruction is implemented as a32x32->64 multiply which then uses only 32 least significant bits ofthe result. Replace that with a simple 32x32->32 multiply.
target-arm: cleanup internal resource leaks
Revised patch for getting rid of tcg temporary variable leaks intarget-arm/translate.c. This version also includes the leak patch forgen_set_cpsr macro, now converted as a static inline function, which Isent earlier as a separate patch on top of this patch....
target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330ed
Use load_reg_var() instead of accessing cpu_R[rn] directly to generatecorrect code when rn = 15.
target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7
target-arm: remove cpu_T for ARM once and for all
Signed-off-by: Filip Navara <filip.navara@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: convert gen_lookup_tb not to use cpu_T
target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16helpers used fixed registers to return values. This patch replaces that withTCG code, so T0/T1 is no longer directly used by the helper functions....
target-arm: fix TANDC and TORC instructions
Uninitialized register was used instead of proper TCG variable.
target-arm: replace thumb usage of cpu_T registers by proper register allocations
The goal is eventually to get rid of all cpu_T register usage and to usejust short-lived tmp/tmp2 registers. This patch converts all the places wherecpu_T was used in the Thumb code and replaces it with explicit TCG register...
target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T
target-arm: convert disas_neon_data_insn and helpers not to use cpu_T
target-arm: convert disas_neon_ls_insn not to use cpu_T
target-arm: convert disas_dsp_insn not use cpu_T
target-arm: convert disas_iwmmxt_insn not to use cpu_T
target-arm: convert VFP not to use cpu_T
target-arm: use tcg_global_mem_new_i32 to allocate registers
Currently each read/write of ARM register involves a LD/ST TCG operation. Thispatch uses TCG memory-backed registers to represent the ARM register set. Withmemory-backed registers the LD/ST operations are transparently generated by TCG...
target-arm: get rid of temporary variable cache
The temporary variable cache in no longer need since tcg_temp_free was introduced.
target-arm: remove useless line that sets register that is never used again
target-arm: remove unused gen_movl_T2_reg function
target-arm: fix SRS/RFE instructions
The encoding of 'IA' and 'DB' conditions was swapped.SRS instruction must store banked SPSR instead of CPSR at the specific address.Missing 'return' statement at the end of RFE handling.Fixed write-back code to reference correct registers....
target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Update to a hopefully more future proof FSF address
Remove unused gen_bx_T0 function.
Signed-off-by: Filip Navara <filip.navara@gmail.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
fix ARMv7 data processing instructions
ARMv7 defines a new behavior for ARM data processing instructionscompared to earlier architecture revisions; when the destinationregister is R15, a Branch and Exchange operation is executed ratherthan a simple Branch to the target address. This patch corrects the...
Modernize parts of target-arm/translate.c in preparation for themodifications in the subsequent patch in this patch set. This is donein order to avoid writing new code to target-arm/translate.c thatwould use deprecated methods and/or variables....
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
Fix ARM quadword VDUP (core register).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...